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SPU Loads and Cold Calls During a DMA2 List

Measures SPU loads, calls into cold cache lines, multiply and divide reads, and RAM loads and stores, alone and while DMA2 walks a list.

SPU Loads and Cold Calls During a DMA2 List
MachineSCPH-5501
Programfollowup22

This is an old revision of this page, as edited by RemmyLee at 05:40, 23 October 2026. Edit this revision | Latest revision

Overview

Each row is a loop of turns built in RAM and run from the instruction cache after a warm call. Root counter 2 counts system clock cycles across the loop, and the program reads it with loads only. A row runs once alone and once straight after DMA2 starts a list, and the pair is repeated. L0 is a list of 1024 empty nodes. L2 is an ordering table of 1024 nodes laid out as the one the BIOS sends during its start-up logo, with GP0 NOP words in the four nodes that carry words.1

For each list a row prints three figures: the cycles of the row, the node DMA2 had reached when the row ended, and the cycles from the start of the list until CHCR bit 24 read clear. The last figure shows how much the CPU's accesses held back the list.1

Table 1: Groups
Tag Turn of the loop
SPW 16 loads, each with 2 NOPs: k SPU halfword loads, k RAM loads or k RAM halfword stores, the rest scratchpad loads
SNP One SPU halfword load and n NOPs (n 0 to 14)
UA4 A RAM load, its use, g NOPs (g 0 to 6), a second RAM load, NOPs to 16 words
JRC Two calls of a two-word routine by jal, jalr or jr, into one warm line or two lines that evict each other
MDS divu or multu, 2 NOPs, mflo, a RAM load, and the same turn with parts left out
K3P One RAM load and p NOPs (p 4 to 17), three times each
LHS A RAM halfword store, k NOPs (0 or 2), a halfword load at 0, 2, 8 or 40h bytes from it
ALT A RAM store or load, 0 or 2 NOPs, a read of root counter 2 saved each turn, alone only
IOP Two halfword reads of root counter 2 back to back, the first at word w of a cache line, alone only

See also:

Results

SPU Loads

An SPU halfword load costs about 19 cycles more than a scratchpad load. With 16 SPU loads in each turn, 8 turns took 2,882 cycles alone against 471 with none, which is (2,882 - 471) / 128 = 18.8 cycles a load. A RAM load cost about 6 cycles more than a scratchpad load, and a RAM store cost nothing alone at any k.1

Table 2: Cycles for 8 turns alone and from the start of L0 to its end by the number k of loads or stores of each kind (first pair of each row)
k SPU load alone SPU load, L0 end RAM load alone RAM load, L0 end RAM store alone RAM store, L0 end
0 471 10,585 471 10,581 471 10,580
1 623 10,706 519 10,599 471 10,600
2 779 10,813 570 10,610 471 10,622
4 1,079 11,061 667 10,649 471 10,689
8 1,687 11,530 870 10,709 471 10,776
16 2,882 12,536 1,236 10,835 471 10,966

The list ends later in step with the number of SPU loads. With 128 SPU loads during it, L0 ended 1,951 cycles later than with none, about 15 cycles for each load, so the list waits while the CPU reads the SPU. The same 128 accesses to RAM delayed the end by 254 cycles for loads and 386 cycles for stores, so each RAM access held the list for about 2 or 3 cycles. On L2 each row took within 21 cycles of its L0 time, and L2 ended 12 to 56 cycles after L0.1

With one SPU load in each turn, 24 turns took 582 to 594 cycles alone with any number of NOPs from 0 to 14 after the load, which is about 24.5 cycles a turn. The NOPs therefore run in the time of the load itself, and the next turn's load waits for the one before it. During L0 the 24 turns took 811 to 835 cycles at every n.2

Calls Into Cold Lines

Two calls in each turn into lines that miss the instruction cache took about 1,600 cycles more over 100 turns than the same calls into a warm line. That is 8 cycles for each cold call, by jal, jalr or jr alike. The jalr and jr rows take 400 and 800 cycles more than jal even when warm. That is the time of the extra instructions in each turn: 4 that load the call address into t9 for jalr, and 8 that load t9 and ra for jr.3

Table 3: Cycles for 100 turns of two calls (first pair of each row)
Call Alone During L0 L0 end
jal, warm 1,165 1,260 10,575
jalr, warm 1,563 1,664 10,583
jr, warm 1,963 2,062 10,579
jal, cold 2,773 3,275 11,596
jalr, cold 3,167 4,212 11,593
jr, cold 3,590 4,335 11,690

During L0 the cold calls ended the list 1,010 to 1,111 cycles later than the warm calls, which is about 5 cycles for each of the 200 line fills. The cold rows themselves took 500 to 1,060 cycles more during the list than alone, while the warm rows took 95 to 106 more.3

Multiply and Divide

A divu followed by mflo waits for the result: 100 turns without the RAM load took 4,467 cycles, which is about 45 a turn. A RAM load after the mflo added 200 cycles alone, 2 a turn, after both divu and multu. Without the mflo neither divu nor multu added any time to the RAM load, and both rows took 1,270 cycles as the load alone did.4

Table 4: Cycles for 100 turns of divu or multu of 1000 by 7 (first pair of each row)
Turn divu alone divu during L0 multu alone multu during L0
All parts 4,667 4,618 1,667 1,689
No mflo 1,270 1,437 1,270 1,433
No RAM load 4,467 4,567 1,467 1,574
RAM load only 1,270 1,433 1,274 1,435

During L0 the full divu row took 4,618 and 4,624 cycles, which is 33 to 49 fewer than alone. The divu row without the load took 100 cycles more during L0 than alone.4

One RAM Load a Turn

Alone, each NOP after the load added 100 cycles over 100 turns from 4 NOPs to 17, which is one cycle a turn. During L0 the time stayed at about 1,436 cycles from 4 to 6 NOPs and was 1,515 to 1,529 at 7. From 8 NOPs on it ran above the alone time by 229 to 238 cycles at 8, 189 at 9, 181 to 190 at 10 and 136 to 164 from 11 to 17. The three runs at each p agreed within 15 cycles.5

Table 5: Cycles for 100 turns of one RAM load and p NOPs (run 1 and first pair)
p Alone During L0
4 1,068 1,437
5 1,172 1,436
6 1,267 1,436
7 1,363 1,521
8 1,464 1,702
9 1,563 1,752
10 1,663 1,844
12 1,863 2,012
14 2,063 2,212
17 2,363 2,510

Load After a Use

During the list a second RAM load placed 4 instructions after the use of the first took 3,701 to 3,718 cycles over 100 turns. Every other gap from 0 to 6 gave 3,619 to 3,649 cycles, so the gap of 4 cost about 80 cycles more. The list also ended about 80 cycles later at that gap. Alone every gap gave 2,757 to 2,771 cycles.6

Load After a Store

Alone, a halfword load after a halfword store took 1,476 to 1,486 cycles over 100 turns. The time was the same whether the load read the halfword just stored, the other halfword of its word, another word of its line or another line, with 0 or 2 NOPs between. During L0 the three loads within the stored line took 2,772 to 2,783 cycles and the load of another line 2,713 to 2,726, which is about 55 cycles less.7

Single Turns

Each turn of a RAM store, 2 NOPs, a read of root counter 2 and a scratchpad store of the count took 13 cycles. The same turn without the NOPs also took 13 cycles, so the two NOPs run in time the turn spends waiting in any case. With a RAM load in place of the store the turn took 18 cycles. The first turn of each row took 20 to 27 cycles, and single later turns took 1 to 4 cycles more than the rest.8

Two halfword reads of root counter 2 back to back read counts 4 apart, whatever word of the cache line held the first read. 100 turns took 2,337 to 2,350 cycles at every place.9

Runs

5 October 2026

followup22/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
9 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80110444 PRId 00000002

followup22/01SPW.txt

===== 01 SPW F22 SPU LOAD WAITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DPCR as found: 33333B33 (the BIOS's in the window: 0F6F4B21, store-win.txt:2)
8 turns of 16 loads: k of them SPU lhu 1F801C0Ch+N*10h, the rest scratchpad lw (no bus:
memory-map.txt:7), each followed by 2 NOPs. The list's end against k says who waits.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
SPU lhu k  0: alone 471; L0 572/66/10585; L2 587/64/10610; alone 465; L0 567/64/10570; L2 588/64/10617;
SPU lhu k  1: alone 623; L0 756/72/10706; L2 774/71/10724; alone 617; L0 766/72/10679; L2 766/70/10726;
SPU lhu k  2: alone 779; L0 953/81/10813; L2 973/79/10842; alone 769; L0 946/78/10799; L2 955/77/10841;
SPU lhu k  4: alone 1079; L0 1294/90/11061; L2 1298/87/11081; alone 1073; L0 1294/88/11046; L2 1294/87/11083;
SPU lhu k  8: alone 1687; L0 1988/112/11530; L2 2007/109/11565; alone 1681; L0 2002/110/11529; L2 1997/109/11555;
SPU lhu k 16: alone 2882; L0 3472/159/12536; L2 3473/156/12566; alone 2870; L0 3472/157/12516; L2 3493/156/12572;
RAM lw  k  0: alone 471; L0 567/66/10581; L2 581/63/10620; alone 470; L0 571/64/10566; L2 570/63/10609;
RAM lw  k  1: alone 519; L0 709/78/10599; L2 717/76/10624; alone 513; L0 710/77/10582; L2 717/76/10624;
RAM lw  k  2: alone 570; L0 805/86/10610; L2 811/83/10644; alone 562; L0 804/84/10601; L2 812/83/10642;
RAM lw  k  4: alone 667; L0 936/95/10649; L2 936/92/10676; alone 658; L0 925/92/10629; L2 928/92/10665;
RAM lw  k  8: alone 870; L0 1228/118/10709; L2 1244/116/10741; alone 854; L0 1239/117/10697; L2 1244/116/10741;
RAM lw  k 16: alone 1236; L0 1775/159/10835; L2 1781/156/10865; alone 1222; L0 1776/157/10831; L2 1782/156/10856;
RAM sh  k  0: alone 471; L0 567/66/10580; L2 575/63/10614; alone 465; L0 568/64/10567; L2 578/63/10617;
RAM sh  k  1: alone 471; L0 581/65/10600; L2 586/62/10632; alone 465; L0 585/63/10598; L2 595/62/10643;
RAM sh  k  2: alone 471; L0 585/63/10622; L2 593/60/10659; alone 465; L0 591/61/10620; L2 597/61/10650;
RAM sh  k  4: alone 471; L0 624/62/10689; L2 632/59/10701; alone 465; L0 628/60/10671; L2 628/59/10704;
RAM sh  k  8: alone 471; L0 1034/93/10776; L2 1041/90/10801; alone 465; L0 1036/91/10768; L2 1041/90/10797;
RAM sh  k 16: alone 471; L0 1856/155/10966; L2 1861/152/10999; alone 468; L0 1862/153/10955; L2 1872/152/11003;
Done.

followup22/02SNP.txt

===== 02 SNP F22 SPU LHU NOPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
24 turns of lhu 1F801C0Ch and n NOPs, n 0 to 14, alone and on L0.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
n  0: alone 594; L0 811/55/10937; alone 582; L0 827/53/10941;
n  1: alone 588; L0 834/55/10955; alone 582; L0 826/53/10939;
n  2: alone 588; L0 817/55/10938; alone 582; L0 816/53/10929;
n  3: alone 588; L0 820/55/10939; alone 582; L0 826/53/10939;
n  4: alone 588; L0 828/55/10957; alone 582; L0 817/53/10933;
n  5: alone 588; L0 820/55/10952; alone 582; L0 822/53/10931;
n  6: alone 588; L0 825/55/10954; alone 582; L0 816/53/10932;
n  7: alone 588; L0 821/55/10942; alone 582; L0 825/53/10933;
n  8: alone 588; L0 815/55/10942; alone 582; L0 819/53/10930;
n  9: alone 589; L0 812/55/10946; alone 586; L0 835/53/10948;
n 10: alone 588; L0 817/55/10949; alone 582; L0 820/53/10931;
n 11: alone 588; L0 819/55/10942; alone 582; L0 817/53/10930;
n 12: alone 591; L0 827/55/10954; alone 582; L0 815/53/10926;
n 13: alone 588; L0 829/55/10941; alone 582; L0 821/53/10929;
n 14: alone 589; L0 821/55/10944; alone 583; L0 817/53/10930;
Done.

followup22/03UA4.txt

===== 03 UA4 F22 LOAD AFTER USE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of 16 words: lw t2; NOP; addu t3,t3,t2 (the use); g NOPs; lw t4 0x40(s0);
NOPs to 16. g 0 to 6, alone and on L0 and L2.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
g 0: alone 2766; L0 3619/324/10984; L2 3637/322/11021; alone 2762; L0 3627/323/10971; L2 3632/322/11019;
g 1: alone 2771; L0 3632/325/10988; L2 3638/322/11013; alone 2757; L0 3637/322/10980; L2 3640/322/11015;
g 2: alone 2765; L0 3621/324/10981; L2 3637/322/11021; alone 2762; L0 3627/323/10971; L2 3632/322/11019;
g 3: alone 2769; L0 3632/325/10988; L2 3638/322/11013; alone 2757; L0 3637/322/10980; L2 3640/322/11015;
g 4: alone 2765; L0 3701/325/11067; L2 3718/323/11086; alone 2757; L0 3714/323/11056; L2 3718/323/11089;
g 5: alone 2765; L0 3623/324/10996; L2 3631/322/11009; alone 2763; L0 3629/323/10980; L2 3630/321/11029;
g 6: alone 2770; L0 3644/326/10988; L2 3649/323/11022; alone 2765; L0 3630/323/10973; L2 3629/321/11028;
Done.

followup22/04JRC.txt

===== 04 JRC F22 COLD CALLS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of two calls of a 'jr ra; NOP' routine: both at C00h (warm) or C00h and
1C00h (one line, two tags: each cold). By jal, jalr t9, or jr t9 with ra set.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
jal  warm: alone 1165; L0 1260/134/10575; L2 1269/131/10600; alone 1157; L0 1263/132/10562; L2 1266/131/10609;
jalr warm: alone 1563; L0 1664/173/10583; L2 1668/170/10610; alone 1557; L0 1662/171/10561; L2 1673/170/10614;
jr   warm: alone 1963; L0 2062/212/10579; L2 2077/209/10611; alone 1961; L0 2069/211/10563; L2 2070/209/10613;
jal  cold: alone 2773; L0 3275/231/11596; L2 3277/228/11628; alone 2768; L0 3269/229/11583; L2 3280/228/11624;
jalr cold: alone 3167; L0 4212/324/11593; L2 4219/321/11610; alone 3163; L0 4221/323/11571; L2 4221/321/11609;
jr   cold: alone 3590; L0 4335/326/11690; L2 4336/323/11712; alone 3587; L0 4334/324/11663; L2 4343/324/11710;
Done.

followup22/05MDS.txt

===== 05 MDS F22 MULDIV PARTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns, alone and on L0: divu or multu (1000, 7), 2 NOPs, mflo, then a RAM lw;
the same without the mflo; without the lw; the lw alone after 3 NOPs.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
divu  all: alone 4667; L0 4618/444/10759; alone 4657; L0 4624/442/10755;
divu  no mflo: alone 1270; L0 1437/131/10781; alone 1264; L0 1436/129/10764;
divu  no lw: alone 4467; L0 4567/457/10582; alone 4461; L0 4564/455/10564;
divu  lw only: alone 1270; L0 1433/131/10776; alone 1264; L0 1436/129/10764;
multu all: alone 1667; L0 1689/154/10808; alone 1661; L0 1693/152/10796;
multu no mflo: alone 1270; L0 1433/131/10776; alone 1264; L0 1436/129/10764;
multu no lw: alone 1467; L0 1574/164/10584; alone 1461; L0 1571/162/10560;
multu lw only: alone 1274; L0 1435/131/10782; alone 1264; L0 1437/129/10777;
Done.

followup22/06K3P.txt

===== 06 K3P F22 ONE LOAD P4 17 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of a RAM lw and p NOPs, p 4 to 17, on L0, three times each (followup14 ONK
gave more for p 8 to 10 only).
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
p  4 run 1: alone 1068; L0 1437/131/10789; alone 1062; L0 1436/129/10768;
p  4 run 2: alone 1068; L0 1439/131/10783; alone 1061; L0 1435/129/10769;
p  4 run 3: alone 1070; L0 1436/131/10779; alone 1064; L0 1434/129/10770;
p  5 run 1: alone 1172; L0 1436/131/10784; alone 1160; L0 1435/129/10769;
p  5 run 2: alone 1170; L0 1434/131/10786; alone 1163; L0 1438/129/10775;
p  5 run 3: alone 1172; L0 1431/131/10783; alone 1166; L0 1434/129/10770;
p  6 run 1: alone 1267; L0 1436/131/10777; alone 1260; L0 1436/129/10768;
p  6 run 2: alone 1266; L0 1439/131/10787; alone 1260; L0 1436/129/10764;
p  6 run 3: alone 1267; L0 1436/131/10777; alone 1260; L0 1436/129/10768;
p  7 run 1: alone 1363; L0 1521/132/10865; alone 1359; L0 1515/129/10842;
p  7 run 2: alone 1365; L0 1529/132/10870; alone 1360; L0 1523/130/10847;
p  7 run 3: alone 1364; L0 1515/131/10859; alone 1357; L0 1523/130/10854;
p  8 run 1: alone 1464; L0 1702/154/10811; alone 1457; L0 1689/151/10796;
p  8 run 2: alone 1463; L0 1695/154/10815; alone 1457; L0 1686/151/10793;
p  8 run 3: alone 1463; L0 1695/154/10815; alone 1457; L0 1686/151/10793;
p  9 run 1: alone 1563; L0 1752/162/10775; alone 1557; L0 1746/160/10761;
p  9 run 2: alone 1563; L0 1752/162/10775; alone 1557; L0 1746/160/10761;
p  9 run 3: alone 1563; L0 1752/162/10775; alone 1557; L0 1746/160/10761;
p 10 run 1: alone 1663; L0 1844/169/10805; alone 1657; L0 1847/167/10789;
p 10 run 2: alone 1663; L0 1844/169/10805; alone 1657; L0 1847/167/10789;
p 10 run 3: alone 1663; L0 1844/169/10805; alone 1657; L0 1847/167/10789;
p 11 run 1: alone 1763; L0 1909/177/10790; alone 1757; L0 1921/176/10773;
p 11 run 2: alone 1768; L0 1912/177/10778; alone 1757; L0 1920/176/10765;
p 11 run 3: alone 1763; L0 1910/177/10790; alone 1757; L0 1913/175/10778;
p 12 run 1: alone 1863; L0 2012/187/10788; alone 1857; L0 2013/185/10772;
p 12 run 2: alone 1863; L0 2011/187/10787; alone 1857; L0 2013/185/10772;
p 12 run 3: alone 1863; L0 2011/187/10787; alone 1857; L0 2013/185/10772;
p 13 run 1: alone 1963; L0 2105/194/10807; alone 1957; L0 2115/193/10789;
p 13 run 2: alone 1963; L0 2120/195/10810; alone 1957; L0 2112/193/10787;
p 13 run 3: alone 1963; L0 2107/195/10805; alone 1957; L0 2120/194/10781;
p 14 run 1: alone 2063; L0 2212/208/10778; alone 2057; L0 2216/206/10754;
p 14 run 2: alone 2063; L0 2215/208/10769; alone 2063; L0 2219/206/10765;
p 14 run 3: alone 2063; L0 2212/207/10774; alone 2057; L0 2204/205/10766;
p 15 run 1: alone 2163; L0 2308/216/10785; alone 2157; L0 2311/214/10775;
p 15 run 2: alone 2163; L0 2313/217/10786; alone 2157; L0 2308/214/10770;
p 15 run 3: alone 2163; L0 2315/217/10781; alone 2157; L0 2309/215/10764;
p 16 run 1: alone 2263; L0 2405/227/10769; alone 2257; L0 2400/225/10742;
p 16 run 2: alone 2263; L0 2404/227/10769; alone 2257; L0 2408/225/10754;
p 16 run 3: alone 2268; L0 2404/227/10762; alone 2257; L0 2409/225/10753;
p 17 run 1: alone 2363; L0 2510/231/10834; alone 2357; L0 2511/229/10817;
p 17 run 2: alone 2363; L0 2511/231/10834; alone 2357; L0 2511/229/10824;
p 17 run 3: alone 2363; L0 2511/231/10834; alone 2357; L0 2511/229/10824;
Done.

followup22/07LHS.txt

===== 07 LHS F22 STORE THEN LHU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns: sh t6,0(s1); k NOPs; lhu of 0(s1) (the same halfword), 2(s1) (same word),
8(s1) (same line), 40h(s1) (another line); 4 NOPs. k 0 and 2, alone and on L0.
Each row: alone (cycles), then L<shape> cycles/node at the end/list done; twice.
k 0 lhu 00h: alone 1485; L0 2783/231/11096; alone 1476; L0 2775/229/11087;
k 0 lhu 02h: alone 1485; L0 2774/231/11094; alone 1481; L0 2777/229/11083;
k 0 lhu 08h: alone 1480; L0 2775/231/11098; alone 1481; L0 2772/229/11076;
k 0 lhu 40h: alone 1485; L0 2726/227/11096; alone 1476; L0 2718/225/11087;
k 2 lhu 00h: alone 1485; L0 2772/231/11093; alone 1481; L0 2772/229/11085;
k 2 lhu 02h: alone 1486; L0 2773/231/11093; alone 1481; L0 2776/229/11082;
k 2 lhu 08h: alone 1486; L0 2772/231/11090; alone 1481; L0 2772/229/11085;
k 2 lhu 40h: alone 1483; L0 2723/227/11091; alone 1481; L0 2713/225/11077;
Done.

followup22/08ALT.txt

===== 08 ALT F22 TURN BY TURN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
40 turns, alone, each turn's timer 2 count saved to the scratchpad: sh to RAM, 2 NOPs,
lhu of timer 2 (1F801120h); the same with 0 NOPs; the same with a lw for the sh.
sh, 2 NOPs: turn lengths 22 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 17 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
sh, 0 NOPs: turn lengths 20 13 13 13 14 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
lw, 2 NOPs: turn lengths 27 18 18 18 18 18 18 18 18 18 18 18 18 22 18 18 18 18 18 18 18 18 18 18 18 18 18 22 18 18 18 18 18 18 18 18 18 18 18
Done.

followup22/09IOP.txt

===== 09 IOP F22 IO LOAD PAIRS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of two lhu of timer 2 back to back, the first at word w of a cache line, then
their difference saved; printed the last turn's difference and the turns' time.
w 0 run 1: 100 turns 2337, the pair 4 apart
w 0 run 2: 100 turns 2337, the pair 4 apart
w 1 run 1: 100 turns 2350, the pair 4 apart
w 1 run 2: 100 turns 2339, the pair 4 apart
w 2 run 1: 100 turns 2339, the pair 4 apart
w 2 run 2: 100 turns 2349, the pair 4 apart
w 3 run 1: 100 turns 2338, the pair 4 apart
w 3 run 2: 100 turns 2338, the pair 4 apart
Done.

References

  1. ^ a b c d SCPH-5501 output: followup22/01SPW.txt.

  2. ^ SCPH-5501 output: followup22/02SNP.txt.

  3. ^ a b SCPH-5501 output: followup22/04JRC.txt.

  4. ^ a b SCPH-5501 output: followup22/05MDS.txt.

  5. ^ SCPH-5501 output: followup22/06K3P.txt.

  6. ^ SCPH-5501 output: followup22/03UA4.txt.

  7. ^ SCPH-5501 output: followup22/07LHS.txt.

  8. ^ SCPH-5501 output: followup22/08ALT.txt.

  9. ^ SCPH-5501 output: followup22/09IOP.txt.

Categories: Hardware tests