Load Delay Slot Collisions

Measures the time a counted loop takes when the instruction in a load's delay slot, or the one after it, writes, reads or loads the load's destination register, by load width, data region and code segment.

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Overview

The program is a set of 2,016 small programs, each timed whole for 16 passes of a counted loop and called eight times; the first call is cold. Each pass is a lui of the address, a load L into t1, an instruction N, and j NOPs. N sits in the load's delay slot ("slot") or one word later after a NOP ("late"). Each line's name gives L, N, the data region, the code segment, j and the position, and the line gives the eight times twice, as run1 and run2.¹

See also:

• Load Landing and Device Loads

Results

In all 2,016 lines run1 and run2 hold the same eight times. The control ctl, which writes another register, is the time of the loop without a collision, and the times below are the median of calls 2 to 8.¹

With RAM data and cached code, any N that wrote t1, read it or moved HI into it in the delay slot took 47 to 49 counts more than the control over the 16 passes, which is about 3 a pass. A second load into t1 took 112 to 116 counts more. With N one word later the cost was 64 to 66 counts, and 129 for the second load. With scratchpad data none of the N cost anything over the control.¹

From uncached code with N one word later, wd and rd still cost 30 to 32 counts, but wds and mfhi cost nothing. In the delay slot from uncached code every N cost 27 to 37 counts and the second load 97 to 101.¹

The load width changed these costs by at most 8 counts. RAM data through KSEG0, KSEG1 or KUSEG gave times within 5 counts of each other in every program.¹

Runs

9 October 2026

col1/COL1.txt

References