SPU Voice Start and MDEC Reset

Measures SPU voice behavior at key on, the noise generator state, the ENDX refill and the repeat address, and whether an MDEC command stored straight after a reset is taken.

This is an old revision of this page, as edited by RemmyLee at 05:49, 23 October 2026. Edit this revision | Latest revision

Overview

The program runs six groups. Five of them use the SPU: each uploads a test image to sound RAM at 28000h, reads it back, and then keys on a voice and records what it plays or what its registers show. In every group the image read back with 0 of its 512 halfwords different.¹ The sixth group stores an MDEC command straight after an MDEC reset.²

See also:

• SPU Voice Onset and Pitch
• MDEC Reset and Store Timing

Results

Key On After a Bit 11 Rise

The key on came 68 to 109 cycles later than the delay d asked for: 109 cycles after the rise for d 0 and 12,076 cycles for d 12,000. In the capture the tone began 4 samples later for each 3,000 cycles of d from 0 to 9,000, and 2 samples later again at d 12,000.³

Noise at Key On

The noise voice was keyed on three times with 512 and then 768 samples between the key ons. It was keyed on twice more after SPUCNT was turned off and on. The first 24 samples were different each time: they began 09F6h, A499h, F5C2h, 0AC5h and 21C3h. Key on and an SPUCNT off and on therefore do not set the noise generator to one starting state.⁴

ENDX Refill

With all 24 voices keyed on onto a block of flags 07h at 28000h and released, the low half of ENDX was written 0000h at eight delays from 0 to 18,816 cycles after a bit 11 rise. Each time it read FFFFh again after 1,029 to 18,677 cycles, and the time depended on the delay.⁵

Repeat Address

Voice 1's data was at 30000h, so 6000h in the repeat register is the start of its data and 6010h is 30080h, which lies 8 blocks of 16 bytes further on. Keyed on at pitch 0 onto a block without flags, the voice read repeat address 4000h with ENDX bit 1 set at once, and 4000h with the bit clear 50,000 cycles later.⁶

Keyed on with the SPU off, the voice still read 4000h 100,000 cycles later, and 100,000 cycles after the SPU was turned on it read 6010h. A voice released on the block of flags 07h read 6000h with ENDX bit 1 set. When block 0 then lost its flags, the voice read 6010h 200,000 cycles later. The same happened when the SPU was turned off and on after the release, and after the key on and key off that SpuInit performs.⁶

MDEC Command After a Reset

In nine of the eleven cases the status read after the two stores was 40000001h in both runs. In the first run it was A004001Fh in two cases: a RAM store and 4 NOPs before the reset, and nothing before the reset with 1 NOP between the two stores. The second run gave 40000001h in those cases as well.²

Runs

5 October 2026

followup26/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
6 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8010B144 PRId 00000002

followup26/01RMP.txt

===== 01 RMP F26 RAMP AFTER ONE VALUE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
Voice 1, ADSR attack 0, decay Fh, sustain Fh: block 0 of one value (7) then block 1 a ramp
(-8 to 7, 7 down to -4, shift 0 filter 0), captured (row 36); then the ramp first.
one value (7), then the ramp, pitch 1000: onset at 53; from 4 before it
  0000 0000 0000 0000 30CE 619D 6F8E 6F8E 6F8E 6F8E 6F87 6F87 6F87 6F87 6F87 6F87
  from 24 after it:
  4BDE A61B 907E A06D B05C C04B D03A E029 F018 0006 0FF5 1FE4 2FD3 3FC2 4FB1 5FA0
  6D2E 6D26 5F90 4FA1 3FB2 2FC3 1FD4 0FE5 FFF7 F008 E019 D02A CC1E F69C 0000 0000
one value (7), then the ramp, pitch 0800: onset at 453; from 4 before it
  0000 0000 0000 0000 30CE 619D 6F8E 6F8E 6F8E 6F8E 6F87 6F87 6F87 6F87 6F87 6F87
  from 24 after it:
  6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87
  6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F87 6F89 6C6C 4BDE F7DA A61B 8BC1 907E 9877
one value (7), then the ramp, pitch 0400: onset at 411; from 4 before it
  0000 0000 0000 0000 30CE 619E 6F8E 6F8E 6F8E 6F8F 6F8E 6F8E 6F8E 6F8F 6F8E 6F8E
  from 24 after it:
  6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87
  6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87 6F87 6F88 6F87 6F87
one value (7), then the ramp, pitch 2000: onset at 499; from 4 before it
  0000 0000 0000 0000 30CE 619D 6F8E 6F8E 6F8E 6F8E 6F8E 6F8E 6F87 6F87 6F87 4BDE
  from 24 after it:
  E019 CC1E 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ramp first, pitch 1000: onset at 413; from 4 before it
  0000 0000 0000 0000 DD26 C83E D037 E027 F017 0006 0FF6 1FE6 2FD6 3FC6 4FB6 5FA6
Done.

followup26/02CPS.txt

===== 02 CPS F26 KEY ON FROM A BIT 11 RISE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
Voice 1 plays tone T (U_T, looped) at pitch 0800h; the key on d cycles after a SPUSTAT
bit 11 rise; cycles from that rise to the key on, from the key on to the second rise
after it (the capture is read there), then the first 32 samples of the ring (row 65).
d 0: rise to key on 109, key on to the read's rise 786339
  018C 00FD 0073 FFEF FF6E FEF1 FE77 FE03 FD91 FD23 FCB9 FC53 FBEE FB8E FB30 FAD5
  FA7D FA29 F9EE FA94 FCCA FF31 006D 00FD 017D 01FC 027C 02FB 037B 03FA 0479 04F9
d 3000: rise to key on 3084, key on to the read's rise 783348
  03F6 0354 02B7 021F 018C 00FD 0073 FFEF FF6E FEF1 FE77 FE03 FD91 FD23 FCB9 FC53
  FBEE FB8E FB30 FAD5 FA7D FA29 F9EE FA94 FCCA FF31 006D 00FD 017D 01FC 027C 02FB
d 6000: rise to key on 6068, key on to the read's rise 780375
  06AF 05FD 054B 049E 03F6 0354 02B7 021F 018C 00FD 0073 FFEF FF6E FEF1 FE77 FE03
  FD91 FD23 FCB9 FC53 FBEE FB8E FB30 FAD5 FA7D FA29 F9EE FA94 FCCA FF31 006D 00FD
d 9000: rise to key on 9096, key on to the read's rise 777316
  0693 06DF 0722 0724 06AF 05FD 054B 049E 03F6 0354 02B7 021F 018C 00FD 0073 FFEF
  FF6E FEF1 FE77 FE03 FD91 FD23 FCB9 FC53 FBEE FB8E FB30 FAD5 FA7D FA29 F9EE FA94
d 12000: rise to key on 12076, key on to the read's rise 774356
  05F5 0645 0693 06DF 0722 0724 06AF 05FD 054B 049E 03F6 0354 02B7 021F 018C 00FD
  0073 FFEF FF6E FEF1 FE77 FE03 FD91 FD23 FCB9 FC53 FBEE FB8E FB30 FAD5 FA7D FA29
Done.

followup26/03NKS.txt

===== 03 NKS F26 NOISE STATE AT KEY ON | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
Noise shift 15 step 3 on voice 1 (NON bit 1, spx:681), the level written 7FFFh at each key
on, each key on at a SPUSTAT bit 11 rise (256 samples apart); the first 24 samples (row 66).
key on 1:
  09F6 13EC 27D9 4FB2 9F77 3EDE 7DBD FB8C F718 EE31 DC62 B8C6 717A E306 C60C 8C19
  1820 3041 6083 C119 8232 0453 08A7 114E
key on 2, 512 samples later:
  A499 4921 9255 249A 4934 927B 24E6 49CC 93AB 2746 4E8C 9D2B 3A46 748E E930 D262
  A4C5 4979 9305 25FA 4BF4 97FB 2FE4 5FCA
key on 3, 768 samples after 2:
  F5C2 EB85 D70B AE17 5C1D B84D 7088 E122 C244 8488 0900 1200 2401 4802 9017 201E
  403E 808F 010D 021C 043A 0875 10EA 21D5
after SPUCNT off and on:
  0AC5 158A 2B15 562B AC6A 58C3 B19A 6324 C65B 8CB7 195C 32B9 6572 CAF7 95F0 2BCE
  579D AF4E 5E8B BD28 7A40 F493 E927 D250
after SPUCNT off and on, again:
  21C3 4388 8723 0E36 1C6D 38DA 71B5 E37C C6F8 8DF1 1BD0 37A1 6F43 DE99 BD33 7A56
  F4BF E97F D300 A601 4BF1 97F5 2FD8 5FB2
Done.

followup26/04EXR.txt

===== 04 EXR F26 ENDX REFILL AFTER A WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
All 24 voices keyed on onto the 07h block at 28000h and released, as followup18 EXH. ENDX
low half written 0000h d cycles after a SPUSTAT bit 11 rise; cycles to its refill (row 109):
 d 0: 2077 (FFFF)
 d 2688: 14817 (FFFF)
 d 5376: 6021 (FFFF)
 d 8064: 18677 (FFFF)
 d 10752: 9884 (FFFF)
 d 13440: 1029 (FFFF)
 d 16128: 13673 (FFFF)
 d 18816: 4876 (FFFF)
Done.

followup26/05MRQ.txt

===== 05 MRQ F26 MDEC COMMAND AFTER A RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
MDEC1 80000000h, then 40000001h to MDEC0 with nothing between, then the status (A004001F
kept, 80040000 lost; h/109-mdec2/09MST.txt:14). First run, then a second (row 113):
 nothing before: 40000001 40000001
 a RAM sw before (load_tables): 40000001 40000001
 two RAM sw before: 40000001 40000001
 a RAM sw, 1 nop before: 40000001 40000001
 a RAM sw, 4 nops before: A004001F 40000001
 a scratchpad sw before: 40000001 40000001
 an MDEC1 sw of 0 before: 40000001 40000001
 a RAM lw before: 40000001 40000001
 nothing before, 1 nop between: A004001F 40000001
 a RAM sw before, 1 nop between: 40000001 40000001
 a RAM sw before, 2 nops between: 40000001 40000001
Done.

followup26/06RPT.txt

===== 06 RPT F26 REPEAT ADDRESS AFTER KEY ON | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
Voice 1 at 30000h; repeat address/ENDX bit 1 after each step (row 115):
 pitch 0, flagless start, key on: at once 4000/1 50000 later 4000/0
 SPU off, key on at block 1: 100000 later 4000/0 SPU on, 100000 later 6010/0
 released on the 07h block 6000/1 block 0 flagless, 200000 later 6010/1
 released, SPU off and on 6000/1 block 0 flagless, 200000 later 6010/1
 SpuInit's key on and off 6000/0 block 0 flagless, 200000 later 6010/1
Done.

References