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Undrained SPU Write FIFO

Measures which halfwords of a block in the SPU write FIFO reach sound RAM when the transfer mode is set to Stop a given time after the block is sent, and what the halfwords not yet written keep.

Undrained SPU Write FIFO
MachineSCPH-5501
Programfollowup12

This is an old revision of this page, as edited by RemmyLee at 05:40, 23 October 2026. Edit this revision | Latest revision

Overview

The program first writes 1234h to all 32 halfwords at sound RAM address 30000h by DMA and lets the write drain in full, then reads the area back. It then sends either a block of 16 words, the halfwords B000h to B01Fh, by SPU DMA, or the 16 halfwords B000h to B00Fh stored by hand to the data transfer FIFO. After a wait of 0 to 900 cycles of root counter 2, counted from the end of the DMA or from the store to SPUCNT that starts the manual transfer, it sets the transfer mode to Stop and reads all 32 halfwords back by DMA.1

See also:

Results

The area read 1234h in all 32 halfwords before every row, so the first fill had drained. After a block sent by DMA, the halfwords that had reached sound RAM by the Stop held B000h onward in order, and every halfword after them still held 1234h. A halfword the FIFO had not written by the Stop therefore keeps what sound RAM held before. The number written grew with the wait until all 32 were in place at 800 cycles.1

Table 1: Halfwords written from a DMA block by wait
Wait (cycles) Halfwords written
0 9
100 10
200 12
300 13
400 17
500 21
600 26
700 30
800 32
900 32

From a wait of 200 cycles on, the 16 halfwords stored by hand read back as B000h to B00Fh and the 16 halfwords after them held 1234h. At waits of 0 and 100 cycles only 12 halfwords had been written, and they were shifted. The area began with B001h at wait 0 and with B002h at wait 100, and its last halfword read DAAAh at wait 0, while the last two read DAAAh and 7AAAh at wait 100.1

Runs

3 October 2026

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8010D5E0 PRId 00000002

01SSK.txt

===== 01 SSK F12 SPU FIFO KEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
SPU write FIFO cut by a Stop: 1234h written to all 32 halfwords at 30000h and drained
first, then 16 words B000h + i by DMA (the wait from the DMA's end) or 16 halfwords by
hand (from the SPUCNT store), Stop, and all 32 read back by DMA.
  DMA, wait 0 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 100 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 200 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 300 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 400 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 500 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 B011 B012 B013 B014 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  DMA, wait 600 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 B011 B012 B013 B014 B015 B016 B017
    B018 B019 1234 1234 1234 1234 1234 1234
  DMA, wait 700 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 B011 B012 B013 B014 B015 B016 B017
    B018 B019 B01A B01B B01C B01D 1234 1234
  DMA, wait 800 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 B011 B012 B013 B014 B015 B016 B017
    B018 B019 B01A B01B B01C B01D B01E B01F
  DMA, wait 900 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    B010 B011 B012 B013 B014 B015 B016 B017
    B018 B019 B01A B01B B01C B01D B01E B01F
  manual, wait 0 (1234h first in 32 of 32):
    B001 B002 B003 B004 B005 B006 B007 B008
    B009 B00A B00B B00C 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 DAAA
  manual, wait 100 (1234h first in 32 of 32):
    B002 B003 B004 B005 B006 B007 B008 B009
    B00A B00B B00C B00D 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 DAAA 7AAA
  manual, wait 200 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 300 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 400 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 500 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 600 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 700 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 800 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
  manual, wait 900 (1234h first in 32 of 32):
    B000 B001 B002 B003 B004 B005 B006 B007
    B008 B009 B00A B00B B00C B00D B00E B00F
    1234 1234 1234 1234 1234 1234 1234 1234
    1234 1234 1234 1234 1234 1234 1234 1234
Done.

References

  1. ^ a b c SCPH-5501 output: followup12/01SSK.txt and the file beside it.

Categories: Hardware tests