Bus Auto Increment: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| A 32-bit access to a 16-bit device is two bus transactions, and to an 8-bit device four. Bit 13 of a device's delay and size register decides whether the device address advances between those transactions. The program tests this on the 8-bit BIOS ROM through DEV2 (1F801010h) and on the 16-bit SPU through DEV4 (1F801014h).[^src] | A 32-bit access to a 16-bit device is two bus transactions, and to an 8-bit device four. Bit 13 of a device's delay and size register decides whether the device address advances between those transactions. The program tests this on the 8-bit BIOS ROM through DEV2 (1F801010h) and on the 16-bit SPU through DEV4 (1F801014h).[^src] | ||
| − | On the ROM it reads words, halfwords and bytes from BFC00000h under the BIOS's own setting and again with bit 13 cleared. On the SPU it seeds the voice 0 ADSR registers at 1F801C08h and 1F801C0Ah with halfword stores under a safe setting. It then issues one SW, LW, LH or SH under the setting being tested and reads the result back under the safe setting.[^src] | + | On the ROM it reads words, halfwords and bytes from BFC00000h under the BIOS's own setting and again with bit 13 cleared. On the SPU it seeds the voice 0 ADSR registers at 1F801C08h and 1F801C0Ah with halfword stores under a safe setting. It then issues one SW, LW, LH or SH under the setting being tested and reads the result back under the safe setting.[^src] The program ran its full set three times and printed the same lines each time.[^run] |
| − | The program ran its full set three times and printed the same lines each time.[^run] | ||
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| ## Results | ## Results | ||