Cache Control Register Bits: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| The cache control register BCC sits at FFFE0130h, and the BIOS leaves it at 0001E988h. psx-spx names bits 12 to 17 INTP, RDPRI, NOPAD, BGNT, LDSCH and NOSTR after the LR33300 manual.[^srcb] | The cache control register BCC sits at FFFE0130h, and the BIOS leaves it at 0001E988h. psx-spx names bits 12 to 17 INTP, RDPRI, NOPAD, BGNT, LDSCH and NOSTR after the LR33300 manual.[^srcb] | ||
| − | The bcc-bits program flips one bit at a time away from 0001E988h and times a fixed set of sequences against the unchanged value. Interrupts are masked, and root counter 2 counts system clock cycles. The sequences are a RAM load and its use, a RAM store, a store then a load, a RAM load and a NOP, a scratchpad access, an I/O access, uncached instruction fetch, and a DMA transfer running against the CPU. Each figure is the smallest of 8 runs, and each row is taken twice. The program prints UNSTABLE when the two passes differ, and MOVED when the row differs from the unchanged value. As a control it also clears bit 11, which turns the instruction cache off.[^srcb] | + | The bcc-bits program flips one bit at a time away from 0001E988h and times a fixed set of sequences against the unchanged value. Interrupts are masked, and root counter 2 counts system clock cycles. The sequences are a RAM load and its use, a RAM store, a store then a load, a RAM load and a NOP, a scratchpad access, an I/O access, uncached instruction fetch, and a DMA transfer running against the CPU. Each figure is the smallest of 8 runs, and each row is taken twice. The program prints UNSTABLE when the two passes differ, and MOVED when the row differs from the unchanged value. As a control it also clears bit 11, which turns the instruction cache off.[^srcb] The bcc-narrow program reads BCC three times with LW, with LB at each byte offset and with LH at each halfword offset.[^runn] |
| − | The bcc-narrow program reads BCC three times with LW, with LB at each byte offset and with LH at each halfword offset.[^runn] | ||
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| ## Results | ## Results | ||
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| | 0001E188h | bit 11 cleared | 1114 | 590 | 5110 to 5111 | | | 0001E188h | bit 11 cleared | 1114 | 590 | 5110 to 5111 | | ||
| − | Clearing BGNT (bit 15) stopped the DMA transfer from finishing: the channel was still busy when the program gave up, and it drained once BCC was restored. Clearing LDSCH (bit 16) slowed a RAM load followed by a NOP from 292 to 357 counts and added 1 or 2 counts to the other sequences. Setting NOSTR (bit 17) slowed uncached instruction fetch from 590 to 624 counts.[^runb] | + | Clearing BGNT (bit 15) stopped the DMA transfer from finishing: the channel was still busy when the program gave up, and it drained once BCC was restored. Clearing LDSCH (bit 16) slowed a RAM load followed by a NOP from 292 to 357 counts and added 1 or 2 counts to the other sequences. Setting NOSTR (bit 17) slowed uncached instruction fetch from 590 to 624 counts.[^runb] Clearing bit 11 made every cached sequence run at the uncached speed: the RAM load and its use took 590 counts against 262, and the scratchpad sequence 592 against 100.[^runb] |
| − | Clearing bit 11 made every cached sequence run at the uncached speed: the RAM load and its use took 590 counts against 262, and the scratchpad sequence 592 against 100.[^runb] | ||
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| ### Narrow Reads of BCC | ### Narrow Reads of BCC | ||