Cache Control Register Bits

Measures the effect of BCC bits 11 to 17 on bus, cache and DMA timing, and what narrow reads of BCC return.

Cache Control Register Bits
Machine	SCPH-5501
Program	bcc-bits and bcc-narrow (pcsx-redux nugget)

Overview

The cache control register BCC sits at FFFE0130h, and the BIOS leaves it at 0001E988h. psx-spx names bits 12 to 17 INTP, RDPRI, NOPAD, BGNT, LDSCH and NOSTR after the LR33300 manual.¹

The bcc-bits program flips one bit at a time away from 0001E988h and times a fixed set of sequences against the unchanged value. Interrupts are masked, and root counter 2 counts system clock cycles. The sequences are a RAM load and its use, a RAM store, a store then a load, a RAM load and a NOP, a scratchpad access, an I/O access, uncached instruction fetch, and a DMA transfer running against the CPU. Each figure is the smallest of 8 runs, and each row is taken twice. The program prints UNSTABLE when the two passes differ, and MOVED when the row differs from the unchanged value. As a control it also clears bit 11, which turns the instruction cache off.¹ The bcc-narrow program reads BCC three times with LW, with LB at each byte offset and with LH at each halfword offset.²

Results

BCC Bits

Bits 12 (INTP), 13 (RDPRI) and 14 (NOPAD) changed no sequence by more than 3 counts, and neither did the unchanged value between its own two passes. The DMA row varied by a few counts in every row, so most rows are marked UNSTABLE.³

Table 1: Counts with one BCC bit changed
Value	Bit	RAM load and NOP	Uncached fetch	DMA against the CPU
0001E988h	none	292	590	4647 to 4651
0001F988h	INTP	292	592	4650
0001C988h	RDPRI	292	590	4650
0001A988h	NOPAD	292	591	4650 to 4653
00016988h	BGNT	292	591	never finished
0000E988h	LDSCH	357	591	4652 to 4653
0003E988h	NOSTR	292	624	4646 to 4651
0001E188h	bit 11 cleared	1114	590	5110 to 5111

Clearing BGNT (bit 15) stopped the DMA transfer from finishing: the channel was still busy when the program gave up, and it drained once BCC was restored. Clearing LDSCH (bit 16) slowed a RAM load followed by a NOP from 292 to 357 counts and added 1 or 2 counts to the other sequences. Setting NOSTR (bit 17) slowed uncached instruction fetch from 590 to 624 counts.³ Clearing bit 11 made every cached sequence run at the uncached speed: the RAM load and its use took 590 counts against 262, and the scratchpad sequence 592 against 100.³

Narrow Reads of BCC

A word read of BCC returns 0001E988h. A byte read at offset 0 returns 88h, and byte reads at offsets 1, 2 and 3 return 00h. A halfword read at offset 0 returns E988h and at offset 2 returns 0000h. All three passes read the same values.²

Runs

22 October 2026 (link-2)

BCCBITS.txt:

BCCBITS-START bcc=0001e988
BCC base   set=0001e988 read=0001e988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=590 dmaContend=262 dmaDone=4647/4650 UNSTABLE BASE
BCC INTP   set=0001f988 read=0001f988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=592 dmaContend=262 dmaDone=4650/4650 UNSTABLE MOVED
BCC RDPRI  set=0001c988 read=0001c988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=590 dmaContend=262 dmaDone=4650/4650 same
BCC NOPAD  set=0001a988 read=0001a988 ramLoadUse=262 ramStore=70 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=591 dmaContend=262 dmaDone=4650/4653 UNSTABLE MOVED
BCC BGNT   set=00016988 read=00016988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=591 dmaContend=262 dmaDone=65535/65535 dmaLeftBusy drainedAfterRestore UNSTABLE MOVED
BCC LDSCH  set=0000e988 read=0000e988 ramLoadUse=263 ramStore=70 storeLoad=424 ramLoadNop=357 spad=101 mmio=165 ifetchUnc=591 dmaContend=263 dmaDone=4653/4652 UNSTABLE MOVED
BCC NOSTR  set=0003e988 read=0003e988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=624 dmaContend=262 dmaDone=4651/4646 UNSTABLE MOVED
BCC ctl-IS1 set=0001e188 read=0001e188 ramLoadUse=590 ramStore=317 storeLoad=727 ramLoadNop=1114 spad=592 mmio=296 ifetchUnc=590 dmaContend=590 dmaDone=5110/5111 UNSTABLE MOVED
BCC base   set=0001e988 read=0001e988 ramLoadUse=262 ramStore=69 storeLoad=422 ramLoadNop=292 spad=100 mmio=163 ifetchUnc=590 dmaContend=262 dmaDone=4651/4651 UNSTABLE same
BCCBITS-DONE
ResetGraph:jtb=801e78b8,env=801e7900

bench.txt:

1668 bytes of TTY text in psx.log

when.txt:

20261022T2232Z

22 October 2026 (link-3)

BCCNARROW.txt:

BCCN-START
BCCN rep=0 lw +0 0001e988
BCCN rep=0 BEFORE lb +0
BCCN rep=0 lb +0 88
BCCN rep=0 BEFORE lb +1
BCCN rep=0 lb +1 00
BCCN rep=0 BEFORE lb +2
BCCN rep=0 lb +2 00
BCCN rep=0 BEFORE lb +3
BCCN rep=0 lb +3 00
BCCN rep=0 BEFORE lh +0
BCCN rep=0 lh +0 e988
BCCN rep=0 BEFORE lh +2
BCCN rep=0 lh +2 0000
BCCN rep=1 lw +0 0001e988
BCCN rep=1 BEFORE lb +0
BCCN rep=1 lb +0 88
BCCN rep=1 BEFORE lb +1
BCCN rep=1 lb +1 00
BCCN rep=1 BEFORE lb +2
BCCN rep=1 lb +2 00
BCCN rep=1 BEFORE lb +3
BCCN rep=1 lb +3 00
BCCN rep=1 BEFORE lh +0
BCCN rep=1 lh +0 e988
BCCN rep=1 BEFORE lh +2
BCCN rep=1 lh +2 0000
BCCN rep=2 lw +0 0001e988
BCCN rep=2 BEFORE lb +0
BCCN rep=2 lb +0 88
BCCN rep=2 BEFORE lb +1
BCCN rep=2 lb +1 00
BCCN rep=2 BEFORE lb +2
BCCN rep=2 lb +2 00
BCCN rep=2 BEFORE lb +3
BCCN rep=2 lb +3 00
BCCN rep=2 BEFORE lh +0
BCCN rep=2 lh +0 e988
BCCN rep=2 BEFORE lh +2
BCCN rep=2 lh +2 0000
BCCN-DONE
ResetGraph:jtb=801e78b8,env=801e7900

bench.txt:

940 bytes of TTY text in psx.log

Output files that match an earlier run: when.txt (as run 20261022T2232Z-5501a-link-2).

References

^ ^a ^b pcsx-redux nugget, tests/bcc-bits/bcc-bits.c, header comment and the ctl-IS1 control row. MIT License. https://github.com/pcsx-redux/nugget
^ ^a ^b Hardware test run 20261022T2232Z-5501a-link-3 on the SCPH-5501: BCCNARROW.txt.
^ ^a ^b ^c Hardware test run 20261022T2232Z-5501a-link-2 on the SCPH-5501: BCCBITS.txt.

Categories: Hardware tests