CPU Core and Bus: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ### Bus Errors on Unused Addresses | ### Bus Errors on Unused Addresses | ||
| − | A load of a word, a halfword or a byte from KUSEG above the first 512MB raises a data bus error (exception code 7). The test read 7FFAF614h, 20000000h, 40000000h and 7FFFFFFCh. In every case the target register kept 5A5A5A5Ah, so the load did not complete, and BadVaddr did not change.[^runh] | + | A load of a word, a halfword or a byte from KUSEG above the first 512MB raises a data bus error (exception code 7). The test read 7FFAF614h, 20000000h, 40000000h and 7FFFFFFCh. In every case the target register kept 5A5A5A5Ah, so the load did not complete, and BadVaddr did not change.[^runh] A store to 7FFAF614h or 20000000h raises the same data bus error.[^runh] |
| − | A store to 7FFAF614h or 20000000h raises the same data bus error.[^runh] | ||
| − | |||
| ### Exceptions | ### Exceptions | ||