CPU Core and Bus
Measures CPU exceptions, arithmetic results, load delays, bus errors, mirrors, cache and instruction timing.
| Machine | SCPH-5501 |
|---|---|
| Program | cpu_bus and cpu_core |
This is an old revision of this page, as edited by RemmyLee at 05:11, 23 October 2026. Edit this revision | Latest revision
Overview
The program runs a series of groups on the CPU, each of which prints what the console did rather than a pass or a fail. The groups cover loads from addresses that nothing answers, exceptions, the results of the arithmetic instructions, unaligned loads and stores, load and coprocessor delays, multiply, divide and memory timing, memory mirrors, the instruction cache, the COP0 debug registers, bus errors on stores, BREAK and SYSCALL, and a data break that traps.1
Each load that may fault first fills its target register with 5A5A5A5Ah. A load that the exception handler skipped therefore leaves 5A5A5A5Ah in the register, and a load that completed replaces it. The exception handler records how many exceptions occurred, the exception code and BD bit of the last one, EPC and BadVaddr.1
Timings use root counter 2 counting system clock cycles with interrupts disabled. Each timed line is 100 turns of a short loop, and the line reports the total count for the 100 turns.1
Results
Bus Errors on Unused Addresses
A load of a word, a halfword or a byte from KUSEG above the first 512MB raises a data bus error (exception code 7). The test read 7FFAF614h, 20000000h, 40000000h and 7FFFFFFCh. In every case the target register kept 5A5A5A5Ah, so the load did not complete, and BadVaddr did not change.1
A store to 7FFAF614h or 20000000h raises the same data bus error.1
Exceptions
The exceptions taken by single instructions were as follows:1
| Instruction | Exception code | Result |
|---|---|---|
| lw or lh from an address 1 or 2 past alignment | 4 (address error, load) | EPC is the load; BadVaddr is the address; the register is unchanged |
| sw or sh to an address 1 past alignment | 5 (address error, store) | EPC is the store; BadVaddr is the address |
| add or addi of 7FFFFFFFh and 1, sub of 80000000h and 1 | 12 (overflow) | EPC is the instruction; the register is unchanged |
| primary opcode 3Fh, SPECIAL function 01h | 10 (reserved instruction) | EPC is the instruction |
| lw from 7FFAF614h | 7 (bus error, data) | EPC is the load; the register is unchanged |
| jump to an address 2 past alignment | 4 (address error, load) | EPC and BadVaddr are the jump target |
| jump to 7FFAF610h | 6 (bus error, instruction) | EPC is the jump target |
A misaligned load in the delay slot of JR, and an overflowing ADD in the delay slot of a taken BEQ, both set the BD bit of Cause. EPC then holds the address of the branch.1
A data bus error is not taken at the load or store that caused it. The test followed the access with 16 ADDIU instructions that each count by one, and the exception handler skips the instruction at EPC. After a load from 7FFAF614h, EPC pointed 16 bytes past the load, at the fourth ADDIU, and the count was 15. A store behaved the same way. When the loaded register was used by the second instruction after the load, EPC pointed to the load itself and all 16 ADDIU instructions ran.1
Arithmetic Results
Division by zero does not raise an exception. The quotient and remainder it leaves are as follows:1
| Instruction | Dividend | HI | LO |
|---|---|---|---|
| div | 00000001h | 00000001h | FFFFFFFFh |
| div | FFFFFFFFh | FFFFFFFFh | 00000001h |
| div | 00000000h | 00000000h | FFFFFFFFh |
| div | 80000000h | 80000000h | 00000001h |
| div | 7FFFFFFFh | 7FFFFFFFh | FFFFFFFFh |
| divu | any of the above | the dividend | FFFFFFFFh |
DIV of 80000000h by FFFFFFFFh gives LO 80000000h and HI 0 without an exception. MULT and MULTU give the full 64-bit product: 7FFFFFFFh times 7FFFFFFFh is 3FFFFFFF00000001h for both, and FFFFFFFFh times FFFFFFFFh is 0000000000000001h for MULT and FFFFFFFE00000001h for MULTU.1
SLLV, SRLV and SRAV use only the low 5 bits of the shift amount. A shift by 20h acted as a shift by 0, and shifts by 21h and FFFFFFE1h acted as a shift by 1.1
Unaligned Loads and Stores
With memory holding 44332211h and 88776655h and the register holding AABBCCDDh, LWL and LWR merged the bytes as follows:1
| Offset | LWL | LWR |
|---|---|---|
| +0 | 11BBCCDDh | 44332211h |
| +1 | 2211CCDDh | AA443322h |
| +2 | 332211DDh | AABB4433h |
| +3 | 44332211h | AABBCC44h |
An LWR placed in the load delay of an LWL to the same register merges with the LWL's result: LWL +3 then LWR +0 gave 44332211h. The same holds after a plain LW to that register. Read inside the LWR's own delay slot, the register still held AABBCCDDh, and one instruction later it held AA443322h.1
Load and Coprocessor Delays
A register loaded by LW still holds its old value in the instruction after the load, and holds the loaded value one instruction later. An LI to the same register in the delay slot wins over the load. MFC0 has the same one-instruction delay.1
A GTE register written by MTC2, LWC2 or CTC2 still reads its old value when MFC2 or CFC2 follows at once or after one NOP. It reads the new value after two NOPs. The same holds for a command that reads the register: SQR issued at once or after one NOP squared the old IR1, and after two NOPs the new one.1
RTPS, RTPT and MVMVA issued at once after a write of their vector, or of TRZ or TRX, used the new value. NCCS used a new RGBC at once as well. INTPL issued at once after MTC2 took the old IR1 but the new IR3.1
A BEQ, JR or JALR placed in the delay slot of another branch runs one instruction of the first branch's target before taking its own branch. JAL leaves RA 8 bytes past the JAL.1
Instruction and Memory Timing
Each timed loop is 100 turns of the operation, an MFLO and the loop's own counter and branch. The loop with a NOP in place of the operation took 547 cycles.1
| Operation | Cycles |
|---|---|
| nop | 547 |
| mult with rs 0 to 7FFh | 1127 |
| mult with rs 800h to FFFFFh | 1427 |
| mult with rs 100000h and above | 1827 |
| mult with rs FFFFFFFFh | 1127 |
| multu with rs FFFFFFFFh | 1852 |
| div 12345678h by 3 | 4147 |
| div by 0 | 4147 |
| mult then 20 nops, then mflo | 2572 |
The time of a multiply depends on rs and not on rt: with rs fixed at 3 every rt gave 1127 to 1147. Twenty NOPs between the multiply and MFLO hide the multiply completely, as the loop then takes the same 2572 cycles as 20 NOPs alone. A divide takes about 36 cycles, so it runs past 20 NOPs.1
MTLO or MTHI right after a busy multiply does not wait for it. The loop with mult then mtlo took 541 cycles, the same as the NOP loop, where mult then mfhi took 1837.1
The cost of a load depends on the region it reads:1
| Region | Access | Cycles |
|---|---|---|
| RAM, KSEG0 or KSEG1 | lw | 954 to 956 |
| Scratchpad | lw | 545 |
| Cache control FFFE0130h | lw | 544 |
| BIOS ROM | lw | 2940 |
| BIOS ROM | lh | 1753 |
| BIOS ROM | lb | 1148 |
| Expansion 1 | lb | 1149 |
| Expansion 2 | lb | 1547 |
| Expansion 3 | lh or lb | 1053 to 1060 |
| I_STAT, DPCR, timer 0, GPUSTAT, MDEC status | lw | 744 to 750 |
| JOY_STAT | lh | 748 |
| CD-ROM status | lb | 1247 |
| SPUSTAT | lh | 2251 |
| SPU, a 32-bit read | lw | 4240 |
A loop of stores to RAM grows with the number of stores: 446 cycles for one store a turn, 667 for three, 887 for four and 1722 for eight. One to three stores a turn cost little, and from the fourth each store adds about 2 cycles a turn.1
Code run from KSEG1, which bypasses the instruction cache, is several times slower. The NOP loop took 3103 cycles from KSEG1 against 547 from KSEG0.1
Memory Mirrors and Memory Control
After the BIOS has set up the console, the memory control registers read as follows:1
| Address | Value |
|---|---|
| 1F801000h | 1F000000h |
| 1F801004h | 1F802000h |
| 1F801008h | 0013243Fh |
| 1F80100Ch | 00003022h |
| 1F801010h | 0013243Fh |
| 1F801014h | 200931E1h |
| 1F801018h | 00020843h |
| 1F80101Ch | 00070777h |
| 1F801020h | 00031125h |
| 1F801060h (RAM_SIZE) | 03E00B88h |
| FFFE0130h (cache control) | 0001E988h |
The 2MB of RAM repeats every 2MB through the first 8MB of KUSEG, and the same word appears in KSEG0 and KSEG1. The scratchpad appears at 1F800000h in KUSEG and at 9F800000h in KSEG0. The BIOS ROM appears at 1FC00000h, 9FC00000h and BFC00000h.1
The upper half of RAM_SIZE is not driven. A read of RAM_SIZE therefore returns in its upper half the last value seen on the bus. The test placed a store a few instructions before an instruction cache line fill and then read RAM_SIZE. After the fill alone the upper half was 3C00h, which is the upper half of the last word of the filled line. A store to I_MASK one or two instructions before the fill left the upper half at 0000h, and three instructions before it left 3C00h. A store to RAM made no difference.1
Instruction Cache
The test ran a function that returns 1, changed its code in memory to return 2 and ran it again without flushing the cache. Through KSEG0 it still returned 1, and through KSEG1 it returned 2. After FlushCache, KSEG0 returned 2.1
A loop run twice from KSEG0 took 325 cycles the first time and 304 the second, once its code was in the cache. The same loop from KSEG1 took 1848 cycles both times.1
COP0 Debug Registers
BPC, BDA, BDAM and BPCM read back FFFFFFFFh after all ones were written. DCIC written with all ones read back 0000C03Fh.1
With a break armed, DCIC records which break occurred:1
| Event | DCIC |
|---|---|
| Data read break, watched word read | 2680000Dh |
| Data write break, watched word written | 2A800015h |
| Data read break, another word read | 26800000h |
| PC break, target called | 21800003h |
| Data read break, read with interrupts on | 26800000h |
With the trap bit set, a data break jumps to 80000040h with Cause code 9. After it the test read DCIC 0, Cause 00000024h and EPC at the load that hit the break.1
BREAK and SYSCALL
BREAK raises exception code 9 with EPC at the instruction. SYSCALL 0 and SYSCALL 4 reached no handler of the program, because the BIOS's own handler took them.1
Runs
25 September 2026 (card-cpu)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
14 tests
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02B68 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause C0000024 EPC BFC02B78 PRId 00000002
===== 01 BUK CPU BUS KUSEG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/bus kuseg past 512MB
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
Done.
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 80016068 at 80016068 badvaddr 80024BB9 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 800160A0 at 800160A0 badvaddr 80024BBA reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80016084 at 80016084 badvaddr 80024BB9 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 800160BC at 800160BC badvaddr 80024BB9 reg 44332211
sh +1: n 1 code 5 bd 0 epc 800160D0 at 800160D0 badvaddr 80024BB9 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 800160E8 at 800160E8 badvaddr 80024BB9 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 80016100 at 80016100 badvaddr 80024BB9 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 80016118 at 80016118 badvaddr 80024BB9 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 80016128 at 80016128 badvaddr 80024BB9 reg 00000000
special 01h: n 1 code 10 bd 0 epc 80016138 at 80016138 badvaddr 80024BB9 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 80016158 at 80016150 badvaddr 80024BB9 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80016178 at 80016170 badvaddr 80024BB9 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 800161C4 at 800161C4 badvaddr 80024BB9 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80016228 at 80016220 badvaddr 80024BB9 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 80015E60 at 80015E60 badvaddr 80024BB9 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 80015E68 at 80015E68 badvaddr 80024BB9 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 80016166 at 80016166 badvaddr 80016166 reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 80016166 reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 545 cycles for 100
nop, 20 nops 00000000 00000000: 2575 cycles for 100
mult 00000000 00000003: 1145 cycles for 100
multu 00000000 00000003: 1145 cycles for 100
mult rt 00000003 00000000: 1125 cycles for 100
mult 00000001 00000003: 1125 cycles for 100
multu 00000001 00000003: 1133 cycles for 100
mult rt 00000003 00000001: 1125 cycles for 100
mult 000007FF 00000003: 1125 cycles for 100
multu 000007FF 00000003: 1133 cycles for 100
mult rt 00000003 000007FF: 1125 cycles for 100
mult 00000800 00000003: 1425 cycles for 100
multu 00000800 00000003: 1433 cycles for 100
mult rt 00000003 00000800: 1125 cycles for 100
mult 000FFFFF 00000003: 1425 cycles for 100
multu 000FFFFF 00000003: 1433 cycles for 100
mult rt 00000003 000FFFFF: 1125 cycles for 100
mult 00100000 00000003: 1825 cycles for 100
multu 00100000 00000003: 1833 cycles for 100
mult rt 00000003 00100000: 1125 cycles for 100
mult 7FFFFFFF 00000003: 1825 cycles for 100
multu 7FFFFFFF 00000003: 1833 cycles for 100
mult rt 00000003 7FFFFFFF: 1125 cycles for 100
mult FFFFFFFF 00000003: 1125 cycles for 100
multu FFFFFFFF 00000003: 1833 cycles for 100
mult rt 00000003 FFFFFFFF: 1125 cycles for 100
mult 80000000 00000003: 1825 cycles for 100
multu 80000000 00000003: 1833 cycles for 100
mult rt 00000003 80000000: 1125 cycles for 100
div 12345678 00000003: 4145 cycles for 100
divu 12345678 00000003: 4145 cycles for 100
div by 0 12345678 00000000: 4145 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2570 cycles for 100
div, 20 nops 12345678 00000003: 4158 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 03E00B88
cache control FFFE0130: 0001E988
RAM word at 00026E1C holds C0FFEE01
KUSEG 00026E1C: C0FFEE01
KUSEG +2MB 00226E1C: C0FFEE01
KUSEG +4MB 00426E1C: C0FFEE01
KUSEG +6MB 00626E1C: C0FFEE01
KSEG0 +2MB 80226E1C: C0FFEE01
KSEG1 A0026E1C: C0FFEE01
KSEG1 +6MB A0626E1C: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
scratchpad KSEG1 BF800000:
26 September 2026 (card-cpu-1)
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 80016AF8 at 80016AF8 badvaddr 80027371 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80016B30 at 80016B30 badvaddr 80027372 reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80016B14 at 80016B14 badvaddr 80027371 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80016B4C at 80016B4C badvaddr 80027371 reg 44332211
sh +1: n 1 code 5 bd 0 epc 80016B60 at 80016B60 badvaddr 80027371 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80016B78 at 80016B78 badvaddr 80027371 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 80016B90 at 80016B90 badvaddr 80027371 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 80016BA8 at 80016BA8 badvaddr 80027371 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 80016BB8 at 80016BB8 badvaddr 80027371 reg 00000000
special 01h: n 1 code 10 bd 0 epc 80016BC8 at 80016BC8 badvaddr 80027371 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 80016BE8 at 80016BE0 badvaddr 80027371 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80016C08 at 80016C00 badvaddr 80027371 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 80016C54 at 80016C54 badvaddr 80027371 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80016CB8 at 80016CB0 badvaddr 80027371 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 800167D0 at 800167D0 badvaddr 80027371 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 800167D8 at 800167D8 badvaddr 80027371 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 80016BF6 at 80016BF6 badvaddr 80016BF6 reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 80016BF6 reg 00000000
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: 00010002, four later 00030004
mtc2, 1 nop, mfc2: 00010002, four later 00030004
mtc2, 2 nops, mfc2: 00030004, four later 00030004
mtc2, 3 nops, mfc2: 00030004, four later 00030004
lwc2 then mfc2 at once: 00010002, four later 00030004
lwc2, 1 nop, mfc2: 00010002, four later 00030004
lwc2, 2 nops, mfc2: 00030004, four later 00030004
lwc2, 3 nops, mfc2: 00030004, four later 00030004
ctc2 then cfc2 at once: 00010002, four later 00030004
ctc2, 1 nop, cfc2: 00010002, four later 00030004
ctc2, 2 nops, cfc2: 00030004, four later 00030004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 547 cycles for 100
nop, 20 nops 00000000 00000000: 2576 cycles for 100
mult 00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1127 cycles for 100
mult 00000001 00000003: 1127 cycles for 100
multu 00000001 00000003: 1135 cycles for 100
mult rt 00000003 00000001: 1127 cycles for 100
mult 000007FF 00000003: 1127 cycles for 100
multu 000007FF 00000003: 1135 cycles for 100
mult rt 00000003 000007FF: 1127 cycles for 100
mult 00000800 00000003: 1427 cycles for 100
multu 00000800 00000003: 1435 cycles for 100
mult rt 00000003 00000800: 1127 cycles for 100
mult 000FFFFF 00000003: 1427 cycles for 100
multu 000FFFFF 00000003: 1435 cycles for 100
mult rt 00000003 000FFFFF: 1127 cycles for 100
mult 00100000 00000003: 1827 cycles for 100
multu 00100000 00000003: 1835 cycles for 100
mult rt 00000003 00100000: 1127 cycles for 100
mult 7FFFFFFF 00000003: 1827 cycles for 100
multu 7FFFFFFF 00000003: 1835 cycles for 100
mult rt 00000003 7FFFFFFF: 1127 cycles for 100
mult FFFFFFFF 00000003: 1153 cycles for 100
multu FFFFFFFF 00000003: 1842 cycles for 100
mult rt 00000003 FFFFFFFF: 1127 cycles for 100
mult 80000000 00000003: 1827 cycles for 100
multu 80000000 00000003: 1835 cycles for 100
mult rt 00000003 80000000: 1127 cycles for 100
div 12345678 00000003: 4147 cycles for 100
divu 12345678 00000003: 4147 cycles for 100
div by 0 12345678 00000000: 4132 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2576 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1848 cycles for 100
mult, 2 nops, mflo: 1850 cycles for 100
mult, 3 nops, mflo: 1853 cycles for 100
mult, 4 nops, mflo: 1853 cycles for 100
mult, 5 nops, mflo: 1859 cycles for 100
mult, 6 nops, mflo: 1860 cycles for 100
mult, 7 nops, mflo: 1858 cycles for 100
mult, 8 nops, mflo: 1852 cycles for 100
mult, 9 nops, mflo: 1861 cycles for 100
mult, 10 nops, mflo: 1862 cycles for 100
mult, 11 nops, mflo: 1860 cycles for 100
mult, 12 nops, mflo: 1771 cycles for 100
mult, 13 nops, mflo: 1873 cycles for 100
mult, 14 nops, mflo: 1976 cycles for 100
div, 5 nops, mflo: 4143 cycles for 100
div, 10 nops, mflo: 4147 cycles for 100
div, 30 nops, mflo: 4181 cycles for 100
div, 33 nops, mflo: 4185 cycles for 100
div, 34 nops, mflo: 4193 cycles for 100
div, 35 nops, mflo: 4088 cycles for 100
div, 36 nops, mflo: 4192 cycles for 100
div, 37 nops, mflo: 4300 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1849 cycles for 100
mult, no read: 448 cycles for 100
div, no read: 448 cycles for 100
mult then mtlo: 558 cycles for 100
mult then mthi: 554 cycles for 100
mult then mult then mflo: 1953 cycles for 100
mult then mtlo then mflo: 655 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 800298F0 lw: 971 cycles for 100
RAM KSEG1 A00298F0 lw: 965 cycles for 100
scratchpad 1F800100 lw: 563 cycles for 100
BIOS BFC00100 lw: 2953 cycles for 100
BIOS BFC00100 lh: 1756 cycles for 100
BIOS BFC00100 lb: 1153 cycles for 100
EXP1 1F000084 lb: 1153 cycles for 100
EXP2 1F802000 lb: 1553 cycles for 100
EXP3 1FA00000 lh: 1053 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 757 cycles for 100
DPCR 1F8010F0 lw: 757 cycles for 100
timer 0 1F801100 lw: 757 cycles for 100
JOY_STAT 1F801044 lh: 757 cycles for 100
CDROM status 1F801800 lb: 1259 cycles for 100
GPUSTAT 1F801814 lw: 757 cycles for 100
MDEC status 1F801824 lw: 762 cycles for 100
SPUSTAT 1F801DAE lh: 2253 cycles for 100
SPU word 1F801DAC lw: 4253 cycles for 100
cache control FFFE0130 lw: 557 cycles for 100
RAM lw, used at once: 971 cycles for 100
RAM lw, used after 1 nop: 1268 cycles for 100
RAM lw, used after 2 nops: 1363 cycles for 100
RAM lw, used after 3 nops: 1367 cycles for 100
RAM lw then lw: 1464 cycles for 100
BIOS lw, used at once: 2945 cycles for 100
BIOS lw, used after 3 nops: 3330 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 456 cycles for 100
RAM, 2 sw: 568 cycles for 100
RAM, 3 sw: 688 cycles for 100
RAM, 4 sw: 904 cycles for 100
RAM, 5 sw: 1117 cycles for 100
RAM, 6 sw: 1328 cycles for 100
RAM, 7 sw: 1519 cycles for 100
RAM, 8 sw: 1736 cycles for 100
RAM, 4 sw then lw: 2114 cycles for 100
RAM, sw then lw: 1474 cycles for 100
scratchpad, 1 sw: 427 cycles for 100
scratchpad, 8 sw: 1151 cycles for 100
I_MASK, 1 sw: 430 cycles for 100
I_MASK, 4 sw: 852 cycles for 100
I_MASK, sw then lw: 842 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3110 cycles for 100
nop, 20 nops loop: 15302 cycles for 100
RAM lw loop: 3521 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 27BD0B88
cache control FFFE0130: 0001E988
RAM word at 00029634 holds C0FFEE01
KUSEG 00029634: C0FFEE01
KUSEG +2MB 00229634: C0FFEE01
KUSEG +4MB 00429634: C0FFEE01
KUSEG +6MB 00629634: C0FFEE01
KSEG0 +2MB 80229634: C0FFEE01
KSEG1 A0029634: C0FFEE01
KSEG1 +6MB A0629634: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 32240009, 1 before the fill: 00000B88
I_MASK store 32240009, 2 before the fill: 00000B88
I_MASK store 32240009, 3 before the fill: 3C000B88
probe at 8002BA50
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/instruction cache (code at 8002BB60)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 1
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 2
loop from KSEG0: 325 then 304 cycles
loop from KSEG1: 1855 then 1848 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/bus writes
sw 7FFAF614: exception 7, reg 12345678, badvaddr 80016BF6 to 80016BF6
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 80016BF6 to 80016BF6
sw 20000000: exception 7, reg 12345678, badvaddr 80016BF6 to 80016BF6
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 80016BF6 to 80016BF6
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001A510 at 8001A510 badvaddr 80016BF6 reg 00000000
syscall 0: none, at 8001A528, reg 00000000
syscall 4: none, at 8001A528, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001A2F8, the load at 8001A2F8, value read 00000002
Done.
Output files that match an earlier run: 00RUN.txt (as run 20260925T0000Z-5501a-card-cpu) · 01BUK.txt (as run 20260925T0000Z-5501a-card-cpu) · 03ALU.txt (as run 20260925T0000Z-5501a-card-cpu) · 04LWX.txt (as run 20260925T0000Z-5501a-card-cpu).
26 September 2026 (card-cpu-3)
===== 01 BUK CPU BUS KUSEG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
cpu/bus kuseg past 512MB
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lw 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lhu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
lbu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000480 to 00000480
Done.
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 80017204 at 80017204 badvaddr 80028F61 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 8001723C at 8001723C badvaddr 80028F62 reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80017220 at 80017220 badvaddr 80028F61 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80017258 at 80017258 badvaddr 80028F61 reg 44332211
sh +1: n 1 code 5 bd 0 epc 8001726C at 8001726C badvaddr 80028F61 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80017284 at 80017284 badvaddr 80028F61 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 8001729C at 8001729C badvaddr 80028F61 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 800172B4 at 800172B4 badvaddr 80028F61 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 800172C4 at 800172C4 badvaddr 80028F61 reg 00000000
special 01h: n 1 code 10 bd 0 epc 800172D4 at 800172D4 badvaddr 80028F61 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 800172F8 at 800172EC badvaddr 80028F61 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80028F61 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 80017360 at 80017360 badvaddr 80028F61 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80028F61 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 80016EDC at 80016EDC badvaddr 80028F61 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 80016EE4 at 80016EE4 badvaddr 80028F61 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 80017302 at 80017302 badvaddr 80017302 reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 80017302 reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: 00010002, four later 00030004
mtc2, 1 nop, mfc2: 00030004, four later 00030004
mtc2, 2 nops, mfc2: 00030004, four later 00030004
mtc2, 3 nops, mfc2: 00030004, four later 00030004
lwc2 then mfc2 at once: 00010002, four later 00030004
lwc2, 1 nop, mfc2: 00010002, four later 00030004
lwc2, 2 nops, mfc2: 00030004, four later 00030004
lwc2, 3 nops, mfc2: 00030004, four later 00030004
ctc2 then cfc2 at once: 00010002, four later 00030004
ctc2, 1 nop, cfc2: 00030004, four later 00030004
ctc2, 2 nops, cfc2: 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: 00000010, four later 00000100
mtc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: 00000010, four later 00000100
lwc2 IR1 then SQR at once: 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: 00000004, four later 00000010
mtc2 then swc2 at once: 00010002, four later 00030004
mtc2, 1 nop, swc2: 00010002, four later 00030004
mtc2, 2 nops, swc2: 00030004, four later 00030004
mtc2 IR1, lw, SQR: 00000010, four later 00000100
mtc2 IR1, mtc2 VXY0, SQR: 00000010, four later 00000100
lwc2 IR1, lwc2 VXY0, SQR: 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: 00000004, four later 00000004
ctc2 TRZ then RTPT at once: 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: 00030008, four later 00030008
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 550 cycles for 100
nop, 20 nops 00000000 00000000: 2572 cycles for 100
mult 00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1147 cycles for 100
mult 00000001 00000003: 1147 cycles for 100
multu 00000001 00000003: 1142 cycles for 100
mult rt 00000003 00000001: 1147 cycles for 100
mult 000007FF 00000003: 1147 cycles for 100
multu 000007FF 00000003: 1142 cycles for 100
mult rt 00000003 000007FF: 1147 cycles for 100
mult 00000800 00000003: 1447 cycles for 100
multu 00000800 00000003: 1442 cycles for 100
mult rt 00000003 00000800: 1147 cycles for 100
mult 000FFFFF 00000003: 1447 cycles for 100
multu 000FFFFF 00000003: 1442 cycles for 100
mult rt 00000003 000FFFFF: 1147 cycles for 100
mult 00100000 00000003: 1853 cycles for 100
multu 00100000 00000003: 1842 cycles for 100
mult rt 00000003 00100000: 1147 cycles for 100
mult 7FFFFFFF 00000003: 1847 cycles for 100
multu 7FFFFFFF 00000003: 1842 cycles for 100
mult rt 00000003 7FFFFFFF: 1147 cycles for 100
mult FFFFFFFF 00000003: 1147 cycles for 100
multu FFFFFFFF 00000003: 1842 cycles for 100
mult rt 00000003 FFFFFFFF: 1147 cycles for 100
mult 80000000 00000003: 1847 cycles for 100
multu 80000000 00000003: 1842 cycles for 100
mult rt 00000003 80000000: 1147 cycles for 100
div 12345678 00000003: 4147 cycles for 100
divu 12345678 00000003: 4147 cycles for 100
div by 0 12345678 00000000: 4149 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2572 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1848 cycles for 100
mult, 2 nops, mflo: 1844 cycles for 100
mult, 3 nops, mflo: 1847 cycles for 100
mult, 4 nops, mflo: 1847 cycles for 100
mult, 5 nops, mflo: 1848 cycles for 100
mult, 6 nops, mflo: 1857 cycles for 100
mult, 7 nops, mflo: 1852 cycles for 100
mult, 8 nops, mflo: 1852 cycles for 100
mult, 9 nops, mflo: 1861 cycles for 100
mult, 10 nops, mflo: 1868 cycles for 100
mult, 11 nops, mflo: 1866 cycles for 100
mult, 12 nops, mflo: 1772 cycles for 100
mult, 13 nops, mflo: 1864 cycles for 100
mult, 14 nops, mflo: 1970 cycles for 100
div, 5 nops, mflo: 4146 cycles for 100
div, 10 nops, mflo: 4152 cycles for 100
div, 30 nops, mflo: 4181 cycles for 100
div, 33 nops, mflo: 4191 cycles for 100
div, 34 nops, mflo: 4199 cycles for 100
div, 35 nops, mflo: 4088 cycles for 100
div, 36 nops, mflo: 4192 cycles for 100
div, 37 nops, mflo: 4304 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1850 cycles for 100
mult, no read: 455 cycles for 100
div, no read: 448 cycles for 100
mult then mtlo: 548 cycles for 100
mult then mthi: 548 cycles for 100
mult then mult then mflo: 1947 cycles for 100
mult then mtlo then mflo: 655 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 8002B4E0 lw: 971 cycles for 100
RAM KSEG1 A002B4E0 lw: 965 cycles for 100
scratchpad 1F800100 lw: 557 cycles for 100
BIOS BFC00100 lw: 2953 cycles for 100
BIOS BFC00100 lh: 1753 cycles for 100
BIOS BFC00100 lb: 1159 cycles for 100
EXP1 1F000084 lb: 1153 cycles for 100
EXP2 1F802000 lb: 1553 cycles for 100
EXP3 1FA00000 lh: 1053 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 757 cycles for 100
DPCR 1F8010F0 lw: 757 cycles for 100
timer 0 1F801100 lw: 757 cycles for 100
JOY_STAT 1F801044 lh: 757 cycles for 100
CDROM status 1F801800 lb: 1258 cycles for 100
GPUSTAT 1F801814 lw: 757 cycles for 100
MDEC status 1F801824 lw: 757 cycles for 100
SPUSTAT 1F801DAE lh: 2253 cycles for 100
SPU word 1F801DAC lw: 4253 cycles for 100
cache control FFFE0130 lw: 558 cycles for 100
RAM lw, used at once: 969 cycles for 100
RAM lw, used after 1 nop: 1275 cycles for 100
RAM lw, used after 2 nops: 1374 cycles for 100
RAM lw, used after 3 nops: 1368 cycles for 100
RAM lw then lw: 1473 cycles for 100
BIOS lw, used at once: 2953 cycles for 100
BIOS lw, used after 3 nops: 3356 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 456 cycles for 100
RAM, 2 sw: 571 cycles for 100
RAM, 3 sw: 678 cycles for 100
RAM, 4 sw: 899 cycles for 100
RAM, 5 sw: 1111 cycles for 100
RAM, 6 sw: 1328 cycles for 100
RAM, 7 sw: 1535 cycles for 100
RAM, 8 sw: 1747 cycles for 100
RAM, 4 sw then lw: 2117 cycles for 100
RAM, sw then lw: 1483 cycles for 100
scratchpad, 1 sw: 448 cycles for 100
scratchpad, 8 sw: 1155 cycles for 100
I_MASK, 1 sw: 452 cycles for 100
I_MASK, 4 sw: 852 cycles for 100
I_MASK, sw then lw: 848 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1477 cycles for 100
RAM sw, 2 nops, lw: 1483 cycles for 100
RAM sw, 3 nops, lw: 1492 cycles for 100
RAM sw, 4 nops, lw: 1479 cycles for 100
RAM sw, 6 nops, lw: 1576 cycles for 100
RAM sw, lw of another word: 1472 cycles for 100
RAM 4 sw, lw of another word: 2108 cycles for 100
chain-looping's loop: 1659 cycles for 100
RAM lw, used after 4 nops: 1367 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 757 cycles for 100
I_STAT lw, used after 1 nop: 1056 cycles for 100
I_STAT lw, used after 2 nops: 1155 cycles for 100
I_STAT lw then lw: 1152 cycles for 100
BIOS lw, used after 1 nop: 3256 cycles for 100
BIOS lw, used after 2 nops: 3355 cycles for 100
BIOS lw then lw: 5451 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 449 cycles for 100
GP0 NOP, 4 sw: 837 cycles for 100
CDROM index, 1 sb: 631 cycles for 100
CDROM index, 4 sb: 2433 cycles for 100
SPU main volume, 1 sh: 822 cycles for 100
SPU main volume, 4 sh: 3211 cycles for 100
scratchpad, 4 sw: 752 cycles for 100
RAM, 1 sh: 436 cycles for 100
RAM, 4 sh: 885 cycles for 100
RAM, 4 sb: 869 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 655 cycles for 100
mult, mthi, mflo: 648 cycles for 100
mult, mtlo, mfhi: 648 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3112 cycles for 100
nop, 20 nops loop: 15298 cycles for 100
RAM lw loop: 3526 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 03E00B88
cache control FFFE0130: 0001E988
RAM word at 0002B228 holds C0FFEE01
KUSEG 0002B228: C0FFEE01
KUSEG +2MB 0022B228: C0FFEE01
KUSEG +4MB 0042B228: C0FFEE01
KUSEG +6MB 0062B228: C0FFEE01
KSEG0 +2MB 8022B228: C0FFEE01
KSEG1 A002B228: C0FFEE01
KSEG1 +6MB A062B228: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 0C000009, 1 before the fill: 00000B88
I_MASK store 0C000009, 2 before the fill: 00000B88
I_MASK store 0C000009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 0C000009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 8002D730
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/bus writes
sw 7FFAF614: exception 7, reg 12345678, badvaddr 80017302 to 80017302
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
sw 20000000: exception 7, reg 12345678, badvaddr 80017302 to 80017302
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001BF98 at 8001BF98 badvaddr 80017302 reg 00000000
syscall 0: none, at 8001BFB0, reg 00000000
syscall 4: none, at 8001BFB0, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001BD80, the load at 8001BD80, value read 00000002
Done.
===== 13 BUG CPU BUS GAPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/bus gaps
lw 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 1F000000: none, reg FFFFFFFF, badvaddr 80017302 to 80017302
lhu 1F000000: none, reg 0000FFFF, badvaddr 80017302 to 80017302
lbu 1F000000: none, reg 000000FF, badvaddr 80017302 to 80017302
lw 1F801030: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 1F801030: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 1F801030: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 1FA00000: none, reg FFFFFFFF, badvaddr 80017302 to 80017302
lhu 1FA00000: none, reg 0000FFFF, badvaddr 80017302 to 80017302
lbu 1FA00000: none, reg 000000FF, badvaddr 80017302 to 80017302
lw 1FC80000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 1FC80000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 1FC80000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw A0800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu A0800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu A0800000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw C0000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu C0000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu C0000000: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 1F800400: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 1F800400: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 1F800400: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw BFC80100: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu BFC80100: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu BFC80100: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 1F801024: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 1F801024: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 1F801024: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 1F801064: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lhu 1F801064: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lbu 1F801064: exception 7, reg 5A5A5A5A, badvaddr 80017302 to 80017302
lw 00800000 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 00800000 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 10000000 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 10000000 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 1F801030 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 1F801030 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 1FC80000 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 1FC80000 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw A0800000 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw A0800000 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw C0000000 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw C0000000 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 1F800400 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 1F800400 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw BFC80100 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw BFC80100 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 1F801024 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 1F801024 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
lw 1F801064 then 16 addiu: n 1 code 7 bd 0 epc 80017318 at 8001730C badvaddr 80017302 reg 0000000F
sw 1F801064 then 16 addiu: n 1 code 7 bd 0 epc 800173C8 at 800173BC badvaddr 80017302 reg 0000000F
Done.
===== 14 ISO CPU CACHE ISOLATE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017302
cpu/cache isolation: SR bit 16 set, memory holds 11111111
1 isolate and restore, uncached code: cache word before DEADBEEF, read DEADBEEF, memory after 11111111
2 isolated lw, uncached code: cache word before DEADBEEF, read 10400026, memory after 11111111
3 isolated lw, sw 22222222, lw, sw back, uncached code: cache word before 10400026, read 22222222, memory after 11111111
4 the same from cached code:
Output files that match an earlier run: 00RUN.txt (as run 20260925T0000Z-5501a-card-cpu).
26 September 2026 (card-cpu-4)
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 80017304 at 80017304 badvaddr 8002947D reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 8001733C at 8001733C badvaddr 8002947E reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80017320 at 80017320 badvaddr 8002947D reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80017358 at 80017358 badvaddr 8002947D reg 44332211
sh +1: n 1 code 5 bd 0 epc 8001736C at 8001736C badvaddr 8002947D reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80017384 at 80017384 badvaddr 8002947D reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 8001739C at 8001739C badvaddr 8002947D reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 800173B4 at 800173B4 badvaddr 8002947D reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 800173C4 at 800173C4 badvaddr 8002947D reg 00000000
special 01h: n 1 code 10 bd 0 epc 800173D4 at 800173D4 badvaddr 8002947D reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 800173F8 at 800173EC badvaddr 8002947D reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80017418 at 8001740C badvaddr 8002947D reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 80017460 at 80017460 badvaddr 8002947D reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800174C8 at 800174BC badvaddr 8002947D reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 80016FDC at 80016FDC badvaddr 8002947D reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 80016FE4 at 80016FE4 badvaddr 8002947D reg 00000000
jump to +2: n 1 code 4 bd 0 epc 80017402 at 80017402 badvaddr 80017402 reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 80017402 reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: 00010002, four later 00030004
mtc2, 1 nop, mfc2: 00030004, four later 00030004
mtc2, 2 nops, mfc2: 00030004, four later 00030004
mtc2, 3 nops, mfc2: 00030004, four later 00030004
lwc2 then mfc2 at once: 00010002, four later 00030004
lwc2, 1 nop, mfc2: 00010002, four later 00030004
lwc2, 2 nops, mfc2: 00030004, four later 00030004
lwc2, 3 nops, mfc2: 00030004, four later 00030004
ctc2 then cfc2 at once: 00010002, four later 00030004
ctc2, 1 nop, cfc2: 00030004, four later 00030004
ctc2, 2 nops, cfc2: 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: 00000010, four later 00000100
mtc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: 00000010, four later 00000100
lwc2 IR1 then SQR at once: 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: 00000004, four later 00000010
mtc2 then swc2 at once: 00010002, four later 00030004
mtc2, 1 nop, swc2: 00010002, four later 00030004
mtc2, 2 nops, swc2: 00030004, four later 00030004
mtc2 IR1, lw, SQR: 00000010, four later 00000100
mtc2 IR1, mtc2 VXY0, SQR: 00000010, four later 00000100
lwc2 IR1, lwc2 VXY0, SQR: 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: 00000004, four later 00000004
ctc2 TRZ then RTPT at once: 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): 00000010, four later 00000010
mtc2 IR3, 1 nop, SQR (MAC3): 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): 00000040, four later 00000040
lwc2 RGBC then NCCS at once: 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: 00000004, four later 00000004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 541 cycles for 100
nop, 20 nops 00000000 00000000: 2570 cycles for 100
mult 00000000 00000003: 1141 cycles for 100
multu 00000000 00000003: 1141 cycles for 100
mult rt 00000003 00000000: 1141 cycles for 100
mult 00000001 00000003: 1141 cycles for 100
multu 00000001 00000003: 1137 cycles for 100
mult rt 00000003 00000001: 1141 cycles for 100
mult 000007FF 00000003: 1141 cycles for 100
multu 000007FF 00000003: 1135 cycles for 100
mult rt 00000003 000007FF: 1141 cycles for 100
mult 00000800 00000003: 1441 cycles for 100
multu 00000800 00000003: 1435 cycles for 100
mult rt 00000003 00000800: 1141 cycles for 100
mult 000FFFFF 00000003: 1441 cycles for 100
multu 000FFFFF 00000003: 1435 cycles for 100
mult rt 00000003 000FFFFF: 1141 cycles for 100
mult 00100000 00000003: 1846 cycles for 100
multu 00100000 00000003: 1835 cycles for 100
mult rt 00000003 00100000: 1141 cycles for 100
mult 7FFFFFFF 00000003: 1844 cycles for 100
multu 7FFFFFFF 00000003: 1835 cycles for 100
mult rt 00000003 7FFFFFFF: 1141 cycles for 100
mult FFFFFFFF 00000003: 1141 cycles for 100
multu FFFFFFFF 00000003: 1835 cycles for 100
mult rt 00000003 FFFFFFFF: 1141 cycles for 100
mult 80000000 00000003: 1841 cycles for 100
multu 80000000 00000003: 1835 cycles for 100
mult rt 00000003 80000000: 1141 cycles for 100
div 12345678 00000003: 4146 cycles for 100
divu 12345678 00000003: 4141 cycles for 100
div by 0 12345678 00000000: 4128 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2571 cycles for 100
div, 20 nops 12345678 00000003: 4155 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1841 cycles for 100
mult, 1 nops, mflo: 1842 cycles for 100
mult, 2 nops, mflo: 1839 cycles for 100
mult, 3 nops, mflo: 1851 cycles for 100
mult, 4 nops, mflo: 1847 cycles for 100
mult, 5 nops, mflo: 1848 cycles for 100
mult, 6 nops, mflo: 1857 cycles for 100
mult, 7 nops, mflo: 1843 cycles for 100
mult, 8 nops, mflo: 1846 cycles for 100
mult, 9 nops, mflo: 1855 cycles for 100
mult, 10 nops, mflo: 1857 cycles for 100
mult, 11 nops, mflo: 1860 cycles for 100
mult, 12 nops, mflo: 1762 cycles for 100
mult, 13 nops, mflo: 1864 cycles for 100
mult, 14 nops, mflo: 1974 cycles for 100
div, 5 nops, mflo: 4143 cycles for 100
div, 10 nops, mflo: 4143 cycles for 100
div, 30 nops, mflo: 4180 cycles for 100
div, 33 nops, mflo: 4180 cycles for 100
div, 34 nops, mflo: 4199 cycles for 100
div, 35 nops, mflo: 4088 cycles for 100
div, 36 nops, mflo: 4186 cycles for 100
div, 37 nops, mflo: 4294 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1839 cycles for 100
mult, no read: 444 cycles for 100
div, no read: 447 cycles for 100
mult then mtlo: 553 cycles for 100
mult then mthi: 543 cycles for 100
mult then mult then mflo: 1944 cycles for 100
mult then mtlo then mflo: 649 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 8002BA00 lw: 968 cycles for 100
RAM KSEG1 A002BA00 lw: 967 cycles for 100
scratchpad 1F800100 lw: 554 cycles for 100
BIOS BFC00100 lw: 2947 cycles for 100
BIOS BFC00100 lh: 1747 cycles for 100
BIOS BFC00100 lb: 1147 cycles for 100
EXP1 1F000084 lb: 1147 cycles for 100
EXP2 1F802000 lb: 1547 cycles for 100
EXP3 1FA00000 lh: 1047 cycles for 100
EXP3 1FA00000 lb: 1047 cycles for 100
I_STAT 1F801070 lw: 751 cycles for 100
DPCR 1F8010F0 lw: 754 cycles for 100
timer 0 1F801100 lw: 751 cycles for 100
JOY_STAT 1F801044 lh: 754 cycles for 100
CDROM status 1F801800 lb: 1247 cycles for 100
GPUSTAT 1F801814 lw: 751 cycles for 100
MDEC status 1F801824 lw: 754 cycles for 100
SPUSTAT 1F801DAE lh: 2247 cycles for 100
SPU word 1F801DAC lw: 4247 cycles for 100
cache control FFFE0130 lw: 551 cycles for 100
RAM lw, used at once: 960 cycles for 100
RAM lw, used after 1 nop: 1267 cycles for 100
RAM lw, used after 2 nops: 1361 cycles for 100
RAM lw, used after 3 nops: 1366 cycles for 100
RAM lw then lw: 1467 cycles for 100
BIOS lw, used at once: 2952 cycles for 100
BIOS lw, used after 3 nops: 3353 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 447 cycles for 100
RAM, 2 sw: 576 cycles for 100
RAM, 3 sw: 675 cycles for 100
RAM, 4 sw: 889 cycles for 100
RAM, 5 sw: 1109 cycles for 100
RAM, 6 sw: 1322 cycles for 100
RAM, 7 sw: 1529 cycles for 100
RAM, 8 sw: 1732 cycles for 100
RAM, 4 sw then lw: 2110 cycles for 100
RAM, sw then lw: 1465 cycles for 100
scratchpad, 1 sw: 442 cycles for 100
scratchpad, 8 sw: 1147 cycles for 100
I_MASK, 1 sw: 446 cycles for 100
I_MASK, 4 sw: 844 cycles for 100
I_MASK, sw then lw: 842 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1474 cycles for 100
RAM sw, 2 nops, lw: 1475 cycles for 100
RAM sw, 3 nops, lw: 1481 cycles for 100
RAM sw, 4 nops, lw: 1484 cycles for 100
RAM sw, 6 nops, lw: 1575 cycles for 100
RAM sw, lw of another word: 1458 cycles for 100
RAM 4 sw, lw of another word: 2101 cycles for 100
chain-looping's loop: 1654 cycles for 100
RAM lw, used after 4 nops: 1369 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 752 cycles for 100
I_STAT lw, used after 1 nop: 1050 cycles for 100
I_STAT lw, used after 2 nops: 1148 cycles for 100
I_STAT lw then lw: 1146 cycles for 100
BIOS lw, used after 1 nop: 3250 cycles for 100
BIOS lw, used after 2 nops: 3352 cycles for 100
BIOS lw then lw: 5445 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 443 cycles for 100
GP0 NOP, 4 sw: 826 cycles for 100
CDROM index, 1 sb: 631 cycles for 100
CDROM index, 4 sb: 2427 cycles for 100
SPU main volume, 1 sh: 819 cycles for 100
SPU main volume, 4 sh: 3210 cycles for 100
scratchpad, 4 sw: 746 cycles for 100
RAM, 1 sh: 439 cycles for 100
RAM, 4 sh: 871 cycles for 100
RAM, 4 sb: 897 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 654 cycles for 100
mult, mthi, mflo: 643 cycles for 100
mult, mtlo, mfhi: 643 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3106 cycles for 100
nop, 20 nops loop: 15298 cycles for 100
RAM lw loop: 3517 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 03E00B88
cache control FFFE0130: 0001E988
RAM word at 0002B744 holds C0FFEE01
KUSEG 0002B744: C0FFEE01
KUSEG +2MB 0022B744: C0FFEE01
KUSEG +4MB 0042B744: C0FFEE01
KUSEG +6MB 0062B744: C0FFEE01
KSEG0 +2MB 8022B744: C0FFEE01
KSEG1 A002B744: C0FFEE01
KSEG1 +6MB A062B744: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 0C000009, 1 before the fill: 00000B88
I_MASK store 0C000009, 2 before the fill: 00000B88
I_MASK store 0C000009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 0C000009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 8002DC90
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/instruction cache (code at 8002DDA0)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 1
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 2
loop from KSEG0: 319 then 318 cycles
loop from KSEG1: 1849 then 1848 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/bus writes
sw 7FFAF614: exception 7, reg 12345678, badvaddr 80017402 to 80017402
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
sw 20000000: exception 7, reg 12345678, badvaddr 80017402 to 80017402
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001C2B0, the load at 8001C2B0, value read 00000002
Done.
===== 13 ISO CPU CACHE ISOLATE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/cache isolation: SR bit 16 set, memory holds 11111111
1 isolate and restore, uncached code: cache word before DEADBEEF, read DEADBEEF, memory after 11111111
2 isolated lw, uncached code: cache word before DEADBEEF, read 8DC20000, memory after 11111111
3 isolated lw, sw 22222222, lw, sw back, uncached code: cache word before 8DC20000, read 22222222, memory after 11111111
Done.
===== 14 BUG CPU BUS GAPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017402
cpu/bus gaps
lw 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lhu 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lbu 00800000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lw 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lhu 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lbu 10000000: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lw 1F000000: none, reg FFFFFFFF, badvaddr 80017402 to 80017402
lhu 1F000000: none, reg 0000FFFF, badvaddr 80017402 to 80017402
lbu 1F000000: none, reg 000000FF, badvaddr 80017402 to 80017402
lw 1F801030: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lhu 1F801030: exception 7, reg 5A5A5A5A, badvaddr 80017402 to 80017402
lbu 1F801030:
Output files that match an earlier run: 00RUN.txt (as run 20260925T0000Z-5501a-card-cpu) · 01BUK.txt (as run 20260926T0000Z-5501a-card-cpu-3).
26 September 2026 (card-cpu-5)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02B68 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause C0000024 EPC BFC02B78 PRId 00000002
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 80017538 at 80017538 badvaddr 8002A8D1 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80017570 at 80017570 badvaddr 8002A8D2 reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80017554 at 80017554 badvaddr 8002A8D1 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 8001758C at 8001758C badvaddr 8002A8D1 reg 44332211
sh +1: n 1 code 5 bd 0 epc 800175A0 at 800175A0 badvaddr 8002A8D1 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 800175B8 at 800175B8 badvaddr 8002A8D1 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 800175D0 at 800175D0 badvaddr 8002A8D1 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 800175E8 at 800175E8 badvaddr 8002A8D1 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 800175F8 at 800175F8 badvaddr 8002A8D1 reg 00000000
special 01h: n 1 code 10 bd 0 epc 80017608 at 80017608 badvaddr 8002A8D1 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 80017628 at 80017620 badvaddr 8002A8D1 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80017648 at 80017640 badvaddr 8002A8D1 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 80017694 at 80017694 badvaddr 8002A8D1 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800176F8 at 800176F0 badvaddr 8002A8D1 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 80017210 at 80017210 badvaddr 8002A8D1 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 80017218 at 80017218 badvaddr 8002A8D1 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 80017636 at 80017636 badvaddr 80017636 reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 80017636 reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: 00010002, four later 00030004
mtc2, 1 nop, mfc2: 00010002, four later 00030004
mtc2, 2 nops, mfc2: 00030004, four later 00030004
mtc2, 3 nops, mfc2: 00030004, four later 00030004
lwc2 then mfc2 at once: 00010002, four later 00030004
lwc2, 1 nop, mfc2: 00010002, four later 00030004
lwc2, 2 nops, mfc2: 00030004, four later 00030004
lwc2, 3 nops, mfc2: 00030004, four later 00030004
ctc2 then cfc2 at once: 00010002, four later 00030004
ctc2, 1 nop, cfc2: 00010002, four later 00030004
ctc2, 2 nops, cfc2: 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: 00000004, four later 00000010
mtc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: 00000010, four later 00000100
lwc2 IR1 then SQR at once: 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: 00000004, four later 00000010
mtc2 then swc2 at once: 00010002, four later 00030004
mtc2, 1 nop, swc2: 00030004, four later 00030004
mtc2, 2 nops, swc2: 00030004, four later 00030004
mtc2 IR1, lw, SQR: 00000004, four later 00000010
mtc2 IR1, mtc2 VXY0, SQR: 00000004, four later 00000010
lwc2 IR1, lwc2 VXY0, SQR: 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: 00000004, four later 00000004
ctc2 TRZ then RTPT at once: 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): 00000010, four later 00000100
mtc2 IR3, 1 nop, SQR (MAC3): 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): 00000040, four later 00000040
lwc2 RGBC then NCCS at once: 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: 00000004, four later 00000004
mtc2 VZ0 then MVMVA at once (MAC3): 00000004, four later 00000004
lwc2 VZ0 then MVMVA at once: 00000004, four later 00000004
mtc2 IR1 then INTPL at once (MAC1): 00000002, four later 00000004
mtc2 IR3 then INTPL at once (MAC3): 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC1 = VX0): 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC2 = VY0): 00000003, four later 00000003
ctc2 TRX then RTPS at once (MAC1 = TRX + VX0): 00030008, four later 00030008
mtc2 VZ0 then RTPT at once (SZ1): 00000004, four later 00000004
lwc2 VZ0 then RTPT at once (SZ1): 00000004, four later 00000004
mtc2 VZ1 then RTPT at once (SZ2): 00000004, four later 00000004
mtc2 LZCS then mfc2 LZCR at once: 0000000F, four later 0000000E
mtc2 LZCS, 1 nop, mfc2 LZCR: 0000000F, four later 0000000E
mtc2 LZCS, 2 nops, mfc2 LZCR: 0000000E, four later 0000000E
mtc2 IRGB then mfc2 IR1 at once: 00000100, four later 00000200
mtc2 IRGB, 1 nop, mfc2 IR1: 00000100, four later 00000200
mtc2 IRGB, 2 nops, mfc2 IR1: 00000200, four later 00000200
mtc2 SXYP then mfc2 SXY2 at once: 00010002, four later 00030004
mtc2 SXYP, 1 nop, mfc2 SXY2: 00010002, four later 00030004
mtc2 SXYP, 2 nops, mfc2 SXY2: 00030004, four later 00030004
cold then cached, pad 0-3 after a line start:
mtc2, 1 nop, mfc2, pad 0: 00010002 then 00010002
mtc2, 1 nop, mfc2, pad 1: 00010002 then 00010002
mtc2, 1 nop, mfc2, pad 2: 00010002 then 00010002
mtc2, 1 nop, mfc2, pad 3: 00030004 then 00010002
lwc2, 1 nop, mfc2, pad 0: 00010002 then 00010002
lwc2, 1 nop, mfc2, pad 1: 00010002 then 00010002
lwc2, 1 nop, mfc2, pad 2: 00010002 then 00010002
lwc2, 1 nop, mfc2, pad 3: 00030004 then 00010002
lwc2 IR1, 1 nop, SQR, pad 0: 00000004 then 00000004
lwc2 IR1, 1 nop, SQR, pad 1: 00000004 then 00000004
lwc2 IR1, 1 nop, SQR, pad 2: 00000004 then 00000004
lwc2 IR1, 1 nop, SQR, pad 3: 00000010 then 00000004
lwc2, 2 nops, mfc2, pad 0: 00030004 then 00030004
lwc2, 2 nops, mfc2, pad 1: 00030004 then 00030004
lwc2, 2 nops, mfc2, pad 2: 00030004 then 00030004
lwc2, 2 nops, mfc2, pad 3: 00030004 then 00030004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 558 cycles for 100
nop, 20 nops 00000000 00000000: 2582 cycles for 100
mult 00000000 00000003: 1154 cycles for 100
multu 00000000 00000003: 1154 cycles for 100
mult rt 00000003 00000000: 1154 cycles for 100
mult 00000001 00000003: 1157 cycles for 100
multu 00000001 00000003: 1153 cycles for 100
mult rt 00000003 00000001: 1153 cycles for 100
mult 000007FF 00000003: 1153 cycles for 100
multu 000007FF 00000003: 1153 cycles for 100
mult rt 00000003 000007FF: 1153 cycles for 100
mult 00000800 00000003: 1453 cycles for 100
multu 00000800 00000003: 1453 cycles for 100
mult rt 00000003 00000800: 1153 cycles for 100
mult 000FFFFF 00000003: 1453 cycles for 100
multu 000FFFFF 00000003: 1453 cycles for 100
mult rt 00000003 000FFFFF: 1153 cycles for 100
mult 00100000 00000003: 1853 cycles for 100
multu 00100000 00000003: 1853 cycles for 100
mult rt 00000003 00100000: 1153 cycles for 100
mult 7FFFFFFF 00000003: 1853 cycles for 100
multu 7FFFFFFF 00000003: 1856 cycles for 100
mult rt 00000003 7FFFFFFF: 1153 cycles for 100
mult FFFFFFFF 00000003: 1153 cycles for 100
multu FFFFFFFF 00000003: 1853 cycles for 100
mult rt 00000003 FFFFFFFF: 1153 cycles for 100
mult 80000000 00000003: 1853 cycles for 100
multu 80000000 00000003: 1853 cycles for 100
mult rt 00000003 80000000: 1154 cycles for 100
div 12345678 00000003: 4154 cycles for 100
divu 12345678 00000003: 4153 cycles for 100
div by 0 12345678 00000000: 4157 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2578 cycles for 100
div, 20 nops 12345678 00000003: 4162 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1859 cycles for 100
mult, 1 nops, mflo: 1854 cycles for 100
mult, 2 nops, mflo: 1854 cycles for 100
mult, 3 nops, mflo: 1849 cycles for 100
mult, 4 nops, mflo: 1847 cycles for 100
mult, 5 nops, mflo: 1852 cycles for 100
mult, 6 nops, mflo: 1853 cycles for 100
mult, 7 nops, mflo: 1857 cycles for 100
mult, 8 nops, mflo: 1852 cycles for 100
mult, 9 nops, mflo: 1854 cycles for 100
mult, 10 nops, mflo: 1862 cycles for 100
mult, 11 nops, mflo: 1856 cycles for 100
mult, 12 nops, mflo: 1762 cycles for 100
mult, 13 nops, mflo: 1875 cycles for 100
mult, 14 nops, mflo: 1970 cycles for 100
div, 5 nops, mflo: 4153 cycles for 100
div, 10 nops, mflo: 4147 cycles for 100
div, 30 nops, mflo: 4176 cycles for 100
div, 33 nops, mflo: 4192 cycles for 100
div, 34 nops, mflo: 4187 cycles for 100
div, 35 nops, mflo: 4092 cycles for 100
div, 36 nops, mflo: 4198 cycles for 100
div, 37 nops, mflo: 4293 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1848 cycles for 100
mult, no read: 457 cycles for 100
div, no read: 450 cycles for 100
mult then mtlo: 551 cycles for 100
mult then mthi: 551 cycles for 100
mult then mult then mflo: 1948 cycles for 100
mult then mtlo then mflo: 648 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 8002CE28 lw: 969 cycles for 100
RAM KSEG1 A002CE28 lw: 948 cycles for 100
scratchpad 1F800100 lw: 533 cycles for 100
BIOS BFC00100 lw: 2936 cycles for 100
BIOS BFC00100 lh: 1748 cycles for 100
BIOS BFC00100 lb: 1143 cycles for 100
EXP1 1F000084 lb: 1124 cycles for 100
EXP2 1F802000 lb: 1528 cycles for 100
EXP3 1FA00000 lh: 1030 cycles for 100
EXP3 1FA00000 lb: 1024 cycles for 100
I_STAT 1F801070 lw: 752 cycles for 100
DPCR 1F8010F0 lw: 736 cycles for 100
timer 0 1F801100 lw: 736 cycles for 100
JOY_STAT 1F801044 lh: 727 cycles for 100
CDROM status 1F801800 lb: 1224 cycles for 100
GPUSTAT 1F801814 lw: 733 cycles for 100
MDEC status 1F801824 lw: 733 cycles for 100
SPUSTAT 1F801DAE lh: 2224 cycles for 100
SPU word 1F801DAC lw: 4230 cycles for 100
cache control FFFE0130 lw: 533 cycles for 100
RAM lw, used at once: 955 cycles for 100
RAM lw, used after 1 nop: 1267 cycles for 100
RAM lw, used after 2 nops: 1360 cycles for 100
RAM lw, used after 3 nops: 1372 cycles for 100
RAM lw then lw: 1470 cycles for 100
BIOS lw, used at once: 2931 cycles for 100
BIOS lw, used after 3 nops: 3327 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 460 cycles for 100
RAM, 2 sw: 579 cycles for 100
RAM, 3 sw: 687 cycles for 100
RAM, 4 sw: 905 cycles for 100
RAM, 5 sw: 1108 cycles for 100
RAM, 6 sw: 1333 cycles for 100
RAM, 7 sw: 1536 cycles for 100
RAM, 8 sw: 1746 cycles for 100
RAM, 4 sw then lw: 2115 cycles for 100
RAM, sw then lw: 1477 cycles for 100
scratchpad, 1 sw: 456 cycles for 100
scratchpad, 8 sw: 1163 cycles for 100
I_MASK, 1 sw: 447 cycles for 100
I_MASK, 4 sw: 855 cycles for 100
I_MASK, sw then lw: 849 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1480 cycles for 100
RAM sw, 2 nops, lw: 1474 cycles for 100
RAM sw, 3 nops, lw: 1474 cycles for 100
RAM sw, 4 nops, lw: 1483 cycles for 100
RAM sw, 6 nops, lw: 1570 cycles for 100
RAM sw, lw of another word: 1467 cycles for 100
RAM 4 sw, lw of another word: 2114 cycles for 100
chain-looping's loop: 1666 cycles for 100
RAM lw, used after 4 nops: 1367 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 746 cycles for 100
I_STAT lw, used after 1 nop: 1053 cycles for 100
I_STAT lw, used after 2 nops: 1149 cycles for 100
I_STAT lw then lw: 1154 cycles for 100
BIOS lw, used after 1 nop: 3240 cycles for 100
BIOS lw, used after 2 nops: 3327 cycles for 100
BIOS lw then lw: 5433 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 447 cycles for 100
GP0 NOP, 4 sw: 851 cycles for 100
CDROM index, 1 sb: 637 cycles for 100
CDROM index, 4 sb: 2433 cycles for 100
SPU main volume, 1 sh: 828 cycles for 100
SPU main volume, 4 sh: 3212 cycles for 100
scratchpad, 4 sw: 753 cycles for 100
RAM, 1 sh: 459 cycles for 100
RAM, 4 sh: 895 cycles for 100
RAM, 4 sb: 902 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1493 cycles for 100
RAM sw, 7 nops, lw: 1666 cycles for 100
RAM sw, 8 nops, lw: 1786 cycles for 100
RAM 5 nops, lw (no store): 1262 cycles for 100
RAM 7 nops, lw (no store): 1460 cycles for 100
RAM 9 nops, lw (no store): 1670 cycles for 100
chain-looping's loop, the sw a nop: 1465 cycles for 100
I_STAT lw, used after 3 nops: 1149 cycles for 100
I_STAT lw, used after 4 nops: 1155 cycles for 100
SPU word lw then lw: 8254 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 655 cycles for 100
mult, mthi, mflo: 652 cycles for 100
mult, mtlo, mfhi: 654 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3110 cycles for 100
nop, 20 nops loop: 15302 cycles for 100
RAM lw loop: 3519 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 27BD0B88
cache control FFFE0130: 0001E988
RAM word at 0002CB78 holds C0FFEE01
KUSEG 0002CB78: C0FFEE01
KUSEG +2MB 0022CB78: C0FFEE01
KUSEG +4MB 0042CB78: C0FFEE01
KUSEG +6MB 0062CB78: C0FFEE01
KSEG0 +2MB 8022CB78: C0FFEE01
KSEG1 A002CB78: C0FFEE01
KSEG1 +6MB A062CB78: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 0C000009, 1 before the fill: 00000B88
I_MASK store 0C000009, 2 before the fill: 00000B88
I_MASK store 0C000009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 0C000009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 8002F1A0
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/instruction cache (code at 8002F2B0)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 1
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 2
loop from KSEG0: 325 then 304 cycles
loop from KSEG1: 1855 then 1848 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/bus writes
sw 7FFAF614: exception 7, reg 12345678, badvaddr 80017636 to 80017636
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 80017636 to 80017636
sw 20000000: exception 7, reg 12345678, badvaddr 80017636 to 80017636
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 80017636 to 80017636
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001DB10 at 8001DB10 badvaddr 80017636 reg 00000000
syscall 0: none, at 8001DB28, reg 00000000
syscall 4: none, at 8001DB28, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 80017636
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001D8F8, the load at 8001D8F8, value read 00000002
Done.
Output files that match an earlier run: 01BUK.txt (as run 20260926T0000Z-5501a-card-cpu-3).
26 September 2026 (card-cpu-6)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02B68 DCIC 00000000 BadVaddr 02000590 BDAM 00000000
BPCM 00000000 SR 00000000 Cause C0000024 EPC BFC02B78 PRId 00000002
===== 01 BUK CPU BUS KUSEG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 02000590
cpu/bus kuseg past 512MB
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lhu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lbu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lhu 20000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lbu 20000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lw 40000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lhu 40000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lbu 40000000: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lw 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lhu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
lbu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 02000590 to 02000590
Done.
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 02000590
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 800174F0 at 800174F0 badvaddr 8002A839 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80017528 at 80017528 badvaddr 8002A83A reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 8001750C at 8001750C badvaddr 8002A839 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80017544 at 80017544 badvaddr 8002A839 reg 44332211
sh +1: n 1 code 5 bd 0 epc 80017558 at 80017558 badvaddr 8002A839 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80017570 at 80017570 badvaddr 8002A839 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 80017588 at 80017588 badvaddr 8002A839 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 800175A0 at 800175A0 badvaddr 8002A839 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 800175B0 at 800175B0 badvaddr 8002A839 reg 00000000
special 01h: n 1 code 10 bd 0 epc 800175C0 at 800175C0 badvaddr 8002A839 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 800175E0 at 800175D8 badvaddr 8002A839 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80017608 at 800175F8 badvaddr 8002A839 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 8001764C at 8001764C badvaddr 8002A839 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800176B8 at 800176A8 badvaddr 8002A839 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 800171C8 at 800171C8 badvaddr 8002A839 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 800171D0 at 800171D0 badvaddr 8002A839 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 800175EE at 800175EE badvaddr 800175EE reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 800175EE reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
mtc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
mtc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
lwc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
lwc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
ctc2 then cfc2 at once: cold 00010002, cached 00010002, four later 00030004
ctc2, 1 nop, cfc2: cold 00010002, cached 00010002, four later 00030004
ctc2, 2 nops, cfc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1 then SQR at once: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 then swc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, swc2: cold 00030004, cached 00010002, four later 00030004
mtc2, 2 nops, swc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1, lw, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, mtc2 VXY0, SQR: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, lwc2 VXY0, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: cold 00000004, cached 00000004, four later 00000004
ctc2 TRZ then RTPT at once: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: cold 00030008, cached 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): cold 00000004, cached 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 IR3, 1 nop, SQR (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): cold 00000040, cached 00000040, four later 00000040
lwc2 RGBC then NCCS at once: cold 00000040, cached 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: cold 00000040, cached 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: cold 00000004, cached 00000004, four later 00000004
mtc2 VZ0 then MVMVA at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then MVMVA at once: cold 00000004, cached 00000004, four later 00000004
mtc2 IR1 then INTPL at once (MAC1): cold 00000002, cached 00000002, four later 00000002
mtc2 IR3 then INTPL at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC1 = VX0): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC2 = VY0): cold 00000003, cached 00000003, four later 00000003
ctc2 TRX then RTPS at once (MAC1 = TRX + VX0): cold 00030008, cached 00030008, four later 00030008
mtc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ1 then RTPT at once (SZ2): cold 00000004, cached 00000004, four later 00000004
mtc2 LZCS then mfc2 LZCR at once: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 1 nop, mfc2 LZCR: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 2 nops, mfc2 LZCR: cold 0000000E, cached 0000000E, four later 0000000E
mtc2 IRGB then mfc2 IR1 at once: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 1 nop, mfc2 IR1: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 2 nops, mfc2 IR1: cold 00000200, cached 00000100, four later 00000200
mtc2 SXYP then mfc2 SXY2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 1 nop, mfc2 SXY2: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 2 nops, mfc2 SXY2: cold 00030004, cached 00030004, four later 00030004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 545 cycles for 100
nop, 20 nops 00000000 00000000: 2570 cycles for 100
mult 00000000 00000003: 1145 cycles for 100
multu 00000000 00000003: 1145 cycles for 100
mult rt 00000003 00000000: 1145 cycles for 100
mult 00000001 00000003: 1145 cycles for 100
multu 00000001 00000003: 1145 cycles for 100
mult rt 00000003 00000001: 1145 cycles for 100
mult 000007FF 00000003: 1145 cycles for 100
multu 000007FF 00000003: 1149 cycles for 100
mult rt 00000003 000007FF: 1145 cycles for 100
mult 00000800 00000003: 1445 cycles for 100
multu 00000800 00000003: 1450 cycles for 100
mult rt 00000003 00000800: 1145 cycles for 100
mult 000FFFFF 00000003: 1445 cycles for 100
multu 000FFFFF 00000003: 1445 cycles for 100
mult rt 00000003 000FFFFF: 1149 cycles for 100
mult 00100000 00000003: 1845 cycles for 100
multu 00100000 00000003: 1845 cycles for 100
mult rt 00000003 00100000: 1145 cycles for 100
mult 7FFFFFFF 00000003: 1845 cycles for 100
multu 7FFFFFFF 00000003: 1845 cycles for 100
mult rt 00000003 7FFFFFFF: 1145 cycles for 100
mult FFFFFFFF 00000003: 1145 cycles for 100
multu FFFFFFFF 00000003: 1848 cycles for 100
mult rt 00000003 FFFFFFFF: 1145 cycles for 100
mult 80000000 00000003: 1845 cycles for 100
multu 80000000 00000003: 1845 cycles for 100
mult rt 00000003 80000000: 1145 cycles for 100
div 12345678 00000003: 4145 cycles for 100
divu 12345678 00000003: 4150 cycles for 100
div by 0 12345678 00000000: 4145 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2570 cycles for 100
div, 20 nops 12345678 00000003: 4159 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1845 cycles for 100
mult, 1 nops, mflo: 1846 cycles for 100
mult, 2 nops, mflo: 1848 cycles for 100
mult, 3 nops, mflo: 1854 cycles for 100
mult, 4 nops, mflo: 1851 cycles for 100
mult, 5 nops, mflo: 1852 cycles for 100
mult, 6 nops, mflo: 1857 cycles for 100
mult, 7 nops, mflo: 1856 cycles for 100
mult, 8 nops, mflo: 1856 cycles for 100
mult, 9 nops, mflo: 1859 cycles for 100
mult, 10 nops, mflo: 1854 cycles for 100
mult, 11 nops, mflo: 1858 cycles for 100
mult, 12 nops, mflo: 1771 cycles for 100
mult, 13 nops, mflo: 1867 cycles for 100
mult, 14 nops, mflo: 1974 cycles for 100
div, 5 nops, mflo: 4147 cycles for 100
div, 10 nops, mflo: 4151 cycles for 100
div, 30 nops, mflo: 4179 cycles for 100
div, 33 nops, mflo: 4188 cycles for 100
div, 34 nops, mflo: 4191 cycles for 100
div, 35 nops, mflo: 4086 cycles for 100
div, 36 nops, mflo: 4194 cycles for 100
div, 37 nops, mflo: 4298 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1842 cycles for 100
mult, no read: 441 cycles for 100
div, no read: 451 cycles for 100
mult then mtlo: 552 cycles for 100
mult then mthi: 552 cycles for 100
mult then mult then mflo: 1945 cycles for 100
mult then mtlo then mflo: 653 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 8002CD90 lw: 967 cycles for 100
RAM KSEG1 A002CD90 lw: 943 cycles for 100
scratchpad 1F800100 lw: 531 cycles for 100
BIOS BFC00100 lw: 2926 cycles for 100
BIOS BFC00100 lh: 1745 cycles for 100
BIOS BFC00100 lb: 1145 cycles for 100
EXP1 1F000084 lb: 1120 cycles for 100
EXP2 1F802000 lb: 1520 cycles for 100
EXP3 1FA00000 lh: 1041 cycles for 100
EXP3 1FA00000 lb: 1045 cycles for 100
I_STAT 1F801070 lw: 748 cycles for 100
DPCR 1F8010F0 lw: 731 cycles for 100
timer 0 1F801100 lw: 731 cycles for 100
JOY_STAT 1F801044 lh: 725 cycles for 100
CDROM status 1F801800 lb: 1220 cycles for 100
GPUSTAT 1F801814 lw: 731 cycles for 100
MDEC status 1F801824 lw: 731 cycles for 100
SPUSTAT 1F801DAE lh: 2220 cycles for 100
SPU word 1F801DAC lw: 4226 cycles for 100
cache control FFFE0130 lw: 531 cycles for 100
RAM lw, used at once: 961 cycles for 100
RAM lw, used after 1 nop: 1269 cycles for 100
RAM lw, used after 2 nops: 1356 cycles for 100
RAM lw, used after 3 nops: 1358 cycles for 100
RAM lw then lw: 1462 cycles for 100
BIOS lw, used at once: 2937 cycles for 100
BIOS lw, used after 3 nops: 3325 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 454 cycles for 100
RAM, 2 sw: 570 cycles for 100
RAM, 3 sw: 693 cycles for 100
RAM, 4 sw: 893 cycles for 100
RAM, 5 sw: 1114 cycles for 100
RAM, 6 sw: 1327 cycles for 100
RAM, 7 sw: 1523 cycles for 100
RAM, 8 sw: 1747 cycles for 100
RAM, 4 sw then lw: 2120 cycles for 100
RAM, sw then lw: 1479 cycles for 100
scratchpad, 1 sw: 446 cycles for 100
scratchpad, 8 sw: 1156 cycles for 100
I_MASK, 1 sw: 447 cycles for 100
I_MASK, 4 sw: 851 cycles for 100
I_MASK, sw then lw: 852 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1485 cycles for 100
RAM sw, 2 nops, lw: 1492 cycles for 100
RAM sw, 3 nops, lw: 1487 cycles for 100
RAM sw, 4 nops, lw: 1483 cycles for 100
RAM sw, 6 nops, lw: 1579 cycles for 100
RAM sw, lw of another word: 1474 cycles for 100
RAM 4 sw, lw of another word: 2115 cycles for 100
chain-looping's loop: 1649 cycles for 100
RAM lw, used after 4 nops: 1364 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 755 cycles for 100
I_STAT lw, used after 1 nop: 1039 cycles for 100
I_STAT lw, used after 2 nops: 1147 cycles for 100
I_STAT lw then lw: 1150 cycles for 100
BIOS lw, used after 1 nop: 3239 cycles for 100
BIOS lw, used after 2 nops: 3325 cycles for 100
BIOS lw then lw: 5423 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 447 cycles for 100
GP0 NOP, 4 sw: 851 cycles for 100
CDROM index, 1 sb: 626 cycles for 100
CDROM index, 4 sb: 2433 cycles for 100
SPU main volume, 1 sh: 806 cycles for 100
SPU main volume, 4 sh: 3220 cycles for 100
scratchpad, 4 sw: 753 cycles for 100
RAM, 1 sh: 436 cycles for 100
RAM, 4 sh: 892 cycles for 100
RAM, 4 sb: 872 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1489 cycles for 100
RAM sw, 7 nops, lw: 1658 cycles for 100
RAM sw, 8 nops, lw: 1785 cycles for 100
RAM 5 nops, lw (no store): 1254 cycles for 100
RAM 7 nops, lw (no store): 1468 cycles for 100
RAM 9 nops, lw (no store): 1667 cycles for 100
chain-looping's loop, the sw a nop: 1480 cycles for 100
I_STAT lw, used after 3 nops: 1154 cycles for 100
I_STAT lw, used after 4 nops: 1144 cycles for 100
SPU word lw then lw: 8247 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 653 cycles for 100
mult, mthi, mflo: 651 cycles for 100
mult, mtlo, mfhi: 653 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3110 cycles for 100
nop, 20 nops loop: 15300 cycles for 100
RAM lw loop: 3523 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 03E00B88
cache control FFFE0130: 0001E988
RAM word at 0002CAE0 holds C0FFEE01
KUSEG 0002CAE0: C0FFEE01
KUSEG +2MB 0022CAE0: C0FFEE01
KUSEG +4MB 0042CAE0: C0FFEE01
KUSEG +6MB 0062CAE0: C0FFEE01
KSEG0 +2MB 8022CAE0: C0FFEE01
KSEG1 A002CAE0: C0FFEE01
KSEG1 +6MB A062CAE0: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 0C000009, 1 before the fill: 00000B88
I_MASK store 0C000009, 2 before the fill: 00000B88
I_MASK store 0C000009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 0C000009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 8002F170
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/instruction cache (code at 8002F280)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 1
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 2
loop from KSEG0: 323 then 304 cycles
loop from KSEG1: 1853 then 1848 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/bus writes
sw 7FFAF614: exception 7, reg 00002000, badvaddr 8002F3E0 to 800175EE
none, reg 12345678, badvaddr 800175EE to 800175EE
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 800175EE to 800175EE
sw 20000000: exception 7, reg 00002000, badvaddr 8002F3E0 to 800175EE
none, reg 12345678, badvaddr 800175EE to 800175EE
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 800175EE to 800175EE
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001DA78 at 8001DA78 badvaddr 800175EE reg 00000000
syscall 0: none, at 8001DA90, reg 00000000
syscall 4: none, at 8001DA90, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800175EE
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001D860, the load at 8001D860, value read 00000002
Done.
27 September 2026 (card-1)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000400 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010DC50 PRId 00000002
===== 01 BUK CPU BUS KUSEG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
cpu/bus kuseg past 512MB
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lhu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lbu 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lhu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lbu 20000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lw 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lhu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lbu 40000000: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lw 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lhu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
lbu 7FFFFFFC: exception 7, reg 5A5A5A5A, badvaddr 00000400 to 00000400
Done.
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 8001544C at 8001544C badvaddr 80023835 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80015484 at 80015484 badvaddr 80023836 reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 80015468 at 80015468 badvaddr 80023835 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 800154A0 at 800154A0 badvaddr 80023835 reg 44332211
sh +1: n 1 code 5 bd 0 epc 800154B4 at 800154B4 badvaddr 80023835 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 800154CC at 800154CC badvaddr 80023835 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 800154E4 at 800154E4 badvaddr 80023835 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 800154FC at 800154FC badvaddr 80023835 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 8001550C at 8001550C badvaddr 80023835 reg 00000000
special 01h: n 1 code 10 bd 0 epc 8001551C at 8001551C badvaddr 80023835 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 80015538 at 80015534 badvaddr 80023835 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80015558 at 80015554 badvaddr 80023835 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 800155A8 at 800155A8 badvaddr 80023835 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80015608 at 80015604 badvaddr 80023835 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 80015124 at 80015124 badvaddr 80023835 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 8001512C at 8001512C badvaddr 80023835 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 8001554A at 8001554A badvaddr 8001554A reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 8001554A reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 40000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 7FFF8000 7FFF8000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, mfc2: cold 00030004, cached 00010002, four later 00030004
mtc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
mtc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
lwc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
lwc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
ctc2 then cfc2 at once: cold 00010002, cached 00010002, four later 00030004
ctc2, 1 nop, cfc2: cold 00030004, cached 00010002, four later 00030004
ctc2, 2 nops, cfc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: cold 00000010, cached 00000004, four later 00000010
mtc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1 then SQR at once: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 then swc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, swc2: cold 00010002, cached 00010002, four later 00030004
mtc2, 2 nops, swc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1, lw, SQR: cold 00000010, cached 00000004, four later 00000010
mtc2 IR1, mtc2 VXY0, SQR: cold 00000010, cached 00000004, four later 00000010
lwc2 IR1, lwc2 VXY0, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: cold 00000004, cached 00000004, four later 00000004
ctc2 TRZ then RTPT at once: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: cold 00030008, cached 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): cold 00000004, cached 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 IR3, 1 nop, SQR (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): cold 00000040, cached 00000040, four later 00000040
lwc2 RGBC then NCCS at once: cold 00000040, cached 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: cold 00000040, cached 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: cold 00000004, cached 00000004, four later 00000004
mtc2 VZ0 then MVMVA at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then MVMVA at once: cold 00000004, cached 00000004, four later 00000004
mtc2 IR1 then INTPL at once (MAC1): cold 00000002, cached 00000002, four later 00000002
mtc2 IR3 then INTPL at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC1 = VX0): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC2 = VY0): cold 00000003, cached 00000003, four later 00000003
ctc2 TRX then RTPS at once (MAC1 = TRX + VX0): cold 00030008, cached 00030008, four later 00030008
mtc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ1 then RTPT at once (SZ2): cold 00000004, cached 00000004, four later 00000004
mtc2 LZCS then mfc2 LZCR at once: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 1 nop, mfc2 LZCR: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 2 nops, mfc2 LZCR: cold 0000000E, cached 0000000E, four later 0000000E
mtc2 IRGB then mfc2 IR1 at once: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 1 nop, mfc2 IR1: cold 00000200, cached 00000100, four later 00000200
mtc2 IRGB, 2 nops, mfc2 IR1: cold 00000100, cached 00000100, four later 00000200
mtc2 SXYP then mfc2 SXY2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 1 nop, mfc2 SXY2: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 2 nops, mfc2 SXY2: cold 00030004, cached 00030004, four later 00030004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 553 cycles for 100
nop, 20 nops 00000000 00000000: 2573 cycles for 100
mult 00000000 00000003: 1151 cycles for 100
multu 00000000 00000003: 1148 cycles for 100
mult rt 00000003 00000000: 1151 cycles for 100
mult 00000001 00000003: 1148 cycles for 100
multu 00000001 00000003: 1148 cycles for 100
mult rt 00000003 00000001: 1148 cycles for 100
mult 000007FF 00000003: 1151 cycles for 100
multu 000007FF 00000003: 1150 cycles for 100
mult rt 00000003 000007FF: 1151 cycles for 100
mult 00000800 00000003: 1448 cycles for 100
multu 00000800 00000003: 1451 cycles for 100
mult rt 00000003 00000800: 1151 cycles for 100
mult 000FFFFF 00000003: 1448 cycles for 100
multu 000FFFFF 00000003: 1448 cycles for 100
mult rt 00000003 000FFFFF: 1148 cycles for 100
mult 00100000 00000003: 1848 cycles for 100
multu 00100000 00000003: 1848 cycles for 100
mult rt 00000003 00100000: 1148 cycles for 100
mult 7FFFFFFF 00000003: 1848 cycles for 100
multu 7FFFFFFF 00000003: 1848 cycles for 100
mult rt 00000003 7FFFFFFF: 1148 cycles for 100
mult FFFFFFFF 00000003: 1148 cycles for 100
multu FFFFFFFF 00000003: 1851 cycles for 100
mult rt 00000003 FFFFFFFF: 1151 cycles for 100
mult 80000000 00000003: 1848 cycles for 100
multu 80000000 00000003: 1848 cycles for 100
mult rt 00000003 80000000: 1151 cycles for 100
div 12345678 00000003: 4148 cycles for 100
divu 12345678 00000003: 4148 cycles for 100
div by 0 12345678 00000000: 4148 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2573 cycles for 100
div, 20 nops 12345678 00000003: 4157 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1848 cycles for 100
mult, 1 nops, mflo: 1847 cycles for 100
mult, 2 nops, mflo: 1846 cycles for 100
mult, 3 nops, mflo: 1843 cycles for 100
mult, 4 nops, mflo: 1847 cycles for 100
mult, 5 nops, mflo: 1849 cycles for 100
mult, 6 nops, mflo: 1847 cycles for 100
mult, 7 nops, mflo: 1846 cycles for 100
mult, 8 nops, mflo: 1853 cycles for 100
mult, 9 nops, mflo: 1853 cycles for 100
mult, 10 nops, mflo: 1853 cycles for 100
mult, 11 nops, mflo: 1863 cycles for 100
mult, 12 nops, mflo: 1761 cycles for 100
mult, 13 nops, mflo: 1863 cycles for 100
mult, 14 nops, mflo: 1967 cycles for 100
div, 5 nops, mflo: 4142 cycles for 100
div, 10 nops, mflo: 4144 cycles for 100
div, 30 nops, mflo: 4190 cycles for 100
div, 33 nops, mflo: 4180 cycles for 100
div, 34 nops, mflo: 4180 cycles for 100
div, 35 nops, mflo: 4091 cycles for 100
div, 36 nops, mflo: 4192 cycles for 100
div, 37 nops, mflo: 4287 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1841 cycles for 100
mult, no read: 442 cycles for 100
div, no read: 442 cycles for 100
mult then mtlo: 542 cycles for 100
mult then mthi: 542 cycles for 100
mult then mult then mflo: 1948 cycles for 100
mult then mtlo then mflo: 642 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 80025ADC lw: 955 cycles for 100
RAM KSEG1 A0025ADC lw: 946 cycles for 100
scratchpad 1F800100 lw: 541 cycles for 100
BIOS BFC00100 lw: 2937 cycles for 100
BIOS BFC00100 lh: 1737 cycles for 100
BIOS BFC00100 lb: 1143 cycles for 100
EXP1 1F000084 lb: 1119 cycles for 100
EXP2 1F802000 lb: 1519 cycles for 100
EXP3 1FA00000 lh: 1025 cycles for 100
EXP3 1FA00000 lb: 1037 cycles for 100
I_STAT 1F801070 lw: 740 cycles for 100
DPCR 1F8010F0 lw: 740 cycles for 100
timer 0 1F801100 lw: 740 cycles for 100
JOY_STAT 1F801044 lh: 733 cycles for 100
CDROM status 1F801800 lb: 1219 cycles for 100
GPUSTAT 1F801814 lw: 740 cycles for 100
MDEC status 1F801824 lw: 740 cycles for 100
SPUSTAT 1F801DAE lh: 2225 cycles for 100
SPU word 1F801DAC lw: 4237 cycles for 100
cache control FFFE0130 lw: 541 cycles for 100
RAM lw, used at once: 956 cycles for 100
RAM lw, used after 1 nop: 1260 cycles for 100
RAM lw, used after 2 nops: 1363 cycles for 100
RAM lw, used after 3 nops: 1363 cycles for 100
RAM lw then lw: 1472 cycles for 100
BIOS lw, used at once: 2922 cycles for 100
BIOS lw, used after 3 nops: 3327 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 453 cycles for 100
RAM, 2 sw: 571 cycles for 100
RAM, 3 sw: 686 cycles for 100
RAM, 4 sw: 901 cycles for 100
RAM, 5 sw: 1098 cycles for 100
RAM, 6 sw: 1310 cycles for 100
RAM, 7 sw: 1529 cycles for 100
RAM, 8 sw: 1740 cycles for 100
RAM, 4 sw then lw: 2105 cycles for 100
RAM, sw then lw: 1474 cycles for 100
scratchpad, 1 sw: 447 cycles for 100
scratchpad, 8 sw: 1154 cycles for 100
I_MASK, 1 sw: 422 cycles for 100
I_MASK, 4 sw: 854 cycles for 100
I_MASK, sw then lw: 847 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1472 cycles for 100
RAM sw, 2 nops, lw: 1488 cycles for 100
RAM sw, 3 nops, lw: 1483 cycles for 100
RAM sw, 4 nops, lw: 1495 cycles for 100
RAM sw, 6 nops, lw: 1575 cycles for 100
RAM sw, lw of another word: 1467 cycles for 100
RAM 4 sw, lw of another word: 2109 cycles for 100
chain-looping's loop: 1648 cycles for 100
RAM lw, used after 4 nops: 1361 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 734 cycles for 100
I_STAT lw, used after 1 nop: 1043 cycles for 100
I_STAT lw, used after 2 nops: 1151 cycles for 100
I_STAT lw then lw: 1147 cycles for 100
BIOS lw, used after 1 nop: 3222 cycles for 100
BIOS lw, used after 2 nops: 3344 cycles for 100
BIOS lw then lw: 5423 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 422 cycles for 100
GP0 NOP, 4 sw: 820 cycles for 100
CDROM index, 1 sb: 625 cycles for 100
CDROM index, 4 sb: 2420 cycles for 100
SPU main volume, 1 sh: 803 cycles for 100
SPU main volume, 4 sh: 3220 cycles for 100
scratchpad, 4 sw: 755 cycles for 100
RAM, 1 sh: 450 cycles for 100
RAM, 4 sh: 860 cycles for 100
RAM, 4 sb: 896 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1486 cycles for 100
RAM sw, 7 nops, lw: 1665 cycles for 100
RAM sw, 8 nops, lw: 1765 cycles for 100
RAM 5 nops, lw (no store): 1254 cycles for 100
RAM 7 nops, lw (no store): 1456 cycles for 100
RAM 9 nops, lw (no store): 1664 cycles for 100
chain-looping's loop, the sw a nop: 1476 cycles for 100
I_STAT lw, used after 3 nops: 1145 cycles for 100
I_STAT lw, used after 4 nops: 1151 cycles for 100
SPU word lw then lw: 8247 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 643 cycles for 100
mult, mthi, mflo: 643 cycles for 100
mult, mtlo, mfhi: 647 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3110 cycles for 100
nop, 20 nops loop: 15298 cycles for 100
RAM lw loop: 3520 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 00000B88
cache control FFFE0130: 0001E988
RAM word at 000258E8 holds C0FFEE01
KUSEG 000258E8: C0FFEE01
KUSEG +2MB 002258E8: C0FFEE01
KUSEG +4MB 004258E8: C0FFEE01
KUSEG +6MB 006258E8: C0FFEE01
KSEG0 +2MB 802258E8: C0FFEE01
KSEG1 A00258E8: C0FFEE01
KSEG1 +6MB A06258E8: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 00400009, 1 before the fill: 00000B88
I_MASK store 00400009, 2 before the fill: 00000B88
I_MASK store 00400009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 00400009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 80026D40
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/instruction cache (code at 80026E50)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 1
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 2
loop from KSEG0: 319 then 306 cycles
loop from KSEG1: 1854 then 1851 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/bus writes
sw 7FFAF614: exception 7, reg 12345678, badvaddr 8001554A to 8001554A
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 8001554A to 8001554A
sw 20000000: exception 7, reg 12345678, badvaddr 8001554A to 8001554A
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 8001554A to 8001554A
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001B9D4 at 8001B9D4 badvaddr 8001554A reg 00000000
syscall 0: none, at 8001B9EC, reg 00000000
syscall 4: none, at 8001B9EC, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001B7BC, the load at 8001B7BC, value read 00000002
Done.
27 September 2026 (card-2)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 8010D104 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010DC70 PRId 00000002
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 800153D0 at 800153D0 badvaddr 80022DD9 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80015408 at 80015408 badvaddr 80022DDA reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 800153EC at 800153EC badvaddr 80022DD9 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80015424 at 80015424 badvaddr 80022DD9 reg 44332211
sh +1: n 1 code 5 bd 0 epc 80015438 at 80015438 badvaddr 80022DD9 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80015450 at 80015450 badvaddr 80022DD9 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 80015468 at 80015468 badvaddr 80022DD9 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 80015480 at 80015480 badvaddr 80022DD9 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 80015490 at 80015490 badvaddr 80022DD9 reg 00000000
special 01h: n 1 code 10 bd 0 epc 800154A0 at 800154A0 badvaddr 80022DD9 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 800154B8 at 800154B8 badvaddr 80022DD9 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800154E8 at 800154D8 badvaddr 80022DD9 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 8001552C at 8001552C badvaddr 80022DD9 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80015598 at 80015588 badvaddr 80022DD9 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 800150A8 at 800150A8 badvaddr 80022DD9 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 800150B0 at 800150B0 badvaddr 80022DD9 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 800154CE at 800154CE badvaddr 800154CE reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 800154CE reg 00000000
Done.
===== 03 ALU CPU ALU | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/alu
div 00000007 00000002: hi 00000001 lo 00000003
divu 00000007 00000002: hi 00000001 lo 00000003
div FFFFFFF9 00000002: hi FFFFFFFF lo FFFFFFFD
divu FFFFFFF9 00000002: hi 00000001 lo 7FFFFFFC
div 00000007 FFFFFFFE: hi 00000001 lo FFFFFFFD
divu 00000007 FFFFFFFE: hi 00000007 lo 00000000
div FFFFFFF9 FFFFFFFE: hi FFFFFFFF lo 00000003
divu FFFFFFF9 FFFFFFFE: hi FFFFFFF9 lo 00000000
div 00000001 00000000: hi 00000001 lo FFFFFFFF
divu 00000001 00000000: hi 00000001 lo FFFFFFFF
div FFFFFFFF 00000000: hi FFFFFFFF lo 00000001
divu FFFFFFFF 00000000: hi FFFFFFFF lo FFFFFFFF
div 00000000 00000000: hi 00000000 lo FFFFFFFF
divu 00000000 00000000: hi 00000000 lo FFFFFFFF
div 80000000 FFFFFFFF: hi 00000000 lo 80000000
divu 80000000 FFFFFFFF: hi 80000000 lo 00000000
div 80000000 00000000: hi 80000000 lo 00000001
divu 80000000 00000000: hi 80000000 lo FFFFFFFF
div 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
divu 7FFFFFFF 00000000: hi 7FFFFFFF lo FFFFFFFF
div FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
divu FFFFFFFF 00000001: hi 00000000 lo FFFFFFFF
mult 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
multu 7FFFFFFF 7FFFFFFF: hi 3FFFFFFF lo 00000001
mult FFFFFFFF FFFFFFFF: hi 00000000 lo 00000001
multu FFFFFFFF FFFFFFFF: hi FFFFFFFE lo 00000001
mult 80000000 80000000: hi 40000000 lo 00000000
multu 80000000 80000000: hi 40000000 lo 00000000
mult 80000000 FFFFFFFF: hi 00000000 lo 80000000
multu 80000000 FFFFFFFF: hi 7FFFFFFF lo 80000000
mult 12345678 9ABCDEF0: hi F8CC93D6 lo 242D2080
multu 12345678 9ABCDEF0: hi 0B00EA4E lo 242D2080
mult 00000000 FFFFFFFF: hi 00000000 lo 00000000
multu 00000000 FFFFFFFF: hi 00000000 lo 00000000
shift by 00000000: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000001: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000001F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by 00000020: sllv 80000001 srlv 80000001 srav 80000001
shift by 00000021: sllv 00000002 srlv 40000000 srav C0000000
shift by 0000003F: sllv 80000000 srlv 00000001 srav FFFFFFFF
shift by FFFFFFE1: sllv 00000002 srlv 40000000 srav C0000000
slt -1,1 1 sltu -1,1 0 slt 1,-1 0 sltu 1,-1 1
slti 0,-1 0 sltiu 0,-1 1 sltiu FFFFFFFE,-1 1
addiu 0,-8000h FFFF8000 andi FFFFFFFF 0000FFFF ori 0,8000h 00008000 xori FFFFFFFF,8000h FFFF7FFF
nor 0,0 FFFFFFFF
lb 80h FFFFFF80 lb 7Fh 0000007F lh 7F80h 00007F80 lh 8000h FFFF8000
Done.
===== 04 LWX CPU UNALIGNED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/unaligned (memory 44332211 88776655, register AABBCCDD)
lwl +0 11BBCCDD
lwl +1 2211CCDD
lwl +2 332211DD
lwl +3 44332211
lwr +0 44332211
lwr +1 AA443322
lwr +2 AABB4433
lwr +3 AABBCC44
swl +0 EEEEEE11 EEEEEEEE
swl +1 EEEE1122 EEEEEEEE
swl +2 EE112233 EEEEEEEE
swl +3 11223344 EEEEEEEE
swr +0 11223344 EEEEEEEE
swr +1 223344EE EEEEEEEE
swr +2 3344EEEE EEEEEEEE
swr +3 44EEEEEE EEEEEEEE
lwl +3 then lwr +0 44332211
lw +4 then lwl +1 22116655
lw +4 then lwr +1 88443322
lwr +1: in its delay AABBCCDD, after AA443322
Done.
===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 40000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 7FFF8000 7FFF8000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
mtc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
mtc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
lwc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
lwc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
ctc2 then cfc2 at once: cold 00010002, cached 00010002, four later 00030004
ctc2, 1 nop, cfc2: cold 00010002, cached 00010002, four later 00030004
ctc2, 2 nops, cfc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1 then SQR at once: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 then swc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, swc2: cold 00030004, cached 00010002, four later 00030004
mtc2, 2 nops, swc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1, lw, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, mtc2 VXY0, SQR: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, lwc2 VXY0, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: cold 00000004, cached 00000004, four later 00000004
ctc2 TRZ then RTPT at once: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: cold 00030008, cached 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): cold 00000004, cached 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 IR3, 1 nop, SQR (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): cold 00000040, cached 00000040, four later 00000040
lwc2 RGBC then NCCS at once: cold 00000040, cached 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: cold 00000040, cached 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: cold 00000004, cached 00000004, four later 00000004
mtc2 VZ0 then MVMVA at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then MVMVA at once: cold 00000004, cached 00000004, four later 00000004
mtc2 IR1 then INTPL at once (MAC1): cold 00000002, cached 00000002, four later 00000002
mtc2 IR3 then INTPL at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC1 = VX0): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC2 = VY0): cold 00000003, cached 00000003, four later 00000003
ctc2 TRX then RTPS at once (MAC1 = TRX + VX0): cold 00030008, cached 00030008, four later 00030008
mtc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ1 then RTPT at once (SZ2): cold 00000004, cached 00000004, four later 00000004
mtc2 LZCS then mfc2 LZCR at once: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 1 nop, mfc2 LZCR: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 2 nops, mfc2 LZCR: cold 0000000E, cached 0000000E, four later 0000000E
mtc2 IRGB then mfc2 IR1 at once: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 1 nop, mfc2 IR1: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 2 nops, mfc2 IR1: cold 00000200, cached 00000100, four later 00000200
mtc2 SXYP then mfc2 SXY2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 1 nop, mfc2 SXY2: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 2 nops, mfc2 SXY2: cold 00030004, cached 00030004, four later 00030004
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 547 cycles for 100
nop, 20 nops 00000000 00000000: 2572 cycles for 100
mult 00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1127 cycles for 100
mult 00000001 00000003: 1127 cycles for 100
multu 00000001 00000003: 1127 cycles for 100
mult rt 00000003 00000001: 1132 cycles for 100
mult 000007FF 00000003: 1127 cycles for 100
multu 000007FF 00000003: 1127 cycles for 100
mult rt 00000003 000007FF: 1127 cycles for 100
mult 00000800 00000003: 1427 cycles for 100
multu 00000800 00000003: 1427 cycles for 100
mult rt 00000003 00000800: 1127 cycles for 100
mult 000FFFFF 00000003: 1427 cycles for 100
multu 000FFFFF 00000003: 1427 cycles for 100
mult rt 00000003 000FFFFF: 1127 cycles for 100
mult 00100000 00000003: 1827 cycles for 100
multu 00100000 00000003: 1827 cycles for 100
mult rt 00000003 00100000: 1127 cycles for 100
mult 7FFFFFFF 00000003: 1827 cycles for 100
multu 7FFFFFFF 00000003: 1832 cycles for 100
mult rt 00000003 7FFFFFFF: 1147 cycles for 100
mult FFFFFFFF 00000003: 1127 cycles for 100
multu FFFFFFFF 00000003: 1847 cycles for 100
mult rt 00000003 FFFFFFFF: 1127 cycles for 100
mult 80000000 00000003: 1827 cycles for 100
multu 80000000 00000003: 1827 cycles for 100
mult rt 00000003 80000000: 1127 cycles for 100
div 12345678 00000003: 4147 cycles for 100
divu 12345678 00000003: 4147 cycles for 100
div by 0 12345678 00000000: 4147 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2572 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1841 cycles for 100
mult, 2 nops, mflo: 1843 cycles for 100
mult, 3 nops, mflo: 1840 cycles for 100
mult, 4 nops, mflo: 1841 cycles for 100
mult, 5 nops, mflo: 1841 cycles for 100
mult, 6 nops, mflo: 1846 cycles for 100
mult, 7 nops, mflo: 1840 cycles for 100
mult, 8 nops, mflo: 1845 cycles for 100
mult, 9 nops, mflo: 1854 cycles for 100
mult, 10 nops, mflo: 1855 cycles for 100
mult, 11 nops, mflo: 1859 cycles for 100
mult, 12 nops, mflo: 1761 cycles for 100
mult, 13 nops, mflo: 1862 cycles for 100
mult, 14 nops, mflo: 1969 cycles for 100
div, 5 nops, mflo: 4142 cycles for 100
div, 10 nops, mflo: 4146 cycles for 100
div, 30 nops, mflo: 4190 cycles for 100
div, 33 nops, mflo: 4188 cycles for 100
div, 34 nops, mflo: 4192 cycles for 100
div, 35 nops, mflo: 4087 cycles for 100
div, 36 nops, mflo: 4185 cycles for 100
div, 37 nops, mflo: 4299 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1837 cycles for 100
mult, no read: 436 cycles for 100
div, no read: 441 cycles for 100
mult then mtlo: 541 cycles for 100
mult then mthi: 541 cycles for 100
mult then mult then mflo: 1940 cycles for 100
mult then mtlo then mflo: 648 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 80024F4C lw: 954 cycles for 100
RAM KSEG1 A0024F4C lw: 956 cycles for 100
scratchpad 1F800100 lw: 545 cycles for 100
BIOS BFC00100 lw: 2940 cycles for 100
BIOS BFC00100 lh: 1753 cycles for 100
BIOS BFC00100 lb: 1148 cycles for 100
EXP1 1F000084 lb: 1149 cycles for 100
EXP2 1F802000 lb: 1547 cycles for 100
EXP3 1FA00000 lh: 1045 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 750 cycles for 100
DPCR 1F8010F0 lw: 744 cycles for 100
timer 0 1F801100 lw: 744 cycles for 100
JOY_STAT 1F801044 lh: 757 cycles for 100
CDROM status 1F801800 lb: 1247 cycles for 100
GPUSTAT 1F801814 lw: 744 cycles for 100
MDEC status 1F801824 lw: 744 cycles for 100
SPUSTAT 1F801DAE lh: 2245 cycles for 100
SPU word 1F801DAC lw: 4240 cycles for 100
cache control FFFE0130 lw: 544 cycles for 100
RAM lw, used at once: 957 cycles for 100
RAM lw, used after 1 nop: 1258 cycles for 100
RAM lw, used after 2 nops: 1357 cycles for 100
RAM lw, used after 3 nops: 1356 cycles for 100
RAM lw then lw: 1464 cycles for 100
BIOS lw, used at once: 2923 cycles for 100
BIOS lw, used after 3 nops: 3320 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 452 cycles for 100
RAM, 2 sw: 564 cycles for 100
RAM, 3 sw: 667 cycles for 100
RAM, 4 sw: 888 cycles for 100
RAM, 5 sw: 1114 cycles for 100
RAM, 6 sw: 1316 cycles for 100
RAM, 7 sw: 1522 cycles for 100
RAM, 8 sw: 1722 cycles for 100
RAM, 4 sw then lw: 2105 cycles for 100
RAM, sw then lw: 1470 cycles for 100
scratchpad, 1 sw: 441 cycles for 100
scratchpad, 8 sw: 1148 cycles for 100
I_MASK, 1 sw: 420 cycles for 100
I_MASK, 4 sw: 845 cycles for 100
I_MASK, sw then lw: 820 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1468 cycles for 100
RAM sw, 2 nops, lw: 1480 cycles for 100
RAM sw, 3 nops, lw: 1472 cycles for 100
RAM sw, 4 nops, lw: 1469 cycles for 100
RAM sw, 6 nops, lw: 1579 cycles for 100
RAM sw, lw of another word: 1479 cycles for 100
RAM 4 sw, lw of another word: 2107 cycles for 100
chain-looping's loop: 1653 cycles for 100
RAM lw, used after 4 nops: 1356 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 750 cycles for 100
I_STAT lw, used after 1 nop: 1035 cycles for 100
I_STAT lw, used after 2 nops: 1137 cycles for 100
I_STAT lw then lw: 1140 cycles for 100
BIOS lw, used after 1 nop: 3220 cycles for 100
BIOS lw, used after 2 nops: 3320 cycles for 100
BIOS lw then lw: 5418 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 420 cycles for 100
GP0 NOP, 4 sw: 818 cycles for 100
CDROM index, 1 sb: 622 cycles for 100
CDROM index, 4 sb: 2436 cycles for 100
SPU main volume, 1 sh: 805 cycles for 100
SPU main volume, 4 sh: 3213 cycles for 100
scratchpad, 4 sw: 749 cycles for 100
RAM, 1 sh: 442 cycles for 100
RAM, 4 sh: 892 cycles for 100
RAM, 4 sb: 903 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1479 cycles for 100
RAM sw, 7 nops, lw: 1660 cycles for 100
RAM sw, 8 nops, lw: 1775 cycles for 100
RAM 5 nops, lw (no store): 1252 cycles for 100
RAM 7 nops, lw (no store): 1458 cycles for 100
RAM 9 nops, lw (no store): 1651 cycles for 100
chain-looping's loop, the sw a nop: 1468 cycles for 100
I_STAT lw, used after 3 nops: 1149 cycles for 100
I_STAT lw, used after 4 nops: 1144 cycles for 100
SPU word lw then lw: 8244 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 650 cycles for 100
mult, mthi, mflo: 646 cycles for 100
mult, mtlo, mfhi: 653 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3103 cycles for 100
nop, 20 nops loop: 15292 cycles for 100
RAM lw loop: 3516 cycles for 100
Done.
===== 07 MIR CPU MIRRORS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/mirrors and memory control
memctrl 1F801000: 1F000000
memctrl 1F801004: 1F802000
memctrl 1F801008: 0013243F
memctrl 1F80100C: 00003022
memctrl 1F801010: 0013243F
memctrl 1F801014: 200931E1
memctrl 1F801018: 00020843
memctrl 1F80101C: 00070777
memctrl 1F801020: 00031125
RAM_SIZE 1F801060: 03E00B88
cache control FFFE0130: 0001E988
RAM word at 00024E8C holds C0FFEE01
KUSEG 00024E8C: C0FFEE01
KUSEG +2MB 00224E8C: C0FFEE01
KUSEG +4MB 00424E8C: C0FFEE01
KUSEG +6MB 00624E8C: C0FFEE01
KSEG0 +2MB 80224E8C: C0FFEE01
KSEG1 A0024E8C: C0FFEE01
KSEG1 +6MB A0624E8C: C0FFEE01
scratchpad word 1F800000 holds 5C4A7C11
scratchpad KUSEG 1F800000: 5C4A7C11
scratchpad KSEG0 9F800000: 5C4A7C11
BIOS KUSEG 1FC00100: 19951204
BIOS KSEG0 9FC00100: 19951204
BIOS KSEG1 BFC00100: 19951204
store then line fill, RAM_SIZE read after it (fill's upper half 3C00):
no store: 3C000B88
RAM store 5EED1234, 1 before the fill: 3C000B88
RAM store 5EED1234, 2 before the fill: 3C000B88
RAM store 5EED1234, 3 before the fill: 3C000B88
I_MASK store 0C000009, 1 before the fill: 00000B88
I_MASK store 0C000009, 2 before the fill: 00000B88
I_MASK store 0C000009, 3 before the fill: 3C000B88
marked line (its words' upper halves 8C82, 2400, 3400, 3C00):
no store: 3C000B88
RAM store, 1 before: 3C000B88; 3 before: 3C000B88
I_MASK store 0C000009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
I_MASK store ABCD0009, 1, 2, 3 before: 00000B88 00000B88 3C000B88
probe at 800261B0
Done.
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/instruction cache (code at 800262C0)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 2
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 3
loop from KSEG0: 325 then 304 cycles
loop from KSEG1: 1848 then 1848 cycles
Done.
===== 09 BRK CPU COP0 DEBUG | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/COP0 debug registers (psx-spx cpuspecifications.txt:937-1050)
all ones written: BPC FFFFFFFF BDA FFFFFFFF BDAM FFFFFFFF BPCM FFFFFFFF; DCIC 0000C03F reads 0000C03F
data read break armed, watched word read: DCIC 2680000D
data write break armed, watched word written: DCIC 2A800015
data read break armed, another word read: DCIC 26800000
PC break armed, target called: DCIC 21800003
data read break armed, read with interrupts on: DCIC 26800000
Done.
===== 10 BUW CPU BUS WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/bus writes
sw 7FFAF614: exception 7, reg 00000000, badvaddr 68000000 to 800154CE
none, reg 12345678, badvaddr 800154CE to 800154CE
lw 7FFAF614: exception 7, reg 5A5A5A5A, badvaddr 800154CE to 800154CE
sw 20000000: exception 7, reg 00000000, badvaddr 68000000 to 800154CE
none, reg 12345678, badvaddr 800154CE to 800154CE
lw 20000000: exception 7, reg 5A5A5A5A, badvaddr 800154CE to 800154CE
Done.
===== 11 SYS CPU BREAK SYSCALL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/BREAK and SYSCALL (the BIOS's handler decides what reaches A(40h))
break: n 1 code 9 bd 0 epc 8001B958 at 8001B958 badvaddr 800154CE reg 00000000
syscall 0: none, at 8001B970, reg 00000000
syscall 4: none, at 8001B970, reg 00000000
Done.
===== 12 BRT CPU BREAK TRAP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/COP0 data break with TR set: jumps to 80000040h, Cause 09h (cpuspecifications.txt:1031-1036)
after: DCIC 00000000, Cause 00000024 (code 9), EPC 8001B740, the load at 8001B740, value read 00000002
Done.
Output files that match an earlier run: 01BUK.txt (as run 20260926T0000Z-5501a-card-cpu-3).
27 September 2026 (card-d)
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 8010D104 DCIC 00000000 BadVaddr 00000400 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010DC70 PRId 00000002
===== 02 EXC CPU EXCEPTIONS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
cpu/exceptions
lw +1: n 1 code 4 bd 0 epc 800153D0 at 800153D0 badvaddr 80022DD9 reg 5A5A5A5A
lw +2: n 1 code 4 bd 0 epc 80015408 at 80015408 badvaddr 80022DDA reg 5A5A5A5A
lh +1: n 1 code 4 bd 0 epc 800153EC at 800153EC badvaddr 80022DD9 reg 5A5A5A5A
sw +1: n 1 code 5 bd 0 epc 80015424 at 80015424 badvaddr 80022DD9 reg 44332211
sh +1: n 1 code 5 bd 0 epc 80015438 at 80015438 badvaddr 80022DD9 reg 44332211
add 7FFFFFFF+1: n 1 code 12 bd 0 epc 80015450 at 80015450 badvaddr 80022DD9 reg 5A5A5A5A
addi 7FFFFFFF+1: n 1 code 12 bd 0 epc 80015468 at 80015468 badvaddr 80022DD9 reg 5A5A5A5A
sub 80000000-1: n 1 code 12 bd 0 epc 80015480 at 80015480 badvaddr 80022DD9 reg 5A5A5A5A
opcode 3Fh: n 1 code 10 bd 0 epc 80015490 at 80015490 badvaddr 80022DD9 reg 00000000
special 01h: n 1 code 10 bd 0 epc 800154A0 at 800154A0 badvaddr 80022DD9 reg 00000000
lw 7FFAF614: n 1 code 7 bd 0 epc 800154B8 at 800154B8 badvaddr 80022DD9 reg 5A5A5A5A
lw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 800154E8 at 800154D8 badvaddr 80022DD9 reg 0000000F
lw 7FFAF614, nop, use, 16 addiu, count: n 1 code 7 bd 0 epc 8001552C at 8001552C badvaddr 80022DD9 reg 00000010
sw 7FFAF614 then 16 addiu, count: n 1 code 7 bd 0 epc 80015598 at 80015588 badvaddr 80022DD9 reg 0000000F
lw +1 in jr slot: n 1 code 4 bd 1 epc 800150A8 at 800150A8 badvaddr 80022DD9 reg 00000000
add ov in beq slot: n 1 code 12 bd 1 epc 800150B0 at 800150B0 badvaddr 80022DD9 reg 00000000
jump to +2: n 1 code 4 bd 0 epc 800154CE at 800154CE badvaddr 800154CE reg 00000000
jump to 7FFAF610: n 1 code 6 bd 0 epc 7FFAF610 at 7FFAF610 badvaddr 800154CE reg 00000000
Done.
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 547 cycles for 100
nop, 20 nops 00000000 00000000: 2572 cycles for 100
mult 00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1127 cycles for 100
mult 00000001 00000003: 1127 cycles for 100
multu 00000001 00000003: 1127 cycles for 100
mult rt 00000003 00000001: 1132 cycles for 100
mult 000007FF 00000003: 1127 cycles for 100
multu 000007FF 00000003: 1127 cycles for 100
mult rt 00000003 000007FF: 1127 cycles for 100
mult 00000800 00000003: 1427 cycles for 100
multu 00000800 00000003: 1427 cycles for 100
mult rt 00000003 00000800: 1127 cycles for 100
mult 000FFFFF 00000003: 1427 cycles for 100
multu 000FFFFF 00000003: 1427 cycles for 100
mult rt 00000003 000FFFFF: 1127 cycles for 100
mult 00100000 00000003: 1827 cycles for 100
multu 00100000 00000003: 1827 cycles for 100
mult rt 00000003 00100000: 1127 cycles for 100
mult 7FFFFFFF 00000003: 1827 cycles for 100
multu 7FFFFFFF 00000003: 1832 cycles for 100
mult rt 00000003 7FFFFFFF: 1147 cycles for 100
mult FFFFFFFF 00000003: 1127 cycles for 100
multu FFFFFFFF 00000003: 1847 cycles for 100
mult rt 00000003 FFFFFFFF: 1127 cycles for 100
mult 80000000 00000003: 1827 cycles for 100
multu 80000000 00000003: 1827 cycles for 100
mult rt 00000003 80000000: 1127 cycles for 100
div 12345678 00000003: 4147 cycles for 100
divu 12345678 00000003: 4150 cycles for 100
div by 0 12345678 00000000: 4147 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2572 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1841 cycles for 100
mult, 2 nops, mflo: 1843 cycles for 100
mult, 3 nops, mflo: 1840 cycles for 100
mult, 4 nops, mflo: 1841 cycles for 100
mult, 5 nops, mflo: 1841 cycles for 100
mult, 6 nops, mflo: 1846 cycles for 100
mult, 7 nops, mflo: 1840 cycles for 100
mult, 8 nops, mflo: 1845 cycles for 100
mult, 9 nops, mflo: 1854 cycles for 100
mult, 10 nops, mflo: 1855 cycles for 100
mult, 11 nops, mflo: 1859 cycles for 100
mult, 12 nops, mflo: 1761 cycles for 100
mult, 13 nops, mflo: 1862 cycles for 100
mult, 14 nops, mflo: 1969 cycles for 100
div, 5 nops, mflo: 4142 cycles for 100
div, 10 nops, mflo: 4146 cycles for 100
div, 30 nops, mflo: 4190 cycles for 100
div, 33 nops, mflo: 4188 cycles for 100
div, 34 nops, mflo: 4192 cycles for 100
div, 35 nops, mflo: 4087 cycles for 100
div, 36 nops, mflo: 4185 cycles for 100
div, 37 nops, mflo: 4299 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1837 cycles for 100
mult, no read: 436 cycles for 100
div, no read: 441 cycles for 100
mult then mtlo: 541 cycles for 100
mult then mthi: 541 cycles for 100
mult then mult then mflo: 1940 cycles for 100
mult then mtlo then mflo: 648 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 80024F4C lw: 954 cycles for 100
RAM KSEG1 A0024F4C lw: 956 cycles for 100
scratchpad 1F800100 lw: 545 cycles for 100
BIOS BFC00100 lw: 2940 cycles for 100
BIOS BFC00100 lh: 1753 cycles for 100
BIOS BFC00100 lb: 1148 cycles for 100
EXP1 1F000084 lb: 1149 cycles for 100
EXP2 1F802000 lb: 1547 cycles for 100
EXP3 1FA00000 lh: 1045 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 750 cycles for 100
DPCR 1F8010F0 lw: 744 cycles for 100
timer 0 1F801100 lw: 744 cycles for 100
JOY_STAT 1F801044 lh: 757 cycles for 100
CDROM status 1F801800 lb: 1247 cycles for 100
GPUSTAT 1F801814 lw: 744 cycles for 100
MDEC status 1F801824 lw: 744 cycles for 100
SPUSTAT 1F801DAE lh: 2245 cycles for 100
SPU word 1F801DAC lw: 4240 cycles for 100
cache control FFFE0130 lw: 544 cycles for 100
RAM lw, used at once: 957 cycles for 100
RAM lw, used after 1 nop: 1258 cycles for 100
RAM lw, used after 2 nops: 1357 cycles for 100
RAM lw, used after 3 nops: 1356 cycles for 100
RAM lw then lw: 1464 cycles for 100
BIOS lw, used at once: 2923 cycles for 100
BIOS lw, used after 3 nops: 3320 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 452 cycles for 100
RAM, 2 sw: 564 cycles for 100
RAM, 3 sw: 667 cycles for 100
RAM, 4 sw: 888 cycles for 100
RAM, 5 sw: 1114 cycles for 100
RAM, 6 sw: 1316 cycles for 100
RAM, 7 sw: 1522 cycles for 100
RAM, 8 sw: 1722 cycles for 100
RAM, 4 sw then lw: 2105 cycles for 100
RAM, sw then lw: 1470 cycles for 100
scratchpad, 1 sw: 441 cycles for 100
scratchpad, 8 sw: 1148 cycles for 100
I_MASK, 1 sw: 420 cycles for 100
I_MASK, 4 sw: 845 cycles for 100
I_MASK, sw then lw: 820 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1468 cycles for 100
RAM sw, 2 nops, lw: 1480 cycles for 100
RAM sw, 3 nops, lw: 1472 cycles for 100
RAM sw, 4 nops, lw: 1469 cycles for 100
RAM sw, 6 nops, lw: 1579 cycles for 100
RAM sw, lw of another word: 1479 cycles for 100
RAM 4 sw, lw of another word: 2107 cycles for 100
chain-looping's loop: 1653 cycles for 100
RAM lw, used after 4 nops: 1356 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 750 cycles for 100
I_STAT lw, used after 1 nop: 1035 cycles for 100
I_STAT lw, used after 2 nops: 1137 cycles for 100
I_STAT lw then lw: 1140 cycles for 100
BIOS lw, used after 1 nop: 3220 cycles for 100
BIOS lw, used after 2 nops: 3320 cycles for 100
BIOS lw then lw: 5418 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 420 cycles for 100
GP0 NOP, 4 sw: 818 cycles for 100
CDROM index, 1 sb: 622 cycles for 100
CDROM index, 4 sb: 2436 cycles for 100
SPU main volume, 1 sh: 805 cycles for 100
SPU main volume, 4 sh: 3213 cycles for 100
scratchpad, 4 sw: 749 cycles for 100
RAM, 1 sh: 442 cycles for 100
RAM, 4 sh: 892 cycles for 100
RAM, 4 sb: 903 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1479 cycles for 100
RAM sw, 7 nops, lw: 1660 cycles for 100
RAM sw, 8 nops, lw: 1775 cycles for 100
RAM 5 nops, lw (no store): 1252 cycles for 100
RAM 7 nops, lw (no store): 1458 cycles for 100
RAM 9 nops, lw (no store): 1651 cycles for 100
chain-looping's loop, the sw a nop: 1468 cycles for 100
I_STAT lw, used after 3 nops: 1149 cycles for 100
I_STAT lw, used after 4 nops: 1144 cycles for 100
SPU word lw then lw: 8244 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 650 cycles for 100
mult, mthi, mflo: 646 cycles for 100
mult, mtlo, mfhi: 653 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3103 cycles for 100
nop, 20 nops loop: 15292 cycles for 100
RAM lw loop: 3516 cycles for 100
Done.
Output files that match an earlier run: 01BUK.txt (as run 20260927T0000Z-5501a-card-1) · 03ALU.txt (as run 20260927T0000Z-5501a-card-2) · 04LWX.txt (as run 20260927T0000Z-5501a-card-2) · 05DLY.txt (as run 20260927T0000Z-5501a-card-2) · 07MIR.txt (as run 20260927T0000Z-5501a-card-2) · 08CAC.txt (as run 20260927T0000Z-5501a-card-2) · 09BRK.txt (as run 20260927T0000Z-5501a-card-2) · 10BUW.txt (as run 20260927T0000Z-5501a-card-2) · 11SYS.txt (as run 20260927T0000Z-5501a-card-2) · 12BRT.txt (as run 20260927T0000Z-5501a-card-2).
27 September 2026 (card-g2)
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/instruction cache (code at 800262C0)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 2
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 3
loop from KSEG0: 325 then 304 cycles
loop from KSEG1: 1850 then 1850 cycles
Done.
Output files that match an earlier run: 00RUN.txt (as run 20260927T0000Z-5501a-card-d) · 01BUK.txt (as run 20260927T0000Z-5501a-card-1) · 02EXC.txt (as run 20260927T0000Z-5501a-card-d) · 03ALU.txt (as run 20260927T0000Z-5501a-card-2) · 04LWX.txt (as run 20260927T0000Z-5501a-card-2) · 05DLY.txt (as run 20260927T0000Z-5501a-card-2) · 06TIM.txt (as run 20260927T0000Z-5501a-card-2) · 07MIR.txt (as run 20260927T0000Z-5501a-card-2) · 09BRK.txt (as run 20260927T0000Z-5501a-card-2) · 10BUW.txt (as run 20260927T0000Z-5501a-card-2) · 11SYS.txt (as run 20260927T0000Z-5501a-card-2) · 12BRT.txt (as run 20260927T0000Z-5501a-card-2).
27 September 2026 (card-g3)
===== 08 CAC CPU ICACHE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/instruction cache (code at 800262C0)
returns 1, run twice through KSEG0: 1 1
changed to 2, no flush: KSEG0 1
then KSEG1 2
then KSEG0 2
after FlushCache: KSEG0 2
changed to 3: KSEG1 first 2, then KSEG0 3
loop from KSEG0: 325 then 304 cycles
loop from KSEG1: 1848 then 1852 cycles
Done.
Output files that match an earlier run: 00RUN.txt (as run 20260927T0000Z-5501a-card-2) · 01BUK.txt (as run 20260926T0000Z-5501a-card-cpu-3) · 02EXC.txt (as run 20260927T0000Z-5501a-card-2) · 03ALU.txt (as run 20260927T0000Z-5501a-card-2) · 04LWX.txt (as run 20260927T0000Z-5501a-card-2) · 05DLY.txt (as run 20260927T0000Z-5501a-card-2) · 06TIM.txt (as run 20260927T0000Z-5501a-card-2) · 07MIR.txt (as run 20260927T0000Z-5501a-card-2) · 09BRK.txt (as run 20260927T0000Z-5501a-card-2) · 10BUW.txt (as run 20260927T0000Z-5501a-card-2) · 11SYS.txt (as run 20260927T0000Z-5501a-card-2) · 12BRT.txt (as run 20260927T0000Z-5501a-card-2).
28 September 2026 (card-h)
===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
cpu/mult div timing (timer 2, system clock)
nop 00000000 00000000: 547 cycles for 100
nop, 20 nops 00000000 00000000: 2572 cycles for 100
mult 00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1127 cycles for 100
mult 00000001 00000003: 1127 cycles for 100
multu 00000001 00000003: 1132 cycles for 100
mult rt 00000003 00000001: 1127 cycles for 100
mult 000007FF 00000003: 1127 cycles for 100
multu 000007FF 00000003: 1127 cycles for 100
mult rt 00000003 000007FF: 1127 cycles for 100
mult 00000800 00000003: 1427 cycles for 100
multu 00000800 00000003: 1427 cycles for 100
mult rt 00000003 00000800: 1132 cycles for 100
mult 000FFFFF 00000003: 1427 cycles for 100
multu 000FFFFF 00000003: 1427 cycles for 100
mult rt 00000003 000FFFFF: 1127 cycles for 100
mult 00100000 00000003: 1827 cycles for 100
multu 00100000 00000003: 1827 cycles for 100
mult rt 00000003 00100000: 1127 cycles for 100
mult 7FFFFFFF 00000003: 1827 cycles for 100
multu 7FFFFFFF 00000003: 1827 cycles for 100
mult rt 00000003 7FFFFFFF: 1147 cycles for 100
mult FFFFFFFF 00000003: 1127 cycles for 100
multu FFFFFFFF 00000003: 1852 cycles for 100
mult rt 00000003 FFFFFFFF: 1127 cycles for 100
mult 80000000 00000003: 1827 cycles for 100
multu 80000000 00000003: 1827 cycles for 100
mult rt 00000003 80000000: 1127 cycles for 100
div 12345678 00000003: 4147 cycles for 100
divu 12345678 00000003: 4150 cycles for 100
div by 0 12345678 00000000: 4147 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2572 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1841 cycles for 100
mult, 2 nops, mflo: 1843 cycles for 100
mult, 3 nops, mflo: 1840 cycles for 100
mult, 4 nops, mflo: 1841 cycles for 100
mult, 5 nops, mflo: 1841 cycles for 100
mult, 6 nops, mflo: 1846 cycles for 100
mult, 7 nops, mflo: 1840 cycles for 100
mult, 8 nops, mflo: 1845 cycles for 100
mult, 9 nops, mflo: 1854 cycles for 100
mult, 10 nops, mflo: 1855 cycles for 100
mult, 11 nops, mflo: 1859 cycles for 100
mult, 12 nops, mflo: 1761 cycles for 100
mult, 13 nops, mflo: 1862 cycles for 100
mult, 14 nops, mflo: 1972 cycles for 100
div, 5 nops, mflo: 4142 cycles for 100
div, 10 nops, mflo: 4146 cycles for 100
div, 30 nops, mflo: 4190 cycles for 100
div, 33 nops, mflo: 4188 cycles for 100
div, 34 nops, mflo: 4192 cycles for 100
div, 35 nops, mflo: 4087 cycles for 100
div, 36 nops, mflo: 4185 cycles for 100
div, 37 nops, mflo: 4299 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1837 cycles for 100
mult, no read: 436 cycles for 100
div, no read: 441 cycles for 100
mult then mtlo: 541 cycles for 100
mult then mthi: 541 cycles for 100
mult then mult then mflo: 1940 cycles for 100
mult then mtlo then mflo: 648 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 80024F4C lw: 954 cycles for 100
RAM KSEG1 A0024F4C lw: 956 cycles for 100
scratchpad 1F800100 lw: 545 cycles for 100
BIOS BFC00100 lw: 2940 cycles for 100
BIOS BFC00100 lh: 1753 cycles for 100
BIOS BFC00100 lb: 1148 cycles for 100
EXP1 1F000084 lb: 1149 cycles for 100
EXP2 1F802000 lb: 1547 cycles for 100
EXP3 1FA00000 lh: 1060 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 750 cycles for 100
DPCR 1F8010F0 lw: 744 cycles for 100
timer 0 1F801100 lw: 745 cycles for 100
JOY_STAT 1F801044 lh: 748 cycles for 100
CDROM status 1F801800 lb: 1247 cycles for 100
GPUSTAT 1F801814 lw: 744 cycles for 100
MDEC status 1F801824 lw: 744 cycles for 100
SPUSTAT 1F801DAE lh: 2251 cycles for 100
SPU word 1F801DAC lw: 4240 cycles for 100
cache control FFFE0130 lw: 544 cycles for 100
RAM lw, used at once: 965 cycles for 100
RAM lw, used after 1 nop: 1257 cycles for 100
RAM lw, used after 2 nops: 1352 cycles for 100
RAM lw, used after 3 nops: 1358 cycles for 100
RAM lw then lw: 1465 cycles for 100
BIOS lw, used at once: 2926 cycles for 100
BIOS lw, used after 3 nops: 3320 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 446 cycles for 100
RAM, 2 sw: 561 cycles for 100
RAM, 3 sw: 667 cycles for 100
RAM, 4 sw: 887 cycles for 100
RAM, 5 sw: 1109 cycles for 100
RAM, 6 sw: 1316 cycles for 100
RAM, 7 sw: 1522 cycles for 100
RAM, 8 sw: 1722 cycles for 100
RAM, 4 sw then lw: 2105 cycles for 100
RAM, sw then lw: 1466 cycles for 100
scratchpad, 1 sw: 441 cycles for 100
scratchpad, 8 sw: 1146 cycles for 100
I_MASK, 1 sw: 420 cycles for 100
I_MASK, 4 sw: 845 cycles for 100
I_MASK, sw then lw: 820 cycles for 100
a store, n instructions, then a load of its word:
RAM sw, 1 nop, lw: 1471 cycles for 100
RAM sw, 2 nops, lw: 1467 cycles for 100
RAM sw, 3 nops, lw: 1479 cycles for 100
RAM sw, 4 nops, lw: 1481 cycles for 100
RAM sw, 6 nops, lw: 1579 cycles for 100
RAM sw, lw of another word: 1479 cycles for 100
RAM 4 sw, lw of another word: 2107 cycles for 100
chain-looping's loop: 1653 cycles for 100
RAM lw, used after 4 nops: 1356 cycles for 100
IO and BIOS loads used after the delay slot:
I_STAT lw, used at once: 750 cycles for 100
I_STAT lw, used after 1 nop: 1035 cycles for 100
I_STAT lw, used after 2 nops: 1137 cycles for 100
I_STAT lw then lw: 1140 cycles for 100
BIOS lw, used after 1 nop: 3220 cycles for 100
BIOS lw, used after 2 nops: 3320 cycles for 100
BIOS lw then lw: 5418 cycles for 100
stores to other devices, each writing back what is there:
GP0 NOP, 1 sw: 420 cycles for 100
GP0 NOP, 4 sw: 818 cycles for 100
CDROM index, 1 sb: 622 cycles for 100
CDROM index, 4 sb: 2436 cycles for 100
SPU main volume, 1 sh: 805 cycles for 100
SPU main volume, 4 sh: 3213 cycles for 100
scratchpad, 4 sw: 749 cycles for 100
RAM, 1 sh: 442 cycles for 100
RAM, 4 sh: 892 cycles for 100
RAM, 4 sb: 903 cycles for 100
card 5, the store-then-load curve with baselines:
RAM sw, 5 nops, lw: 1479 cycles for 100
RAM sw, 7 nops, lw: 1660 cycles for 100
RAM sw, 8 nops, lw: 1775 cycles for 100
RAM 5 nops, lw (no store): 1252 cycles for 100
RAM 7 nops, lw (no store): 1458 cycles for 100
RAM 9 nops, lw (no store): 1651 cycles for 100
chain-looping's loop, the sw a nop: 1468 cycles for 100
I_STAT lw, used after 3 nops: 1149 cycles for 100
I_STAT lw, used after 4 nops: 1144 cycles for 100
SPU word lw then lw: 8244 cycles for 100
mthi and mtlo after a busy multiply (rs 00100000):
mult, mthi, mfhi: 650 cycles for 100
mult, mthi, mflo: 646 cycles for 100
mult, mtlo, mfhi: 653 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3103 cycles for 100
nop, 20 nops loop: 15292 cycles for 100
RAM lw loop: 3516 cycles for 100
Done.
Output files that match an earlier run: 00RUN.txt (as run 20260927T0000Z-5501a-card-2) · 01BUK.txt (as run 20260926T0000Z-5501a-card-cpu-3) · 02EXC.txt (as run 20260927T0000Z-5501a-card-2) · 03ALU.txt (as run 20260927T0000Z-5501a-card-2) · 04LWX.txt (as run 20260927T0000Z-5501a-card-2) · 05DLY.txt (as run 20260927T0000Z-5501a-card-2) · 07MIR.txt (as run 20260927T0000Z-5501a-card-2) · 08CAC.txt (as run 20260927T0000Z-5501a-card-2) · 09BRK.txt (as run 20260927T0000Z-5501a-card-2) · 10BUW.txt (as run 20260927T0000Z-5501a-card-2) · 11SYS.txt (as run 20260927T0000Z-5501a-card-2) · 12BRT.txt (as run 20260927T0000Z-5501a-card-2).
References
Categories: Hardware tests