DMA List Loops: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ## Overview | ## Overview | ||
| − | The work is a loop of 1000 additions to a variable in RAM. Root counter 2 times it in units of 8 system clock cycles, and the program prints the time in cycles. The program times it once with no DMA running. It then starts [DMA](/hardware/dma/) channel 2 in list mode (sync mode 2) on three lists: a list with one entry that ends at once, a list whose only entry points to itself, and two entries that point to each other.[^src] | + | The work is a loop of 1000 additions to a variable in RAM. Root counter 2 times it in units of 8 system clock cycles, and the program prints the time in cycles. The program times it once with no DMA running. It then starts [DMA](/hardware/dma/) channel 2 in list mode (sync mode 2) on three lists: a list with one entry that ends at once, a list whose only entry points to itself, and two entries that point to each other.[^src] After the work the program reads whether CHCR bit 24 has cleared (finished) and whether the channel's DICR flag is set (irq), then stops the channel.[^src] |
| − | After the work the program reads whether CHCR bit 24 has cleared (finished) and whether the channel's DICR flag is set (irq), then stops the channel.[^src] | ||
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| ## Results | ## Results | ||