DMA Registers and Interrupt Latency: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| Times are counted on root counter 2 in system clock cycles, from the CHCR write (or the DPCR write) to the first poll that sees CHCR bit 24 clear. Rows that might pass 131071 clocks count at system clock / 8 and are given here in system clocks. The safe build that ran on the console holds groups 01 to 05.[^run] | Times are counted on root counter 2 in system clock cycles, from the CHCR write (or the DPCR write) to the first poll that sees CHCR bit 24 clear. Rows that might pass 131071 clocks count at system clock / 8 and are given here in system clocks. The safe build that ran on the console holds groups 01 to 05.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [DMA Registers and Timer Pulse Mode](/tests/dma-registers-timer-pulse-mode/) | ||
| + | |||
| ## Results | ## Results | ||