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Hardware tests

DMA Registers and Interrupt Latency

Measures every DMA register bit, OTC lengths, DICR flags on five kinds of transfer and three-channel priority.

DMA Registers and Interrupt Latency
MachineSCPH-5501
Programdma2

Overview

The program continues the DMA Timing test on the DMA controller. It writes each register one bit at a time, runs OTC transfers at 44 lengths with every entry checked, and sets DICR around five kinds of transfer. It also measures how soon the DICR flag and I_STAT bit 3 follow the end of a transfer, and starts three channels with one DPCR write.1

Times are counted on root counter 2 in system clock cycles, from the CHCR write (or the DPCR write) to the first poll that sees CHCR bit 24 clear. Rows that might pass 131071 clocks count at system clock / 8 and are given here in system clocks. The safe build that ran on the console holds groups 01 to 05.1

See also:

Results

Register Bits

MADR keeps bits 0 to 23 on every channel and BCR keeps all 32 bits. CHCR on channels 0 to 5 keeps 71770703h. Channel 6 CHCR keeps 51000002h: bit 1 always reads 1, and writing bit 0 or bit 2 reads back 00000002h. DPCR keeps every bit.2

Table 1: DICR written one bit at a time
Bits written Read back
0 to 5 kept
6 to 14 read 0
15 80008000h, and I_STAT bit 3 is set
16 to 23 kept
31 read 0
24 to 30 with no flag set read 0

OTC Lengths

Every entry of every OTC table was right at all 44 lengths from 1 to 4096 words, and the guard words on both sides were kept. MADR and BCR keep their start values. After the first transfer a 2-word OTC took 54 clocks. 256 words took 320 clocks and 4096 words took 4395. Long tables cost about 1.06 clocks a word.3

The OTC ignores the low two bits of MADR and bits 24 to 31, and it writes the same table at the word address. It also ignores the upper half of BCR, CHCR bits 0 and 1, the chopping bit and the SyncMode bits. Bit 30 stays set in CHCR after the transfer. Without bit 28 the OTC does not start, and the poll timed out with the table unwritten.3

DICR Flags

On every channel tested, a transfer sets its DICR flag (bit 24+n) when its enable bit (16+n) is set, with or without bit 23. Bit 31 and I_STAT bit 3 are set only when bit 23 is set as well.4

Table 2: DICR after one transfer of each kind
Transfer Enable alone Enable and bit 23 Bit 23 alone
OTC (channel 6) 40400000h C0C00000h, IRQ3 00800000h
GPU write (channel 2) 04040000h 84840000h, IRQ3 00800000h
SPU write (channel 4) 10100000h 90900000h, IRQ3 00800000h
MDEC0 table (channel 0) 01010000h 81810000h, IRQ3 00800000h
MDEC1 block (channel 1) 02020000h 82820000h, IRQ3 00800000h

Writing 0 to CHCR bit 24 part way stops a transfer. BCR holds the remaining block count, and 5000 clocks later it still holds the same count. No flag is set. Writing the same CHCR again continues the transfer to the end, and the flag and IRQ3 then follow.4

A flag set while bit 23 was off raises IRQ3 as soon as bit 23 is written. Writing 0 to a flag keeps it, and writing 1 clears it.4

Interrupt Latency

For OTC, GPU, MDEC0 and MDEC1 transfers the DICR flag and I_STAT bit 3 appeared at the same poll as CHCR bit 24 clearing. For a 64-word SPU write in SyncMode 1, I_STAT bit 3 appeared about 220 clocks before bit 24 cleared: 3319 against 3539 on one sample and 3321 against 3541 on the next.5

Three Channels

An OTC of 1024 words, a GPU VRAM read of 512 words and an SPU read of 512 words were armed and started by one DPCR write. Across nine priority settings the OTC finished at 1280 to 1528 clocks, the GPU read at 2280 to 2568 and the SPU read at 35912 to 37048. With the OTC at priority 7 and the others at 0, the OTC reported done at 256 clocks.6

Runs

27 September 2026 card-g2

Raw output: 00RUN.txt · 01DRM.txt · 02DOT.txt · 03DIC.txt · 04DCI.txt · 05DPR.txt

00RUN.txt:

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 800154CE BDAM FFFFFFFF
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001CA54 PRId 00000002

01DRM.txt:

===== 01 DRM D2 REGISTER BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Each register written one bit at a time and read back, each channel with its DPCR
enable off (channels.txt:18-87). CHCR is written 0 before any enable comes back.
Channel 0:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 1:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 2:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 3:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 4:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 5:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 6:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR bit 0 written reads 00000002
  CHCR bit 2 written reads 00000002
  CHCR keeps 51000002; FFFFFFFFh reads 51000002; 0 reads 00000002
DPCR one bit at a time (every CHCR 0):
  keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF
DICR bits 0-23 one at a time, with I_STAT bit 3 after each (bit 15 forces it):
  0:00000001/0  1:00000002/0  2:00000004/0  3:00000008/0
  4:00000010/0  5:00000020/0  6:00000000/0  7:00000000/0
  8:00000000/0  9:00000000/0 10:00000000/0 11:00000000/0
 12:00000000/0 13:00000000/0 14:00000000/0 15:80008000/1
 16:00010000/0 17:00020000/0 18:00040000/0 19:00080000/0
 20:00100000/0 21:00200000/0 22:00400000/0 23:00800000/0
DICR 80000000h (bit 31 written) reads 00000000
DICR 7F000000h (every flag written 1, none set) reads 00000000
Done.

02DOT.txt:

===== 02 DOT D2 OTC LENGTHS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
OTC (CHCR 11000002h) of n words: clocks from the CHCR write to bit 24 clear, every
entry checked (the first FFFFFFh, the rest the address below, channels.txt:143-151),
a guard word on each side, MADR, BCR and CHCR after.
   1 words: 89, 0 wrong, guards kept, MADR moved 0, BCR 00000001, CHCR 00000002
   2 words: 58, 0 wrong, guards kept, MADR moved 0, BCR 00000002, CHCR 00000002
   3 words: 57, 0 wrong, guards kept, MADR moved 0, BCR 00000003, CHCR 00000002
   4 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000004, CHCR 00000002
   5 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000005, CHCR 00000002
   6 words: 55, 0 wrong, guards kept, MADR moved 0, BCR 00000006, CHCR 00000002
   7 words: 56, 0 wrong, guards kept, MADR moved 0, BCR 00000007, CHCR 00000002
   8 words: 57, 0 wrong, guards kept, MADR moved 0, BCR 00000008, CHCR 00000002
   9 words: 58, 0 wrong, guards kept, MADR moved 0, BCR 00000009, CHCR 00000002
  10 words: 59, 0 wrong, guards kept, MADR moved 0, BCR 0000000A, CHCR 00000002
  11 words: 60, 0 wrong, guards kept, MADR moved 0, BCR 0000000B, CHCR 00000002
  12 words: 61, 0 wrong, guards kept, MADR moved 0, BCR 0000000C, CHCR 00000002
  13 words: 62, 0 wrong, guards kept, MADR moved 0, BCR 0000000D, CHCR 00000002
  14 words: 63, 0 wrong, guards kept, MADR moved 0, BCR 0000000E, CHCR 00000002
  15 words: 64, 0 wrong, guards kept, MADR moved 0, BCR 0000000F, CHCR 00000002
  16 words: 65, 0 wrong, guards kept, MADR moved 0, BCR 00000010, CHCR 00000002
  17 words: 66, 0 wrong, guards kept, MADR moved 0, BCR 00000011, CHCR 00000002
  18 words: 67, 0 wrong, guards kept, MADR moved 0, BCR 00000012, CHCR 00000002
  19 words: 68, 0 wrong, guards kept, MADR moved 0, BCR 00000013, CHCR 00000002
  20 words: 69, 0 wrong, guards kept, MADR moved 0, BCR 00000014, CHCR 00000002
  24 words: 73, 0 wrong, guards kept, MADR moved 0, BCR 00000018, CHCR 00000002
  31 words: 80, 0 wrong, guards kept, MADR moved 0, BCR 0000001F, CHCR 00000002
  32 words: 81, 0 wrong, guards kept, MADR moved 0, BCR 00000020, CHCR 00000002
  33 words: 82, 0 wrong, guards kept, MADR moved 0, BCR 00000021, CHCR 00000002
  63 words: 127, 0 wrong, guards kept, MADR moved 0, BCR 0000003F, CHCR 00000002
  64 words: 118, 0 wrong, guards kept, MADR moved 0, BCR 00000040, CHCR 00000002
  65 words: 119, 0 wrong, guards kept, MADR moved 0, BCR 00000041, CHCR 00000002
 127 words: 191, 0 wrong, guards kept, MADR moved 0, BCR 0000007F, CHCR 00000002
 128 words: 192, 0 wrong, guards kept, MADR moved 0, BCR 00000080, CHCR 00000002
 129 words: 183, 0 wrong, guards kept, MADR moved 0, BCR 00000081, CHCR 00000002
 255 words: 323, 0 wrong, guards kept, MADR moved 0, BCR 000000FF, CHCR 00000002
 256 words: 320, 0 wrong, guards kept, MADR moved 0, BCR 00000100, CHCR 00000002
 257 words: 321, 0 wrong, guards kept, MADR moved 0, BCR 00000101, CHCR 00000002
 511 words: 590, 0 wrong, guards kept, MADR moved 0, BCR 000001FF, CHCR 00000002
 512 words: 591, 0 wrong, guards kept, MADR moved 0, BCR 00000200, CHCR 00000002
 513 words: 592, 0 wrong, guards kept, MADR moved 0, BCR 00000201, CHCR 00000002
1023 words: 1132, 0 wrong, guards kept, MADR moved 0, BCR 000003FF, CHCR 00000002
1024 words: 1143, 0 wrong, guards kept, MADR moved 0, BCR 00000400, CHCR 00000002
1025 words: 1134, 0 wrong, guards kept, MADR moved 0, BCR 00000401, CHCR 00000002
2047 words: 2226, 0 wrong, guards kept, MADR moved 0, BCR 000007FF, CHCR 00000002
2048 words: 2223, 0 wrong, guards kept, MADR moved 0, BCR 00000800, CHCR 00000002
2049 words: 2228, 0 wrong, guards kept, MADR moved 0, BCR 00000801, CHCR 00000002
4095 words: 4394, 0 wrong, guards kept, MADR moved 0, BCR 00000FFF, CHCR 00000002
4096 words: 4391, 0 wrong, guards kept, MADR moved 0, BCR 00001000, CHCR 00000002
Odd settings, 4 words from word 20 (AAAAAAh where nothing was written):
MADR+1: MADR read 001147C1, 54, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR+2: MADR read 001147C2, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR+3: MADR read 001147C3, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR with FFh in bits 24-31: MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
BCR 00010004h: MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000000h (bit 1 clear): MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000003h (bit 0 set): MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000102h (chopping bit): MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 51000002h (bit 30): MADR read 001147C0, 76, CHCR 40000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000202h (SyncMode 1 bits): MADR read 001147C0, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 1147B4 1147B8 1147BC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 01000002h (no trigger): MADR read 001147C0, timeout, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Done.

03DIC.txt:

===== 03 DIC D2 DICR CHANNELS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
DICR written as shown (flags cleared), one transfer of each kind, then DICR and
I_STAT bit 3 (channels.txt:112-130). Per kind: DICR 0, the channel's enable bit
16+n alone, with bit 23, and bit 23 alone. Clocks between.
OTC (channel 6): 00000000 -> 158 00000000/0 00400000 -> 105 40400000/0
  00C00000 -> 105 C0C00000/1 00800000 -> 105 00800000/0
GPU write (channel 2): 00000000 -> 146 00000000/0 00040000 -> 146 04040000/0
  00840000 -> 147 84840000/1 00800000 -> 146 00800000/0
SPU write (channel 4): 00000000 -> 3806 00000000/0 00100000 -> 3530 10100000/0
  00900000 -> 3517 90900000/1 00800000 -> 3523 00800000/0
MDEC0 table (channel 0): 00000000 -> 52 00000000/0 00010000 -> 52 01010000/0
  00810000 -> 52 81810000/1 00800000 -> 55 00800000/0
MDEC1 block (channel 1): 00000000 -> 1381 00000000/0 00020000 -> 1381 02020000/0
  00820000 -> 1381 82820000/1 00800000 -> 1381 00800000/0
A transfer stopped by writing CHCR bit 24 = 0 part way, enable and bit 23 set:
SPU write of 1024 words stopped at 3000: MADR moved 192, BCR 003D0010 (003D0010 5000 later), CHCR 00000201, DICR 00900000, IRQ3 0
  started again with the same CHCR: 69152, MADR moved 4096, BCR 00000010, DICR 90900000
GPU write of 1024 words stopped at 1000: MADR moved 2368, BCR 001B0010 (001B0010 5000 later), CHCR 00000201, DICR 00840000, IRQ3 0
  started again with the same CHCR: 778, MADR moved 4096, BCR 00000010, DICR 84840000
Bit 15 forced twice, with I_STAT bit 3 acknowledged between; then 0 and again:
 first IRQ3 0, second (bit 15 still set) 1, after 0 then 8000h 0, DICR 80008000
A flag set with bit 23 off (OTC, enable bit 22 alone), then bit 23 written on:
 after the OTC 40400000; bit 23 on C0C00000, IRQ3 1; flag written 1 00C00000
Flag written 0 keeps it? OTC with 22 and 23, then DICR written 00C00000h:
 after the OTC C0C00000; 00C00000h written C0C00000; bit 23 off 40400000
Done.

04DCI.txt:

===== 04 DCI D2 IRQ LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Clocks from the CHCR write to CHCR bit 24 clear, to the DICR flag, and to I_STAT
bit 3, with the channel's enable and bit 23 set (FINDINGS "DICR latency"). The
poll takes three reads a turn; the I_STAT-only rows poll one register. Three each.
OTC 16: bit 24 clear 79, flag 79, I_STAT 79
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 94
GPU write 16: bit 24 clear 80, flag 80, I_STAT 80
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 109
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3556, flag 3556, I_STAT 3336
SPU write 16, I_STAT only: I_STAT 212
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 1327, flag 1327, I_STAT 1327
MDEC1 block 16, I_STAT only: I_STAT 1387
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 94
GPU write 16: bit 24 clear 78, flag 78, I_STAT 78
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 109
SPU write 16: bit 24 clear 183, flag 183, I_STAT 183
SPU write 64: bit 24 clear 3544, flag 3544, I_STAT 3324
SPU write 16, I_STAT only: I_STAT 212
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 1324, flag 1324, I_STAT 1324
MDEC1 block 16, I_STAT only: I_STAT 1397
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 94
GPU write 16: bit 24 clear 83, flag 83, I_STAT 83
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 105
SPU write 16: bit 24 clear 186, flag 186, I_STAT 186
SPU write 64: bit 24 clear 3544, flag 3544, I_STAT 3324
SPU write 16, I_STAT only: I_STAT 212
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 1324, flag 1324, I_STAT 1324
MDEC1 block 16, I_STAT only: I_STAT 1397
Done.

05DPR.txt:

===== 05 DPR D2 THREE PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
OTC of 1024 words, GPU VRAM read of 512 words (16 x 32) and SPU read of 512 words
(16 x 32), all three armed with their DPCR enables off, then one DPCR write with the
priorities shown (channels.txt:89-110: 0 highest; ties go to the higher channel).
Clocks (timer / 8, times 8) from the DPCR write until each channel's bit 24 clears.
Priority OTC 0 GPU 1 SPU 2: done OTC 1384, GPU read 2400, SPU read 36944 (344 polls)
Priority OTC 0 GPU 2 SPU 1: done OTC 1320, GPU read 2408, SPU read 36696 (342 polls)
Priority OTC 1 GPU 0 SPU 2: done OTC 1368, GPU read 2424, SPU read 37192 (346 polls)
Priority OTC 1 GPU 2 SPU 0: done OTC 1472, GPU read 2568, SPU read 36104 (334 polls)
Priority OTC 2 GPU 0 SPU 1: done OTC 1520, GPU read 2304, SPU read 36104 (334 polls)
Priority OTC 2 GPU 1 SPU 0: done OTC 1504, GPU read 2288, SPU read 36104 (334 polls)
Priority OTC 3 GPU 3 SPU 3: done OTC 1280, GPU read 2368, SPU read 37200 (346 polls)
Priority OTC 7 GPU 0 SPU 0: done OTC 256, GPU read 2288, SPU read 35944 (334 polls)
Priority OTC 0 GPU 7 SPU 7: done OTC 1280, GPU read 2480, SPU read 37232 (347 polls)
Priority OTC 7 GPU 7 SPU 0: done OTC 1280, GPU read 2384, SPU read 36096 (334 polls)
Done.

27 September 2026 card-g3

Raw output: 00RUN.txt · 01DRM.txt · 02DOT.txt · 03DIC.txt · 04DCI.txt · 05DPR.txt

00RUN.txt:

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
10 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 8001BEE8 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8001CA54 PRId 00000002

01DRM.txt:

===== 01 DRM D2 REGISTER BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Each register written one bit at a time and read back, each channel with its DPCR
enable off (channels.txt:18-87). CHCR is written 0 before any enable comes back.
Channel 0:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 1:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 2:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 3:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 4:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 5:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 6:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR bit 0 written reads 00000002
  CHCR bit 2 written reads 00000002
  CHCR keeps 51000002; FFFFFFFFh reads 51000002; 0 reads 00000002
DPCR one bit at a time (every CHCR 0):
  keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF
DICR bits 0-23 one at a time, with I_STAT bit 3 after each (bit 15 forces it):
  0:00000001/0  1:00000002/0  2:00000004/0  3:00000008/0
  4:00000010/0  5:00000020/0  6:00000000/0  7:00000000/0
  8:00000000/0  9:00000000/0 10:00000000/0 11:00000000/0
 12:00000000/0 13:00000000/0 14:00000000/0 15:80008000/1
 16:00010000/0 17:00020000/0 18:00040000/0 19:00080000/0
 20:00100000/0 21:00200000/0 22:00400000/0 23:00800000/0
DICR 80000000h (bit 31 written) reads 00000000
DICR 7F000000h (every flag written 1, none set) reads 00000000
Done.

02DOT.txt:

===== 02 DOT D2 OTC LENGTHS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
OTC (CHCR 11000002h) of n words: clocks from the CHCR write to bit 24 clear, every
entry checked (the first FFFFFFh, the rest the address below, channels.txt:143-151),
a guard word on each side, MADR, BCR and CHCR after.
   1 words: 85, 0 wrong, guards kept, MADR moved 0, BCR 00000001, CHCR 00000002
   2 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000002, CHCR 00000002
   3 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000003, CHCR 00000002
   4 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000004, CHCR 00000002
   5 words: 54, 0 wrong, guards kept, MADR moved 0, BCR 00000005, CHCR 00000002
   6 words: 55, 0 wrong, guards kept, MADR moved 0, BCR 00000006, CHCR 00000002
   7 words: 56, 0 wrong, guards kept, MADR moved 0, BCR 00000007, CHCR 00000002
   8 words: 57, 0 wrong, guards kept, MADR moved 0, BCR 00000008, CHCR 00000002
   9 words: 58, 0 wrong, guards kept, MADR moved 0, BCR 00000009, CHCR 00000002
  10 words: 59, 0 wrong, guards kept, MADR moved 0, BCR 0000000A, CHCR 00000002
  11 words: 60, 0 wrong, guards kept, MADR moved 0, BCR 0000000B, CHCR 00000002
  12 words: 61, 0 wrong, guards kept, MADR moved 0, BCR 0000000C, CHCR 00000002
  13 words: 66, 0 wrong, guards kept, MADR moved 0, BCR 0000000D, CHCR 00000002
  14 words: 63, 0 wrong, guards kept, MADR moved 0, BCR 0000000E, CHCR 00000002
  15 words: 64, 0 wrong, guards kept, MADR moved 0, BCR 0000000F, CHCR 00000002
  16 words: 65, 0 wrong, guards kept, MADR moved 0, BCR 00000010, CHCR 00000002
  17 words: 70, 0 wrong, guards kept, MADR moved 0, BCR 00000011, CHCR 00000002
  18 words: 67, 0 wrong, guards kept, MADR moved 0, BCR 00000012, CHCR 00000002
  19 words: 68, 0 wrong, guards kept, MADR moved 0, BCR 00000013, CHCR 00000002
  20 words: 69, 0 wrong, guards kept, MADR moved 0, BCR 00000014, CHCR 00000002
  24 words: 73, 0 wrong, guards kept, MADR moved 0, BCR 00000018, CHCR 00000002
  31 words: 80, 0 wrong, guards kept, MADR moved 0, BCR 0000001F, CHCR 00000002
  32 words: 91, 0 wrong, guards kept, MADR moved 0, BCR 00000020, CHCR 00000002
  33 words: 92, 0 wrong, guards kept, MADR moved 0, BCR 00000021, CHCR 00000002
  63 words: 117, 0 wrong, guards kept, MADR moved 0, BCR 0000003F, CHCR 00000002
  64 words: 118, 0 wrong, guards kept, MADR moved 0, BCR 00000040, CHCR 00000002
  65 words: 119, 0 wrong, guards kept, MADR moved 0, BCR 00000041, CHCR 00000002
 127 words: 191, 0 wrong, guards kept, MADR moved 0, BCR 0000007F, CHCR 00000002
 128 words: 182, 0 wrong, guards kept, MADR moved 0, BCR 00000080, CHCR 00000002
 129 words: 193, 0 wrong, guards kept, MADR moved 0, BCR 00000081, CHCR 00000002
 255 words: 319, 0 wrong, guards kept, MADR moved 0, BCR 000000FF, CHCR 00000002
 256 words: 320, 0 wrong, guards kept, MADR moved 0, BCR 00000100, CHCR 00000002
 257 words: 321, 0 wrong, guards kept, MADR moved 0, BCR 00000101, CHCR 00000002
 511 words: 590, 0 wrong, guards kept, MADR moved 0, BCR 000001FF, CHCR 00000002
 512 words: 591, 0 wrong, guards kept, MADR moved 0, BCR 00000200, CHCR 00000002
 513 words: 602, 0 wrong, guards kept, MADR moved 0, BCR 00000201, CHCR 00000002
1023 words: 1132, 0 wrong, guards kept, MADR moved 0, BCR 000003FF, CHCR 00000002
1024 words: 1143, 0 wrong, guards kept, MADR moved 0, BCR 00000400, CHCR 00000002
1025 words: 1134, 0 wrong, guards kept, MADR moved 0, BCR 00000401, CHCR 00000002
2047 words: 2216, 0 wrong, guards kept, MADR moved 0, BCR 000007FF, CHCR 00000002
2048 words: 2217, 0 wrong, guards kept, MADR moved 0, BCR 00000800, CHCR 00000002
2049 words: 2228, 0 wrong, guards kept, MADR moved 0, BCR 00000801, CHCR 00000002
4095 words: 4394, 0 wrong, guards kept, MADR moved 0, BCR 00000FFF, CHCR 00000002
4096 words: 4395, 0 wrong, guards kept, MADR moved 0, BCR 00001000, CHCR 00000002
Odd settings, 4 words from word 20 (AAAAAAh where nothing was written):
MADR+1: MADR read 00114789, 54, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR+2: MADR read 0011478A, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR+3: MADR read 0011478B, 77, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MADR with FFh in bits 24-31: MADR read 00114788, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
BCR 00010004h: MADR read 00114788, 82, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000000h (bit 1 clear): MADR read 00114788, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000003h (bit 0 set): MADR read 00114788, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000102h (chopping bit): MADR read 00114788, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 51000002h (bit 30): MADR read 00114788, 76, CHCR 40000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 11000202h (SyncMode 1 bits): MADR read 00114788, 76, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA FFFFFF 11477C 114780 114784 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
CHCR 01000002h (no trigger): MADR read 00114788, timeout, CHCR 00000002, words 14-25: AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Done.

03DIC.txt:

===== 03 DIC D2 DICR CHANNELS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DICR written as shown (flags cleared), one transfer of each kind, then DICR and
I_STAT bit 3 (channels.txt:112-130). Per kind: DICR 0, the channel's enable bit
16+n alone, with bit 23, and bit 23 alone. Clocks between.
OTC (channel 6): 00000000 -> 153 00000000/0 00400000 -> 105 40400000/0
  00C00000 -> 105 C0C00000/1 00800000 -> 105 00800000/0
GPU write (channel 2): 00000000 -> 155 00000000/0 00040000 -> 146 04040000/0
  00840000 -> 146 84840000/1 00800000 -> 155 00800000/0
SPU write (channel 4): 00000000 -> 3805 00000000/0 00100000 -> 3512 10100000/0
  00900000 -> 3499 90900000/1 00800000 -> 3504 00800000/0
MDEC0 table (channel 0): 00000000 -> 52 00000000/0 00010000 -> 52 01010000/0
  00810000 -> 52 81810000/1 00800000 -> 52 00800000/0
MDEC1 block (channel 1): 00000000 -> 870 00000000/0 00020000 -> 870 02020000/0
  00820000 -> 870 82820000/1 00800000 -> 870 00800000/0
A transfer stopped by writing CHCR bit 24 = 0 part way, enable and bit 23 set:
SPU write of 1024 words stopped at 3000: MADR moved 192, BCR 003D0010 (003D0010 5000 later), CHCR 00000201, DICR 00900000, IRQ3 0
  started again with the same CHCR: 69458, MADR moved 4096, BCR 00000010, DICR 90900000
GPU write of 1024 words stopped at 1000: MADR moved 2432, BCR 001A0010 (001A0010 5000 later), CHCR 00000201, DICR 00840000, IRQ3 0
  started again with the same CHCR: 752, MADR moved 4096, BCR 00000010, DICR 84840000
Bit 15 forced twice, with I_STAT bit 3 acknowledged between; then 0 and again:
 first IRQ3 0, second (bit 15 still set) 1, after 0 then 8000h 0, DICR 80008000
A flag set with bit 23 off (OTC, enable bit 22 alone), then bit 23 written on:
 after the OTC 40400000; bit 23 on C0C00000, IRQ3 1; flag written 1 00C00000
Flag written 0 keeps it? OTC with 22 and 23, then DICR written 00C00000h:
 after the OTC C0C00000; 00C00000h written C0C00000; bit 23 off 40400000
Done.

04DCI.txt:

===== 04 DCI D2 IRQ LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Clocks from the CHCR write to CHCR bit 24 clear, to the DICR flag, and to I_STAT
bit 3, with the channel's enable and bit 23 set (FINDINGS "DICR latency"). The
poll takes three reads a turn; the I_STAT-only rows poll one register. Three each.
OTC 16: bit 24 clear 79, flag 79, I_STAT 79
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 99
GPU write 16: bit 24 clear 78, flag 78, I_STAT 78
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3539, flag 3539, I_STAT 3319
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 837, flag 837, I_STAT 837
MDEC1 block 16, I_STAT only: I_STAT 876
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 99
GPU write 16: bit 24 clear 80, flag 80, I_STAT 80
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3541, flag 3541, I_STAT 3321
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 833, flag 833, I_STAT 833
MDEC1 block 16, I_STAT only: I_STAT 876
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 96
GPU write 16: bit 24 clear 78, flag 78, I_STAT 78
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3541, flag 3541, I_STAT 3321
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 833, flag 833, I_STAT 833
MDEC1 block 16, I_STAT only: I_STAT 876
Done.

05DPR.txt:

===== 05 DPR D2 THREE PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
OTC of 1024 words, GPU VRAM read of 512 words (16 x 32) and SPU read of 512 words
(16 x 32), all three armed with their DPCR enables off, then one DPCR write with the
priorities shown (channels.txt:89-110: 0 highest; ties go to the higher channel).
Clocks (timer / 8, times 8) from the DPCR write until each channel's bit 24 clears.
Priority OTC 0 GPU 1 SPU 2: done OTC 1376, GPU read 2400, SPU read 36944 (342 polls)
Priority OTC 0 GPU 2 SPU 1: done OTC 1328, GPU read 2448, SPU read 36872 (340 polls)
Priority OTC 1 GPU 0 SPU 2: done OTC 1368, GPU read 2432, SPU read 37000 (343 polls)
Priority OTC 1 GPU 2 SPU 0: done OTC 1480, GPU read 2568, SPU read 35912 (331 polls)
Priority OTC 2 GPU 0 SPU 1: done OTC 1528, GPU read 2288, SPU read 35920 (331 polls)
Priority OTC 2 GPU 1 SPU 0: done OTC 1480, GPU read 2280, SPU read 36096 (332 polls)
Priority OTC 3 GPU 3 SPU 3: done OTC 1280, GPU read 2384, SPU read 37040 (344 polls)
Priority OTC 7 GPU 0 SPU 0: done OTC 256, GPU read 2328, SPU read 36272 (335 polls)
Priority OTC 0 GPU 7 SPU 7: done OTC 1280, GPU read 2368, SPU read 37048 (344 polls)
Priority OTC 7 GPU 7 SPU 0: done OTC 1280, GPU read 2392, SPU read 36088 (332 polls)
Done.

References

  1. ^ a b SCPH-5501 output: dma2_safe/02DOT.txt.

  2. ^ Run 20260927T0000Z-5501a-card-g3: dma2_safe/01DRM.txt.

  3. ^ a b Run 20260927T0000Z-5501a-card-g3: dma2_safe/02DOT.txt.

  4. ^ a b c Run 20260927T0000Z-5501a-card-g3: dma2_safe/03DIC.txt.

  5. ^ Run 20260927T0000Z-5501a-card-g3: dma2_safe/04DCI.txt.

  6. ^ Run 20260927T0000Z-5501a-card-g3: dma2_safe/05DPR.txt.

Categories: Hardware tests