DMA Timing: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The groups that can hang the console run last, each in a separate program image, so that a hang loses only that row. The variants dmatime_drq1 to drq10, odd1 to odd4, pio1 to pio5 and unk1 to unk3 each hold one such row.[^run] | The groups that can hang the console run last, each in a separate program image, so that a hang loses only that row. The variants dmatime_drq1 to drq10, odd1 to odd4, pio1 to pio5 and unk1 to unk3 each hold one such row.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | |||
| ## Results | ## Results | ||