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---
title: DMA Timing
type: test
summary: Measures DMA register behavior, transfer times, chopping, priorities and DICR interrupts.
category: Hardware tests
info: Machine = SCPH-5501
info: Program = dmatime
---

## Overview

The program measures the [DMA controller](/hardware/dma/) beyond what the register descriptions give: register read-back, transfer times for each device, the CPU's share of the bus while a transfer runs, chopping, channel priority and the DICR interrupt flags. Each group writes its results to its own file.[^run]

Times are counted on root counter 2, which counts system clock cycles. A time runs from the CHCR write that starts a channel to the first poll that sees CHCR bit 24 clear, so every figure includes a fixed overhead for the write and the poll. A CHCR write that starts no transfer reads 68 clocks on the card-h run. Rows that could exceed 131071 clocks use root counter 2 on system clock / 8 and are given here in system clocks.[^run][^h-dot]

The groups that can hang the console run last, each in a separate program image, so that a hang loses only that row. The variants dmatime_drq1 to drq10, odd1 to odd4, pio1 to pio5 and unk1 to unk3 each hold one such row.[^run]

See also:

- [Bus Access and Device Register Timing](/tests/bus-access-register-timing/)

## Results

### Register Read-back

With each channel's DPCR enable off, MADR keeps 24 bits: FFFFFFFFh reads 00FFFFFFh. BCR keeps all 32 bits. CHCR on channels 0 to 5 keeps the bits 71770703h, and the same register reads back at offset +Ch. A halfword or byte store to BCR or CHCR writes only its own lanes: halfword 1234h at +2 reads 12340000h.[^h-drb]

Channel 6 CHCR keeps only bits 30, 28 and 24 of a write, and bit 1 always reads 1, so FFFFFFFFh reads 51000002h. DPCR keeps every bit. DICR keeps bits 0 to 5 and bits 15 to 23. Bit 31 cannot be written, and writing bit 15 sets bit 31 at once.[^h-drb]

1F8010F8h read 7FE7581Ah and 1F8010FCh read 00FFFFFFh. Writing 0 or FFFFFFFFh to either changes nothing. 1F8010F8h does change between transfers: it read 7FE31AA3h after an OTC and 7FE70AA3h after an SPU read, and it changed during an SPU write.[^c-dun]

### OTC (Channel 6)

An OTC transfer takes about one system clock a word plus the overhead, and about 1.06 clocks a word for long tables. BCR 0 clears 65536 words, which took the same time as 65535. MADR and BCR keep their start values after the transfer, and the CPU polled once during each.[^h-dot]

Table: OTC transfer time on the card-h run

| Words | System clocks |
| --- | --- |
| 1 | 89 |
| 16 | 109 to 119 |
| 64 | 157 |
| 256 | 359 |
| 1024 | 1172 |
| 4096 | 4429 to 4434 |
| 16384 | 17461 to 17468 |
| 65535 | 69585 to 69601 |
| 65536 | 69586 to 69601 |

CHCR bit 30 changes nothing in the time, and it stays set after the transfer. The upper half of BCR is ignored in SyncMode 0.[^h-dot]

An OTC that counts down past address 0 stops at the wrap. Three words from address 4 wrote 0 at address 4 and 00FFFFFCh at address 0, and left the word at 1FFFFCh unchanged.[^h-drq10]

### GPU (Channel 2)

A GPU list costs about 10 clocks for each empty node. The CPU runs between nodes: a list of 2048 empty nodes took 21040 clocks and the CPU polled 1064 times during it. Each GP0 word in a node adds about 1.07 clocks, so 16 nodes of 255 words took 4612 to 4628 clocks.[^h-dgl]

A list ended by FFFFFFh ends without an error. A list ended by FFFFFEh or 800000h sets DICR bit 15 and with it bit 31 and IRQ3, and MADR is left holding the end value.[^h-drq789]

A 2048-word block write to VRAM in SyncMode 0 takes 2247 clocks. SyncMode 1 in blocks of 16 words takes 512 to 517 clocks for 16 blocks and 7126 to 7153 for 256 blocks, and smaller blocks cost more: 256 blocks of 1 word took 2978 clocks. Reads from VRAM are slower than writes in SyncMode 1. A read of 64 blocks of 16 words took 2235 clocks against 1855 for the write.[^h-dgb]

With GP1(04h) set to 0 the GPU does not request data, and a SyncMode 0 or 1 transfer stays busy until GP1(04h)=2 is written. With CHCR bit 28 set, a SyncMode 0 transfer runs to the end even with the request off.[^h-drq123]

### SPU (Channel 4)

SPU transfers are much slower than GPU transfers. A SyncMode 0 write of 256 words took 2141 clocks, which is about 8 clocks a word. In SyncMode 1 the first block of 16 words took 217 to 221 clocks and each further block about 1160, so 64 blocks took about 73070 clocks. Reads take about the same time as writes. Changing the SPU delay register between 200931E1h, 220931E1h, 220931F1h and 22093141h moved the 16-block time by less than 1000 clocks.[^h-dsp]

64 words were written to sound RAM and read back. After SyncMode 1 transfers 56 words matched, and after SyncMode 0 transfers 16 matched.[^h-dsp]

With the SPU transfer mode set to stop, a SyncMode 0 or 1 transfer stays busy until the mode is set to DMA write. With CHCR bit 28 it runs to the end.[^h-drq456] During a SyncMode 1 SPU write, MADR advances and BCR counts down one block at a time, and the CPU polls between blocks.[^h-dmw]

### CPU During a Transfer

A loop running from the instruction cache keeps running during an OTC burst. A loop of registers alone or of scratchpad loads finished in the time of the loop or of the transfer, whichever was longer: 4000 turns took 17402 clocks with an OTC of 16384 words, and 10000 turns took 40019 with and without it. The timer read at the end waits for the transfer.[^h-dcp]

Loops that use the bus wait for the transfer. 1000 turns of RAM stores took 21390 clocks with the OTC against 4019 alone, and RAM loads and CHCR loads added the full transfer time. During a SyncMode 1 SPU write, register loops ran at full speed and RAM loads ran about 15 percent slower.[^h-dcp]

### Chopping

Chopping a 2048-word GPU block write in SyncMode 0 lets the CPU run between pieces of the transfer. MADR advances and BCR counts down while it runs, and they end at the last address and 0. The time depends on both windows.[^h-dch]

Table: 2048-word GPU write with chopping in system clocks (CPU polls)

| DMA window (words) | CPU window 1 clock | 4 clocks | 16 clocks | 32 clocks | 128 clocks |
| --- | --- | --- | --- | --- | --- |
| 1 | 16720 (1040) | 23376 (1548) | 47888 (3412) | 80680 (6141) | 276648 (20471) |
| 2 | 9440 (513) | 13400 (1023) | 24640 (1706) | 41000 (3069) | 139208 (10231) |
| 4 | 5864 (266) | 7352 (511) | 13472 (1022) | 21856 (1533) | 70704 (5111) |
| 16 | 3136 (127) | 3504 (127) | 5032 (254) | 7088 (381) | 19280 (1271) |
| 128 | 2352 (15) | 2408 (15) | 2576 (30) | 2792 (45) | 4240 (151) |

The same write without chopping takes 2247 clocks with one poll. A 256-word SPU write chopped at 16 words and 64 clocks took 3206 clocks against 2138 unchopped.[^h-dch]

### Priority

Two channels were armed with their DPCR enables off and then started by one DPCR write, both writing the same 64 words. In SyncMode 0 the channel with the higher priority (the lower number) ran first and the other channel's data was left in memory. At equal priority, channel 6 ran before channel 4 and before channel 2.[^h-dpr] DPCR bits 28 to 30 made no difference to an SPU write or to a CPU loop running beside it.[^h-dpr]

### DICR Interrupts

A channel's flag is set at the end of its transfer when its enable bit (16+n) is set, whether or not bit 23 is set. Bit 31 and IRQ3 follow only when bit 23 is set as well. Writing 1 to a flag clears it.[^h-dic]

Table: DICR around a 16-word OTC on the card-h run

| DICR written | DICR after the OTC | IRQ3 |
| --- | --- | --- |
| 00000000h | 00000000h | 0 |
| 00400000h | 40400000h | 0 |
| 00800000h | 00800000h | 0 |
| 00C00000h | C0C00000h | 1 |
| 00FF0000h | C0FF0000h | 1 |
| 00008000h | 80008000h | 0 |
| 0000003Fh | 0000003Fh | 0 |

IRQ3 is raised when bit 31 changes from 0 to 1. A flag set while bit 23 was off raised IRQ3 as soon as bit 23 was written, and a second flag while bit 31 was already set raised nothing.[^h-dic]

### CHCR Bits 8 29 and 30

Bit 30 stays set in CHCR after a transfer. A 16-block GPU write took 476 to 480 clocks with it against 494 without, and a 16-block SPU write 17355 against 17700. Bit 8 in a list transfer changes nothing. A forced SyncMode 0 burst with bit 29 set runs to the end, and CHCR reads 30000001h after it.[^h-odd]

Bit 8 in SyncMode 1 runs last because it may stop the DMA. On the card-b run the log ends at that row with no result.[^b-dod]

### Expansion Port (Channel 5)

DMA5 from the expansion port at 1F000000h never ends in SyncMode 0 or 1 without bit 28: the channel was still busy after 20000 polls. With bit 28 it runs, at about 20 clocks a word: 1 word took 111 to 115 clocks and 64 words 1380 to 1388. With nothing in the port, every word read FFFFFFFFh.[^c-dpi]

### List End Timing

Short GPU lists ending FFFFFFh took 65 clocks for one empty node and 98 for four. Writing DICR 7F000000h before the transfer changed only the first sample of the first row. That sample read 75 clocks against 65.[^q-lsn]

## Runs

### 27 September 2026 card-b

Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/00RUN.txt) · [01DRB.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/01DRB.txt) · [02DOT.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/02DOT.txt) · [03DGL.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/03DGL.txt) · [04DGB.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/04DGB.txt) · [05DSP.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/05DSP.txt) · [06DMW.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/06DMW.txt) · [07DIC.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/07DIC.txt) · [08DCP.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/08DCP.txt) · [09DCH.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/09DCH.txt) · [10DPR.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/10DPR.txt) · [11DMD.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/11DMD.txt) · [12DRQ.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/12DRQ.txt) · [13DOD.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/13DOD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
15 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM 00000000
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80022438 PRId 00000002
```

01DRB.txt:

```
===== 01 DRB DMA READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA registers written and read back, each channel with its DPCR enable off.
1F8010F8h reads 3FEB1A1C, 1F8010FCh reads 00FFFFFF
Channel 0 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 0 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 0 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 0 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 1 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 1 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 1 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 1 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 2 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 2 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 2 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 2 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 3 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 3 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 3 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 3 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 4 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 4 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 4 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 4 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 5 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 5 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 5 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 5 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 6 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 6 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 6 CHCR: FFFFFFFF reads 51000002, 8E88F8FC reads 00000002, 60770703 reads 40000002 (at +Ch 40000002)
Channel 6 CHCR: 10000000 reads 10000002, byte 07 at +2 reads 00000002, 0 reads 00000002
DPCR was 33333B33. FFFFFFFF reads FFFFFFFF, 0 reads 00000000, 80000000 reads 80000000, 70000000 reads 70000000, byte 08 at +3 reads 08000000
DICR was 00000000. 0 reads 00000000, 7F reads 0000003F, 7F80 reads 00000000, FF0000 reads 00FF0000, 80000000 reads 00000000, IRQ3 0
DICR 8000 reads 80008000 with IRQ3 1; 0 reads 00000000; 8000 again IRQ3 0; 8000 while set IRQ3 1
DICR byte 80 at +2 reads 00800000, halfword 0080 at +2 reads 00800000
1F8010F8h reads 3FEB1A1C, 1F8010FCh reads 00FFFFFF, at +2 halfwords 3FEB 00FF
Done.
```

02DOT.txt:

```
===== 02 DOT DMA OTC TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA6 OTC, CHCR 11000002: system clocks from the CHCR write to the poll that sees bit 24 clear, four times each.
CHCR written 00000002, no transfer: 69, polls 0
OTC     1 words: 77 59 59 63 | polls 0, MADR start0, BCR 00000001, CHCR 00000002, table right
After the first OTC: 1F8010F8h 3FE32A5C, 1F8010FCh 00FFFFFF
OTC     2 words: 74 63 60 60 | polls 0, MADR start0, BCR 00000002, CHCR 00000002, table right
OTC     3 words: 75 64 61 61 | polls 0, MADR start0, BCR 00000003, CHCR 00000002, table right
OTC     4 words: 76 67 62 62 | polls 0, MADR start0, BCR 00000004, CHCR 00000002, table right
OTC     8 words: 80 70 66 66 | polls 0, MADR start0, BCR 00000008, CHCR 00000002, table right
OTC    15 words: 87 73 73 73 | polls 0, MADR start0, BCR 0000000F, CHCR 00000002, table right
OTC    16 words: 93 76 74 74 | polls 0, MADR start0, BCR 00000010, CHCR 00000002, table right
OTC    17 words: 89 75 75 85 | polls 0, MADR start0, BCR 00000011, CHCR 00000002, table right
OTC    32 words: 104 90 100 90 | polls 0, MADR start0, BCR 00000020, CHCR 00000002, table right
OTC    64 words: 146 132 132 132 | polls 0, MADR start0, BCR 00000040, CHCR 00000002, table right
OTC   128 words: 210 196 188 186 | polls 0, MADR start0, BCR 00000080, CHCR 00000002, table right
OTC   256 words: 345 329 329 329 | polls 0, MADR start0, BCR 00000100, CHCR 00000002, table right
OTC  1024 words: 1161 1147 1152 1152 | polls 0, MADR start0, BCR 00000400, CHCR 00000002, table right
OTC  4096 words: 4413 4404 4399 4401 | polls 0, MADR start0, BCR 00001000, CHCR 00000002, table right
OTC 16384 words: 17446 17437 17425 17438 | polls 0, MADR start0, BCR 00004000, CHCR 00000002, table right
OTC 65535 words: 69578 69566 69558 69567 | polls 0, MADR start0, BCR 0000FFFF, CHCR 00000002, table right
OTC 65536 words: 69585 69566 69562 69566 | polls 0, MADR start0, BCR 00000000, CHCR 00000002, table right
OTC 256 words, CHCR 51000002 (bit 30): 344 329 329 330 | CHCR after 40000002, table right
OTC BCR 00050010 (16 words, 5 in the upper half): 88 74 84 74 | BCR after 00050010, table right
After: 1F8010F8h 3FE32A5C, 1F8010FCh 00FFFFFF
Done.
```

03DGL.txt:

```
===== 03 DGL DMA GPU LISTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA2 linked lists, CHCR 01000401, GP1(04h)=2: clocks from the CHCR write to bit 24 clear, and the polls the CPU made meanwhile. BCR written 00050010 first.
List    1 nodes of   0 NOP words: 79 (0 polls) 66 (0 polls) 63 (0 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    2 nodes of   0 NOP words: 92 (1 polls) 74 (1 polls) 74 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of   0 NOP words: 112 (2 polls) 94 (2 polls) 94 (2 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   0 NOP words: 229 (8 polls) 218 (8 polls) 215 (8 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   64 nodes of   0 NOP words: 718 (32 polls) 709 (33 polls) 709 (33 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List  256 nodes of   0 NOP words: 2684 (132 polls) 2675 (133 polls) 2669 (132 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 1024 nodes of   0 NOP words: 10551 (532 polls) 10537 (532 polls) 10531 (531 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 2048 nodes of   0 NOP words: 21035 (1064 polls) 21023 (1065 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   1 NOP words: 320 (14 polls) 310 (15 polls) 304 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   2 NOP words: 339 (14 polls) 323 (15 polls) 326 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   4 NOP words: 368 (14 polls) 358 (15 polls) 352 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   8 NOP words: 432 (14 polls) 422 (15 polls) 422 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  15 NOP words: 563 (14 polls) 552 (15 polls) 552 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  16 NOP words: 571 (14 polls) 566 (15 polls) 564 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  32 NOP words: 849 (14 polls) 838 (15 polls) 832 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  64 NOP words: 1381 (14 polls) 1388 (15 polls) 1364 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 128 NOP words: 2475 (14 polls) 2468 (15 polls) 2458 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 255 NOP words: 4612 (14 polls) 4593 (15 polls) 4608 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    1 nodes of 255 NOP words: 352 (0 polls) 337 (0 polls) 332 (0 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of 255 NOP words: 1195 (2 polls) 1184 (3 polls) 1188 (3 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
Done.
```

04DGB.txt:

```
===== 04 DGB DMA GPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA2 blocks to and from VRAM at 512,256: clocks from the CHCR write to bit 24 clear, twice each; polls, MADR, BCR and CHCR after.
Write SyncMode 1, 16 words x 1: 88 74 | polls 0, MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 122 104 | polls 1, MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 165 164 | polls 3, MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 511 494 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 1853 1838 | polls 63, MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 256: 7142 7138 | polls 258, MADR start16384, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 256: 2976 2965 | polls 193, MADR start1024, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 128: 1721 1720 | polls 127, MADR start1024, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 64: 985 964 | polls 63, MADR start1024, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 32: 664 659 | polls 31, MADR start1024, BCR 00000008, CHCR 00000201
Write SyncMode 1, 32 words x 8: 419 458 | polls 11, MADR start1024, BCR 00000020, CHCR 00000201
Write SyncMode 0, 256 words: 342 328 | polls 0, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0, 2048 words: 2242 2228 | polls 0, MADR start0, BCR 00000800, CHCR 00000001
Write SyncMode 0 bit 28, 256 words: 342 328 | polls 0, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 1 bit 28, 16 words x 16: 508 497 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+2, 16 words x 4: 165 164 | polls 3, MADR start254, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+1, 16 words x 4: 174 155 | polls 3, MADR start255, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 1: 88 74 | polls 0, MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 560 543 | polls 19, MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 2242 2217 | polls 89, MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 64: 920 913 | polls 63, MADR start1024, BCR 00000004, CHCR 00000200
Read SyncMode 0, 256 words: 343 333 | polls 0, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 0 bit 28, 256 words: 343 329 | polls 0, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 1, MADR+2, 16 words x 4: 162 147 | polls 3, MADR start254, BCR 00000010, CHCR 00000200
Read back words 0-3: 7FFF0000 7FFF0001 7FFF0002 7FFF0003
Done.
```

05DSP.txt:

```
===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 220931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 202 (0) 192 (0) 191 (0) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1492 (89) 1470 (88) 1479 (89) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3842 (250) 3814 (249) 3833 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8545 (572) 8520 (571) 8537 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17789 (1202) 17772 (1202) 17772 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73068 (4970) 73068 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4080 (265) 4060 (264) 4071 (265) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4885 (331) 4864 (331) 4855 (330) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4490 (299) 4470 (299) 4477 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4280 (284) 4271 (284) 4472 (299) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 203 (0) 191 (0) 200 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3897 (255) 3894 (256) 3879 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17790 (1207) 17783 (1208) 17780 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73102 (5001) 73102 (5002) 73076 (5000) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4796 (324) 4777 (324) 4780 (324) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 206 (0) 190 (0) 192 (0) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 590 (0) 577 (0) 572 (0) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2125 (0) 2112 (0) 2114 (0) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 589 (0) 572 (0) 572 (0) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 629 (2) 624 (3) 635 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 605 (0) 584 (0) 589 (0) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3845 (250) 3828 (250) 3833 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17766 (1200) 17755 (1200) 17755 (1200) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17803 (1209) 17794 (1209) 17791 (1209) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17524 (1180) 17675 (1194) 17675 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16879 (1215) 16872 (1217) 16854 (1214) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17799 (1208) 17783 (1208) 17780 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.
```

06DMW.txt:

```
===== 06 DMW DMA MIDWAY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR, MADR, BCR and DICR polled while a transfer runs: a row each time one changes (t is timer 2's low 16 bits). DICR flags need bit 23 and bit 16+n (dmachannels.txt:184-186); bits 0-6 may give a flag per slice (dmachannels.txt:174-177).
SPU write 16 words x 8, CHCR 01000201, DICR 00000000:
  poll    t: CHCR MADR BCR DICR
      0   539: 01000201 0011A458 00070010 00000000
      3  1646: 01000201 0011A498 00060010 00000000
      6  2718: 01000201 0011A498 00050010 00000000
      7  3082: 01000201 0011A4D8 00050010 00000000
     10  4150: 01000201 0011A518 00040010 00000000
     13  5224: 01000201 0011A558 00030010 00000000
     16  6280: 01000201 0011A598 00020010 00000000
     19  7358: 01000201 0011A5D8 00010010 00000000
     23  8708: 00000201 0011A618 00000010 00000000
  done after 23 polls
SPU write 16 words x 8, CHCR 11000201 (bit 28):
  poll    t: CHCR MADR BCR DICR
      0   527: 01000201 0011A458 00070010 00000000
      4  1916: 01000201 0011A498 00060010 00000000
      7  2982: 01000201 0011A4D8 00050010 00000000
     10  4049: 01000201 0011A518 00040010 00000000
     13  5117: 01000201 0011A558 00030010 00000000
     17  6470: 01000201 0011A598 00020010 00000000
     20  7539: 01000201 0011A5D8 00010010 00000000
     24  8901: 00000201 0011A618 00000010 00000000
  done after 24 polls
SPU write 16 words x 8, DICR 00900000 (bit 23, bit 20):
  poll    t: CHCR MADR BCR DICR
      0   520: 01000201 0011A458 00070010 00900000
      3  1618: 01000201 0011A458 00060010 00900000
      4  1982: 01000201 0011A498 00060010 00900000
      6  2758: 01000201 0011A4D8 00050010 00900000
     10  4109: 01000201 0011A518 00040010 00900000
     13  5182: 01000201 0011A558 00030010 00900000
     17  6531: 01000201 0011A598 00020010 00900000
     20  7599: 01000201 0011A5D8 00010010 00900000
     23  8657: 00000201 0011A618 00000010 90900000
  done after 23 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010 (bit 4 too, a flag per slice?):
  poll    t: CHCR MADR BCR DICR
      0   523: 01000201 0011A458 00070010 90900010
      3  1621: 01000201 0011A458 00060010 90900010
      4  1983: 01000201 0011A498 00060010 90900010
      6  2766: 01000201 0011A4D8 00050010 90900010
     10  4122: 01000201 0011A518 00040010 90900010
     13  5184: 01000201 0011A558 00030010 90900010
     17  6538: 01000201 0011A598 00020010 90900010
     20  7603: 01000201 0011A5D8 00010010 90900010
     24  8953: 00000201 0011A618 00000010 90900010
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010, I_STAT bit 3 in the last column:
  poll    t: CHCR MADR BCR I_STAT&8
      0   525: 01000201 0011A458 00070010 00000008
      4  1910: 01000201 0011A498 00060010 00000008
      7  2984: 01000201 0011A4D8 00050010 00000008
     10  4040: 01000201 0011A518 00040010 00000008
     13  5118: 01000201 0011A558 00030010 00000008
     17  6467: 01000201 0011A598 00020010 00000008
     20  7542: 01000201 0011A5D8 00010010 00000008
     23  8613: 01000201 0011A618 00000010 00000008
     24  8979: 00000201 0011A618 00000010 00000008
  done after 24 polls
SPU read 16 words x 8, CHCR 01000200:
  poll    t: CHCR MADR BCR DICR
      0   526: 01000200 0011A458 00070010 00000000
      4  1911: 01000200 0011A498 00060010 00000000
      7  2979: 01000200 0011A4D8 00050010 00000000
     10  4050: 01000200 0011A518 00040010 00000000
     13  5117: 01000200 0011A558 00030010 00000000
     17  6481: 01000200 0011A598 00020010 00000000
     20  7540: 01000200 0011A5D8 00010010 00000000
     23  8620: 01000200 0011A618 00000010 00000000
     24  8987: 00000200 0011A618 00000010 00000000
  done after 24 polls
GPU write 16 words x 8 to VRAM, CHCR 01000201:
  poll    t: CHCR MADR BCR DICR
      0   545: 01000201 0015B618 00000010 00000000
      1   942: 00000201 0015B618 00000010 00000000
  done after 1 polls
GPU list 8 nodes of 15 NOPs, DICR 00840004 (bit 2, a flag per entry?):
  list at 116278, nodes 64 bytes apart
  poll    t: CHCR MADR BCR DICR
      0   591: 01000401 00FFFFFF 00000000 84840004
      1   986: 00000401 00FFFFFF 00000000 84840004
  done after 1 polls
Done.
```

07DIC.txt:

```
===== 07 DIC DMA DICR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DICR around a 16 word OTC (channel 6: enable bit 22, flag bit 30). psx-spx sets the flag only with bit 23 and bit 22 (dmachannels.txt:184-186), nocash with bit 22 alone (channels.txt:122-123). IRQ3 is I_STAT bit 3, acknowledged before each OTC.
DICR 00000000 reads 00000000 (IRQ3 0); after OTC 00000000, IRQ3 0
DICR 00400000 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00800000 reads 00800000 (IRQ3 0); after OTC 00800000, IRQ3 0
DICR 00C00000 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00C00040 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00400040 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00BF0000 reads 00BF0000 (IRQ3 0); after OTC 00BF0000, IRQ3 0
DICR 00FF0000 reads 00FF0000 (IRQ3 0); after OTC C0FF0000, IRQ3 1
DICR 00008000 reads 80008000 (IRQ3 1); after OTC 80008000, IRQ3 0
DICR 00C08000 reads 80C08000 (IRQ3 1); after OTC C0C08000, IRQ3 0
DICR 0000003F reads 0000003F (IRQ3 0); after OTC 0000003F, IRQ3 0
A flag, then its enables taken away:
  after OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  bit 22 off: wrote 00800000, reads C0800000, IRQ3 0
  bit 23 off too: wrote 00000000, reads 40000000, IRQ3 0
  bit 23 on: wrote 00800000, reads C0800000, IRQ3 1
  bit 23 on again: wrote 00800000, reads C0800000, IRQ3 0
  flag acknowledged: wrote 40800000, reads 00800000, IRQ3 0
  bit 31 written: wrote 80800000, reads 00800000, IRQ3 0
Flag with bit 22 alone, then bit 23:
  after OTC: wrote 00400000, reads 40400000, IRQ3 0
  bit 23 on: wrote 00C00000, reads C0C00000, IRQ3 1
Bit 15 set, then a flag:
  bit 15 and 22 and 23: wrote 00C08000, reads 80C08000, IRQ3 1
  after OTC: wrote 00C08000, reads C0C08000, IRQ3 0
  bit 15 off: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
Two flags, one acknowledged:
  after first OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  after second OTC: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
  after third OTC: wrote 00C00000, reads C0C00000, IRQ3 1
OTC with bit 28 alone (no start, otc.c) and DICR 00C00000:
  after: wrote 00C00000, reads 00C00000, IRQ3 0
Done.
```

08DCP.txt:

```
===== 08 DCP DMA CPU DURING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
A loop from the i-cache started right after the CHCR write that starts a transfer, then a timer 2 read: clocks alone and with the transfer. A loop turn is its body, addiu, bnez, nop.
OTC 16384 words (CHCR 11000002):
  registers n=1: alone 23, with the transfer 17403
  registers n=100: alone 419, with the transfer 17392
  registers n=1000: alone 4019, with the transfer 17407
  registers n=4000: alone 16019, with the transfer 17412
  registers n=10000: alone 40019, with the transfer 40019
  registers n=20000: alone 80019, with the transfer 80019
  scratchpad loads n=100: alone 419, with the transfer 17402
  scratchpad loads n=1000: alone 4019, with the transfer 17408
  scratchpad loads n=4000: alone 16019, with the transfer 17392
  scratchpad loads n=10000: alone 40019, with the transfer 40019
  scratchpad loads n=20000: alone 80019, with the transfer 80019
  RAM stores n=100: alone 421, with the transfer 17797
  RAM stores n=1000: alone 4022, with the transfer 21392
  RAM stores n=4000: alone 16020, with the transfer 33402
  RAM stores n=10000: alone 40020, with the transfer 57380
  RAM loads n=100: alone 935, with the transfer 18302
  RAM loads n=1000: alone 9163, with the transfer 26535
  RAM loads n=4000: alone 36586, with the transfer 53967
  RAM loads n=10000: alone 91445, with the transfer 108824
  CHCR loads n=100: alone 719, with the transfer 18095
  CHCR loads n=1000: alone 7019, with the transfer 24395
  CHCR loads n=4000: alone 28019, with the transfer 45395
  CHCR loads n=10000: alone 70019, with the transfer 87390
SPU write 16 words x 64 (CHCR 01000201):
  registers n=100: alone 419, with the transfer 419 (still busy after)
  registers n=1000: alone 4019, with the transfer 4019 (still busy after)
  registers n=4000: alone 16019, with the transfer 16019 (still busy after)
  registers n=10000: alone 40019, with the transfer 40019 (still busy after)
  RAM loads n=100: alone 930, with the transfer 1057 (still busy after)
  RAM loads n=1000: alone 9154, with the transfer 10463 (still busy after)
  RAM loads n=4000: alone 36586, with the transfer 41197 (still busy after)
  CHCR loads n=100: alone 719, with the transfer 850 (still busy after)
  CHCR loads n=1000: alone 7019, with the transfer 7951 (still busy after)
  CHCR loads n=4000: alone 28019, with the transfer 31753 (still busy after)
GPU write 2048 words SyncMode 0 chopped, DMA window 1 word, CPU window 128 clocks (CHCR 01700101):
  registers n=100: alone 424, with the transfer 448 (still busy after) (clock/8)
  registers n=1000: alone 4024, with the transfer 4040 (still busy after) (clock/8)
  registers n=4000: alone 16016, with the transfer 16040 (still busy after) (clock/8)
  registers n=10000: alone 40016, with the transfer 40032 (still busy after) (clock/8)
  RAM loads n=100: alone 936, with the transfer 960 (still busy after) (clock/8)
  RAM loads n=1000: alone 9160, with the transfer 9232 (still busy after) (clock/8)
  RAM loads n=4000: alone 36584, with the transfer 36776 (still busy after) (clock/8)
GPU write 2048 words SyncMode 0 not chopped (CHCR 01000001):
  registers n=100: alone 419, with the transfer 2199
  registers n=1000: alone 4019, with the transfer 4035
  registers n=4000: alone 16019, with the transfer 16035
  registers n=10000: alone 40019, with the transfer 40035
Done.
```

09DCH.txt:

```
===== 09 DCH DMA CHOP SHARE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
GPU write 2048 words SyncMode 0 chopped (CHCR 01xx0101), polling CHCR: clocks, polls (the CPU's share), MADR, BCR, CHCR after. Not chopped for scale first.
Not chopped: 2238, polls 0
DMA window   1 words, CPU window   1 clocks: 16704, polls 1040, MADR start8192, BCR 00000000, CHCR 00000101
DMA window   1 words, CPU window   4 clocks: 23368, polls 1547, MADR start8192, BCR 00000000, CHCR 00200101
DMA window   1 words, CPU window  16 clocks: 47880, polls 3411, MADR start8192, BCR 00000000, CHCR 00400101
DMA window   1 words, CPU window  32 clocks: 80688, polls 6140, MADR start8192, BCR 00000000, CHCR 00500101
DMA window   1 words, CPU window 128 clocks: 276640, polls 20470, MADR start8192, BCR 00000000, CHCR 00700101
DMA window   2 words, CPU window   1 clocks: 9432, polls 512, MADR start8192, BCR 00000000, CHCR 00010101
DMA window   2 words, CPU window   4 clocks: 13384, polls 1022, MADR start8192, BCR 00000000, CHCR 00210101
DMA window   2 words, CPU window  16 clocks: 24624, polls 1705, MADR start8192, BCR 00000000, CHCR 00410101
DMA window   2 words, CPU window  32 clocks: 40992, polls 3068, MADR start8192, BCR 00000000, CHCR 00510101
DMA window   2 words, CPU window 128 clocks: 139216, polls 10230, MADR start8192, BCR 00000000, CHCR 00710101
DMA window   4 words, CPU window   1 clocks: 5808, polls 268, MADR start8192, BCR 00000000, CHCR 00020101
DMA window   4 words, CPU window   4 clocks: 7344, polls 510, MADR start8192, BCR 00000000, CHCR 00220101
DMA window   4 words, CPU window  16 clocks: 13456, polls 1021, MADR start8192, BCR 00000000, CHCR 00420101
DMA window   4 words, CPU window  32 clocks: 21864, polls 1532, MADR start8192, BCR 00000000, CHCR 00520101
DMA window   4 words, CPU window 128 clocks: 70664, polls 5110, MADR start8192, BCR 00000000, CHCR 00720101
DMA window  16 words, CPU window   1 clocks: 3128, polls 126, MADR start8192, BCR 00000000, CHCR 00040101
DMA window  16 words, CPU window   4 clocks: 3472, polls 126, MADR start8192, BCR 00000000, CHCR 00240101
DMA window  16 words, CPU window  16 clocks: 5024, polls 253, MADR start8192, BCR 00000000, CHCR 00440101
DMA window  16 words, CPU window  32 clocks: 7064, polls 380, MADR start8192, BCR 00000000, CHCR 00540101
DMA window  16 words, CPU window 128 clocks: 19272, polls 1270, MADR start8192, BCR 00000000, CHCR 00740101
DMA window 128 words, CPU window   1 clocks: 2344, polls 14, MADR start8192, BCR 00000000, CHCR 00070101
DMA window 128 words, CPU window   4 clocks: 2384, polls 14, MADR start8192, BCR 00000000, CHCR 00270101
DMA window 128 words, CPU window  16 clocks: 2552, polls 29, MADR start8192, BCR 00000000, CHCR 00470101
DMA window 128 words, CPU window  32 clocks: 2792, polls 44, MADR start8192, BCR 00000000, CHCR 00570101
DMA window 128 words, CPU window 128 clocks: 4200, polls 150, MADR start8192, BCR 00000000, CHCR 00770101
Chopped 1 word / 128 clocks, as it runs:
  poll    t: CHCR MADR BCR GPUSTAT&1C000000
      0   420: 01700101 0015B41C 000007FF 10000000
      1   828: 01700101 0015B42C 000007FB 10000000
      2  1197: 01700101 0015B434 000007F8 10000000
      3  1573: 01700101 0015B440 000007F6 00000000
      4  1949: 01700101 0015B44C 000007F3 10000000
      5  2328: 01700101 0015B458 000007F0 10000000
      6  2705: 01700101 0015B460 000007ED 10000000
      7  3079: 01700101 0015B46C 000007EB 10000000
      8  3450: 01700101 0015B478 000007E8 10000000
      9  3820: 01700101 0015B484 000007E5 10000000
     10  4200: 01700101 0015B48C 000007E2 10000000
     11  4572: 01700101 0015B498 000007E0 00000000
     12  4948: 01700101 0015B4A4 000007DD 10000000
     13  5313: 01700101 0015B4B0 000007DA 10000000
     14  5692: 01700101 0015B4B8 000007D7 10000000
     15  6065: 01700101 0015B4C4 000007D5 00000000
     16  6440: 01700101 0015B4D0 000007D2 10000000
     17  6813: 01700101 0015B4DC 000007CF 10000000
     18  7189: 01700101 0015B4E4 000007CC 10000000
     19  7561: 01700101 0015B4F0 000007CA 00000000
  done after 947 polls (rows cut at 20)
SPU write 256 words SyncMode 0 chopped 16 words / 64 clocks (CHCR 01640101): 3206, polls 75, MADR start1024, BCR 00000000
SPU write 256 words SyncMode 0 not chopped: 2129, polls 0
Done.
```

10DPR.txt:

```
===== 10 DPR DMA PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Two channels armed with their DPCR enables off, then one DPCR write: which wrote each of 64 shared words last (O OTC, S SPU, G GPU, . untouched, ? other).
SPU read SyncMode 1, priority 1, OTC priority 5: 3912 clocks, 248 polls
  OOOOOOOOOOOOOOOOSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 5, OTC priority 1: 3909 clocks, 248 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 3, OTC priority 3: 3909 clocks, 248 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 1, OTC priority 5: 710 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
SPU read SyncMode 0, priority 5, OTC priority 1: 707 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 3, OTC priority 3: 709 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
GPU read SyncMode 1, priority 1, OTC priority 5: 260 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 1, priority 5, OTC priority 1: 260 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 1, priority 3, OTC priority 3: 270 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 0, priority 1, OTC priority 5: 248 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 0, priority 5, OTC priority 1: 258 clocks, 1 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
DPCR bits 28-30, CPU priority (channels.txt:105, dmachannels.txt:168):
DPCR 0B3B3B33, SPU write 16 words x 64: 73078, polls 4969; loop of 10000 alone 40026, with the SPU write 40019
DPCR 3B3B3B33, SPU write 16 words x 64: 73084, polls 4970; loop of 10000 alone 40026, with the SPU write 40019
DPCR 7B3B3B33, SPU write 16 words x 64: 73080, polls 4969; loop of 10000 alone 40026, with the SPU write 40019
Done.
```

11DMD.txt:

```
===== 11 DMD DMA MDEC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA0 and DMA1 with the MDEC: tables, then MDEC(1) on blocks of only a DC value (Q 1, DC 20h) and FE00h; DMA1 armed first. Clocks from the DMA0 start. Scale table zero.
Mono 8 bit, 1 block, out 16x1: quant 16 words 91, scale 32 words 90, decode: DMA0 done at 111, DMA1 done at 1007, 30 polls
  output sum 08080800, words 0 and last 80808080 80808080; MDEC status 8204FFFF
  DMA0 MADR start128 BCR 00000020 CHCR 00000201; DMA1 MADR start64 BCR 00000010 CHCR 00000200
Mono 8 bit, 4 blocks, out 16x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040010 CHCR 01000200
Mono 8 bit, 4 blocks, out 32x2: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00020020 CHCR 01000200
Mono 4 bit, 4 blocks, out 8x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999980, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004001E
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040008 CHCR 01000200
Colour 15 bit, 1 macroblock, out 32x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 66666600, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040020 CHCR 01000200
Colour 24 bit, 1 macroblock, out 32x6: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999900, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00060020 CHCR 01000200
Colour 15 bit, 2 macroblocks, out 32x8: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum CCCCCC00, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00080020 CHCR 01000200
Done.
```

12DRQ.txt:

```
===== 12 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off:
  GP1(04h)=0, CHCR 01000201 BCR 00040010: polled up to 20000 times, still busy; MADR start0 BCR 00040010 CHCR 01000201
  then GP1(04h)=2: done; MADR start256 BCR 00000010 CHCR 00000201
GPU SyncMode 0 with the GPU request off:
  GP1(04h)=0, CHCR 01000001 BCR 00000040: polled up to 20000 times, still busy; MADR start0 BCR 00000040 CHCR 01000001
  then GP1(04h)=2: done; MADR start0 BCR 00000040 CHCR 00000001
GPU SyncMode 0 bit 28 with the GPU request off:
  GP1(04h)=0, CHCR 11000001 BCR 00000040: polled up to 20000 times, done; MADR start0 BCR 00000040 CHCR 00000001
  then GP1(04h)=2: done; MADR start0 BCR 00000040 CHCR 00000001
SPU SyncMode 1 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 01000201: polled up to 20000 times, still busy; MADR start0 BCR 00040010 SPUSTAT 0000
  then mode DMA write: done; MADR start256 BCR 00000010 SPUSTAT 0020
SPU SyncMode 0 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 01000001: polled up to 20000 times, still busy; MADR start0 BCR 00000040 SPUSTAT 0000
  then mode DMA write: done; MADR start0 BCR 00000040 SPUSTAT 0020
SPU SyncMode 0 bit 28 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 11000001: polled up to 20000 times, done; MADR start0 BCR 00000040 SPUSTAT 0800
  then mode DMA write: done; MADR start0 BCR 00000040 SPUSTAT 0800
GPU list ended by FFFFFFh:
  list of 4 ending FFFFFF: 123, MADR 00FFFFFF, CHCR 00000401, DICR 00000000, IRQ3 0
  DICR with bit 15 written 0: 00000000
GPU list ended by FFFFFEh:
  list of 4 ending FFFFFE: 136, MADR 00FFFFFE, CHCR 00000401, DICR 80008000, IRQ3 1
  DICR with bit 15 written 0: 00000000
GPU list ended by 800000h:
  list of 4 ending 800000: 136, MADR 00800000, CHCR 00000401, DICR 80008000, IRQ3 1
  DICR with bit 15 written 0: 00000000
OTC of 3 words from address 4:
  word 4 00000000, word 0 00FFFFFC, word 1FFFFCh 22222222 (was 22222222); MADR 00000004 CHCR 00000002
Done.
```

13DOD.txt:

```
===== 13 DOD DMA ODD BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR bits 8, 29 and 30 where psx-spx leaves them open.
Bit 30:
  GPU write 16 x 16: CHCR 01000201 494, 41000201 476, CHCR after 40000201
  SPU write 16 x 16: CHCR 01000201 17700, 41000201 17355, CHCR after 40000201
Bits 28 and 29 in SyncMode 1:
  poll    t: CHCR MADR BCR DICR
      0  1480: 20000201 0011A618 00000010 00000000
  done after 0 polls
Bit 8 in a linked list:
  16 nodes of 1, CHCR 01000401: 317, 01000501: 310, MADR 00FFFFFF CHCR 00000501 GPUSTAT 5602220A
Bit 29 in a forced burst:
  GPU SyncMode 0, CHCR 31000001: polled up to 20000 times, done; MADR start0 BCR 00000100 CHCR 30000001
Bit 8 in SyncMode 1:
```

### 27 September 2026 card-c

Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-c/dmatime_rest/00RUN.txt) · [01DUN.txt](/tests/raw/20260927T0000Z-5501a-card-c/dmatime_rest/01DUN.txt) · [02DPI.txt](/tests/raw/20260927T0000Z-5501a-card-c/dmatime_rest/02DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
2 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80016C84 PRId 00000002
```

01DUN.txt:

```
===== 01 DUN DMA F8 FC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
1F8010F8h and 1F8010FCh, "might be remaining length and address?" (channels.txt:132-141): read at the start 7FE7581A 00FFFFFF, while an SPU write runs, after transfers, then written.
While SPU write 16 words x 16 runs:
  poll    t: CHCR F8 FC MADR
      0   549: 01000201 7FEB0A63 00FFFFFF 0011A190
      3  1652: 01000201 7FEB0A63 00FFFFFF 0011A1D0
      6  2725: 01000201 7FEB0A63 00FFFFFF 0011A210
     10  4079: 01000201 7FEB0A63 00FFFFFF 0011A250
     13  5157: 01000201 7FEB0A63 00FFFFFF 0011A290
     16  6227: 01000201 7FEB0A63 00FFFFFF 0011A2D0
     19  7290: 01000201 7FEB0A63 00FFFFFF 0011A310
     23  8641: 01000201 7FEB0A63 00FFFFFF 0011A350
     26  9708: 01000201 7FEB0A63 00FFFFFF 0011A390
     30 11070: 01000201 7FEB0A63 00FFFFFF 0011A3D0
     33 12140: 01000201 7FEB0A63 00FFFFFF 0011A410
     36 13201: 01000201 7FEB0A63 00FFFFFF 0011A450
     39 14273: 01000201 7FEB0A63 00FFFFFF 0011A490
     43 15624: 01000201 7FEB0A63 00FFFFFF 0011A4D0
     46 16696: 01000201 7FEB0A63 00FFFFFF 0011A510
     49 17763: 01000201 79EB0A63 00FFFFFF 0011A550
     50 18128: 00000201 7FEB0A63 00FFFFFF 0011A550
  done after 50 polls
After transfers:
  after an OTC: F8 7FE31AA3 FC 00FFFFFF
  after an SPU read: F8 7FE70AA3 FC 00FFFFFF
  after an OTC from MADR+2: F8 7FE31AA3 FC 00FFFFFF
Written:
  F8 was 7FE31AA3: 0 reads 7FE31AA3, FFFFFFFF reads 7FE31AA3; FC was 00FFFFFF: 0 reads 00FFFFFF, FFFFFFFF reads 00FFFFFF; now 7FE31AA3 00FFFFFF
Done.
```

02DPI.txt:

```
===== 02 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words:
  CHCR 01000200 BCR 00010004: busy after 20000 polls, 109016; MADR start0 BCR 00010004 CHCR 01000200; words 0-1 CCCCCCCC CCCCCCCC
SyncMode 0, 4 words, no bit 28:
  CHCR 01000000 BCR 00000004: busy after 20000 polls, 109015; MADR start0 BCR 00000004 CHCR 01000000; words 0-1 CCCCCCCC CCCCCCCC
SyncMode 0 bit 28, 1 word:
  CHCR 11000000 BCR 00000001: done at 115; MADR start0 BCR 00000001 CHCR 00000000; words 0-1 FFFFFFFF CCCCCCCC
SyncMode 0 bit 28, 16 words:
  CHCR 11000000 BCR 00000010: done at 412; MADR start0 BCR 00000010 CHCR 00000000; words 0-1 FFFFFFFF FFFFFFFF
SyncMode 0 bit 28, 64 words:
  CHCR 11000000 BCR 00000040: done at 1380; MADR start0 BCR 00000040 CHCR 00000000; words 0-1 FFFFFFFF FFFFFFFF
Done.
```

### 27 September 2026 card-g

Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/00RUN.txt) · [01DRB.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/01DRB.txt) · [02DOT.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/02DOT.txt) · [03DGL.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/03DGL.txt) · [04DGB.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/04DGB.txt) · [05DSP.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/05DSP.txt) · [06DMW.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/06DMW.txt) · [07DIC.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/07DIC.txt) · [08DCP.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/08DCP.txt) · [09DCH.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/09DCH.txt) · [10DPR.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/10DPR.txt) · [11DMD.txt](/tests/raw/20260927T0000Z-5501a-card-g/dmatime_safe/11DMD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC034B4 DCIC 00000000 BadVaddr 1F801DAA BDAM 00000000
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80022438 PRId 00000002
```

01DRB.txt:

```
===== 01 DRB DMA READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA registers written and read back, each channel with its DPCR enable off.
1F8010F8h reads 3FEB1A1C, 1F8010FCh reads 00FFFFFF
Channel 0 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 0 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 0 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 0 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 1 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 1 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 1 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 1 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 2 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 2 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 2 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 2 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 3 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 3 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 3 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 3 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 4 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 4 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 4 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 4 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 5 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 5 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 5 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 5 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 6 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 6 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 6 CHCR: FFFFFFFF reads 51000002, 8E88F8FC reads 00000002, 60770703 reads 40000002 (at +Ch 40000002)
Channel 6 CHCR: 10000000 reads 10000002, byte 07 at +2 reads 00000002, 0 reads 00000002
DPCR was 33333B33. FFFFFFFF reads FFFFFFFF, 0 reads 00000000, 80000000 reads 80000000, 70000000 reads 70000000, byte 08 at +3 reads 08000000
DICR was 00000000. 0 reads 00000000, 7F reads 0000003F, 7F80 reads 00000000, FF0000 reads 00FF0000, 80000000 reads 00000000, IRQ3 0
DICR 8000 reads 80008000 with IRQ3 1; 0 reads 00000000; 8000 again IRQ3 0; 8000 while set IRQ3 1
DICR byte 80 at +2 reads 00800000, halfword 0080 at +2 reads 00800000
1F8010F8h reads 3FEB1A1C, 1F8010FCh reads 00FFFFFF, at +2 halfwords 3FEB 00FF
Done.
```

02DOT.txt:

```
===== 02 DOT DMA OTC TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA6 OTC, CHCR 11000002: system clocks from the CHCR write to the poll that sees bit 24 clear, four times each.
CHCR written 00000002, no transfer: 68, polls 0
OTC     1 words: 89 89 89 92 | polls 1, MADR start0, BCR 00000001, CHCR 00000002, table right
After the first OTC: 1F8010F8h 3FE32A5C, 1F8010FCh 00FFFFFF
OTC     2 words: 90 90 95 90 | polls 1, MADR start0, BCR 00000002, CHCR 00000002, table right
OTC     3 words: 91 97 91 91 | polls 1, MADR start0, BCR 00000003, CHCR 00000002, table right
OTC     4 words: 92 92 102 94 | polls 1, MADR start0, BCR 00000004, CHCR 00000002, table right
OTC     8 words: 101 101 101 101 | polls 1, MADR start0, BCR 00000008, CHCR 00000002, table right
OTC    15 words: 112 108 112 112 | polls 1, MADR start0, BCR 0000000F, CHCR 00000002, table right
OTC    16 words: 109 112 109 109 | polls 1, MADR start0, BCR 00000010, CHCR 00000002, table right
OTC    17 words: 110 110 110 110 | polls 1, MADR start0, BCR 00000011, CHCR 00000002, table right
OTC    32 words: 125 125 125 125 | polls 1, MADR start0, BCR 00000020, CHCR 00000002, table right
OTC    64 words: 157 167 161 160 | polls 1, MADR start0, BCR 00000040, CHCR 00000002, table right
OTC   128 words: 223 231 224 231 | polls 1, MADR start0, BCR 00000080, CHCR 00000002, table right
OTC   256 words: 359 359 359 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000002, table right
OTC  1024 words: 1182 1176 1175 1172 | polls 1, MADR start0, BCR 00000400, CHCR 00000002, table right
OTC  4096 words: 4434 4429 4434 4432 | polls 1, MADR start0, BCR 00001000, CHCR 00000002, table right
OTC 16384 words: 17462 17467 17470 17463 | polls 1, MADR start0, BCR 00004000, CHCR 00000002, table right
OTC 65535 words: 69590 69596 69591 69600 | polls 1, MADR start0, BCR 0000FFFF, CHCR 00000002, table right
OTC 65536 words: 69602 69596 69597 69596 | polls 1, MADR start0, BCR 00000000, CHCR 00000002, table right
OTC 256 words, CHCR 51000002 (bit 30): 359 361 359 359 | CHCR after 40000002, table right
OTC BCR 00050010 (16 words, 5 in the upper half): 109 109 109 109 | BCR after 00050010, table right
After: 1F8010F8h 3FE32A5C, 1F8010FCh 00FFFFFF
Done.
```

03DGL.txt:

```
===== 03 DGL DMA GPU LISTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA2 linked lists, CHCR 01000401, GP1(04h)=2: clocks from the CHCR write to bit 24 clear, and the polls the CPU made meanwhile. BCR written 00050010 first.
List    1 nodes of   0 NOP words: 90 (1 polls) 90 (1 polls) 90 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    2 nodes of   0 NOP words: 100 (1 polls) 94 (1 polls) 94 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of   0 NOP words: 114 (2 polls) 114 (2 polls) 114 (2 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   0 NOP words: 235 (8 polls) 234 (8 polls) 238 (8 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   64 nodes of   0 NOP words: 718 (32 polls) 727 (33 polls) 726 (33 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List  256 nodes of   0 NOP words: 2691 (133 polls) 2690 (133 polls) 2699 (133 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 1024 nodes of   0 NOP words: 10561 (533 polls) 10557 (532 polls) 10557 (532 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 2048 nodes of   0 NOP words: 21043 (1065 polls) 21037 (1064 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   1 NOP words: 329 (15 polls) 325 (15 polls) 330 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   2 NOP words: 349 (15 polls) 340 (15 polls) 344 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   4 NOP words: 383 (15 polls) 374 (15 polls) 374 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   8 NOP words: 450 (15 polls) 450 (15 polls) 450 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  15 NOP words: 568 (15 polls) 568 (15 polls) 565 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  16 NOP words: 584 (15 polls) 588 (15 polls) 584 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  32 NOP words: 858 (15 polls) 858 (15 polls) 858 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  64 NOP words: 1389 (15 polls) 1384 (15 polls) 1395 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 128 NOP words: 2474 (15 polls) 2478 (15 polls) 2474 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 255 NOP words: 4619 (15 polls) 4621 (15 polls) 4613 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    1 nodes of 255 NOP words: 367 (1 polls) 361 (1 polls) 363 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of 255 NOP words: 1208 (3 polls) 1210 (3 polls) 1210 (3 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
Done.
```

04DGB.txt:

```
===== 04 DGB DMA GPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA2 blocks to and from VRAM at 512,256: clocks from the CHCR write to bit 24 clear, twice each; polls, MADR, BCR and CHCR after.
Write SyncMode 1, 16 words x 1: 107 107 | polls 1, MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 124 124 | polls 1, MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 178 178 | polls 3, MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 517 517 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 1875 1867 | polls 63, MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 256: 7127 7121 | polls 258, MADR start16384, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 256: 2976 2987 | polls 194, MADR start1024, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 128: 1743 1739 | polls 127, MADR start1024, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 64: 983 993 | polls 63, MADR start1024, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 32: 668 672 | polls 31, MADR start1024, BCR 00000008, CHCR 00000201
Write SyncMode 1, 32 words x 8: 420 451 | polls 8, MADR start1024, BCR 00000020, CHCR 00000201
Write SyncMode 0, 256 words: 357 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0, 2048 words: 2251 2253 | polls 1, MADR start0, BCR 00000800, CHCR 00000001
Write SyncMode 0 bit 28, 256 words: 357 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 1 bit 28, 16 words x 16: 540 520 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+2, 16 words x 4: 178 178 | polls 3, MADR start254, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+1, 16 words x 4: 178 184 | polls 3, MADR start255, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 1: 109 109 | polls 1, MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 558 557 | polls 18, MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 2235 2243 | polls 91, MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 64: 929 928 | polls 63, MADR start1024, BCR 00000004, CHCR 00000200
Read SyncMode 0, 256 words: 362 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 0 bit 28, 256 words: 365 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 1, MADR+2, 16 words x 4: 178 174 | polls 3, MADR start254, BCR 00000010, CHCR 00000200
Read back words 0-3: 7FFF0000 7FFF0001 7FFF0002 7FFF0003
Done.
```

05DSP.txt:

```
===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 220931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 219 (1) 221 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1498 (90) 1483 (88) 1286 (73) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3836 (249) 3832 (249) 3847 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8533 (571) 8545 (572) 8545 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17780 (1202) 17783 (1202) 17790 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73079 (4970) 73079 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4067 (264) 4084 (265) 4079 (265) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4867 (330) 4879 (331) 4870 (330) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4487 (299) 4478 (298) 4487 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4278 (284) 4279 (284) 4486 (300) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 215 (1) 219 (1) 214 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3901 (254) 3911 (254) 3913 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17780 (1206) 17810 (1208) 17801 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73099 (5000) 73106 (5000) 73097 (5000) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4786 (323) 4784 (323) 4784 (323) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 217 (1) 217 (1) 220 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 609 (1) 606 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2137 (1) 2142 (1) 2138 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 601 (1) 608 (1) 606 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 641 (3) 667 (5) 652 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 614 (1) 615 (1) 618 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3840 (250) 3841 (250) 3847 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17775 (1201) 17339 (1167) 17781 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17790 (1207) 17801 (1208) 17810 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17431 (1173) 17642 (1190) 17651 (1191) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16874 (1215) 16868 (1214) 16868 (1214) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17789 (1207) 17810 (1208) 17801 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.
```

06DMW.txt:

```
===== 06 DMW DMA MIDWAY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR, MADR, BCR and DICR polled while a transfer runs: a row each time one changes (t is timer 2's low 16 bits). DICR flags need bit 23 and bit 16+n (dmachannels.txt:184-186); bits 0-6 may give a flag per slice (dmachannels.txt:174-177).
SPU write 16 words x 8, CHCR 01000201, DICR 00000000:
  poll    t: CHCR MADR BCR DICR
      0   553: 01000201 0011A428 00070010 00000000
      3  1662: 01000201 0011A468 00060010 00000000
      6  2740: 01000201 0011A4A8 00050010 00000000
     10  4093: 01000201 0011A4E8 00040010 00000000
     13  5160: 01000201 0011A528 00030010 00000000
     16  6229: 01000201 0011A568 00020010 00000000
     19  7293: 01000201 0011A568 00010010 00000000
     20  7658: 01000201 0011A5A8 00010010 00000000
     23  8726: 00000201 0011A5E8 00000010 00000000
  done after 23 polls
SPU write 16 words x 8, CHCR 11000201 (bit 28):
  poll    t: CHCR MADR BCR DICR
      0   520: 01000201 0011A428 00070010 00000000
      4  1900: 01000201 0011A468 00060010 00000000
      7  2961: 01000201 0011A4A8 00050010 00000000
     10  4033: 01000201 0011A4E8 00040010 00000000
     13  5101: 01000201 0011A4E8 00030010 00000000
     14  5469: 01000201 0011A528 00030010 00000000
     17  6540: 01000201 0011A568 00020010 00000000
     20  7611: 01000201 0011A5A8 00010010 00000000
     23  8685: 01000201 0011A5A8 00000010 00000000
     24  9054: 00000201 0011A5E8 00000010 00000000
  done after 24 polls
SPU write 16 words x 8, DICR 00900000 (bit 23, bit 20):
  poll    t: CHCR MADR BCR DICR
      0   515: 01000201 0011A428 00070010 00900000
      4  1903: 01000201 0011A468 00060010 00900000
      7  2976: 01000201 0011A4A8 00050010 00900000
     10  4040: 01000201 0011A4E8 00040010 00900000
     13  5112: 01000201 0011A528 00030010 00900000
     17  6465: 01000201 0011A568 00020010 00900000
     20  7532: 01000201 0011A5A8 00010010 00900000
     23  8602: 01000201 0011A5E8 00000010 90900000
     24  8964: 00000201 0011A5E8 00000010 90900000
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010 (bit 4 too, a flag per slice?):
  poll    t: CHCR MADR BCR DICR
      0   519: 01000201 0011A428 00070010 90900010
      4  1901: 01000201 0011A468 00060010 90900010
      7  2965: 01000201 0011A4A8 00050010 90900010
     10  4037: 01000201 0011A4E8 00040010 90900010
     13  5105: 01000201 0011A4E8 00030010 90900010
     14  5473: 01000201 0011A528 00030010 90900010
     17  6544: 01000201 0011A568 00020010 90900010
     20  7615: 01000201 0011A5A8 00010010 90900010
     23  8689: 01000201 0011A5A8 00000010 90900010
     24  9058: 00000201 0011A5E8 00000010 90900010
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010, I_STAT bit 3 in the last column:
  poll    t: CHCR MADR BCR I_STAT&8
      0   519: 01000201 0011A428 00070010 00000008
      4  1913: 01000201 0011A468 00060010 00000008
      7  2985: 01000201 0011A4A8 00050010 00000008
     10  4059: 01000201 0011A4E8 00040010 00000008
     13  5112: 01000201 0011A528 00030010 00000008
     17  6462: 01000201 0011A568 00020010 00000008
     20  7521: 01000201 0011A5A8 00010010 00000008
     23  8590: 01000201 0011A5E8 00000010 00000008
     24  8952: 00000201 0011A5E8 00000010 00000008
  done after 24 polls
SPU read 16 words x 8, CHCR 01000200:
  poll    t: CHCR MADR BCR DICR
      0   519: 01000200 0011A428 00070010 00000000
      4  1907: 01000200 0011A468 00060010 00000000
      7  2969: 01000200 0011A4A8 00050010 00000000
     10  4034: 01000200 0011A4E8 00040010 00000000
     13  5108: 01000200 0011A4E8 00030010 00000000
     14  5475: 01000200 0011A528 00030010 00000000
     17  6550: 01000200 0011A568 00020010 00000000
     20  7622: 01000200 0011A5A8 00010010 00000000
     23  8675: 00000200 0011A5E8 00000010 00000000
  done after 23 polls
GPU write 16 words x 8 to VRAM, CHCR 01000201:
  poll    t: CHCR MADR BCR DICR
      0   552: 01000201 0015B5E8 00000010 00000000
      1   941: 00000201 0015B5E8 00000010 00000000
  done after 1 polls
GPU list 8 nodes of 15 NOPs, DICR 00840004 (bit 2, a flag per entry?):
  list at 116248, nodes 64 bytes apart
  poll    t: CHCR MADR BCR DICR
      0   573: 01000401 00FFFFFF 00000000 84840004
      1   964: 00000401 00FFFFFF 00000000 84840004
  done after 1 polls
Done.
```

07DIC.txt:

```
===== 07 DIC DMA DICR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DICR around a 16 word OTC (channel 6: enable bit 22, flag bit 30). psx-spx sets the flag only with bit 23 and bit 22 (dmachannels.txt:184-186), nocash with bit 22 alone (channels.txt:122-123). IRQ3 is I_STAT bit 3, acknowledged before each OTC.
DICR 00000000 reads 00000000 (IRQ3 0); after OTC 00000000, IRQ3 0
DICR 00400000 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00800000 reads 00800000 (IRQ3 0); after OTC 00800000, IRQ3 0
DICR 00C00000 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00C00040 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00400040 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00BF0000 reads 00BF0000 (IRQ3 0); after OTC 00BF0000, IRQ3 0
DICR 00FF0000 reads 00FF0000 (IRQ3 0); after OTC C0FF0000, IRQ3 1
DICR 00008000 reads 80008000 (IRQ3 1); after OTC 80008000, IRQ3 0
DICR 00C08000 reads 80C08000 (IRQ3 1); after OTC C0C08000, IRQ3 0
DICR 0000003F reads 0000003F (IRQ3 0); after OTC 0000003F, IRQ3 0
A flag, then its enables taken away:
  after OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  bit 22 off: wrote 00800000, reads C0800000, IRQ3 0
  bit 23 off too: wrote 00000000, reads 40000000, IRQ3 0
  bit 23 on: wrote 00800000, reads C0800000, IRQ3 1
  bit 23 on again: wrote 00800000, reads C0800000, IRQ3 0
  flag acknowledged: wrote 40800000, reads 00800000, IRQ3 0
  bit 31 written: wrote 80800000, reads 00800000, IRQ3 0
Flag with bit 22 alone, then bit 23:
  after OTC: wrote 00400000, reads 40400000, IRQ3 0
  bit 23 on: wrote 00C00000, reads C0C00000, IRQ3 1
Bit 15 set, then a flag:
  bit 15 and 22 and 23: wrote 00C08000, reads 80C08000, IRQ3 1
  after OTC: wrote 00C08000, reads C0C08000, IRQ3 0
  bit 15 off: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
Two flags, one acknowledged:
  after first OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  after second OTC: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
  after third OTC: wrote 00C00000, reads C0C00000, IRQ3 1
OTC with bit 28 alone (no start, otc.c) and DICR 00C00000:
  after: wrote 00C00000, reads 00C00000, IRQ3 0
Done.
```

08DCP.txt:

```
===== 08 DCP DMA CPU DURING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
A loop from the i-cache started right after the CHCR write that starts a transfer, then a timer 2 read: clocks alone and with the transfer. A loop turn is its body, addiu, bnez, nop.
OTC 16384 words (CHCR 11000002):
  registers n=1: alone 23, with the transfer 17407
  registers n=100: alone 419, with the transfer 17408
  registers n=1000: alone 4019, with the transfer 17400
  registers n=4000: alone 16019, with the transfer 17402
  registers n=10000: alone 40019, with the transfer 40019
  registers n=20000: alone 80019, with the transfer 80019
  scratchpad loads n=100: alone 419, with the transfer 17403
  scratchpad loads n=1000: alone 4019, with the transfer 17402
  scratchpad loads n=4000: alone 16019, with the transfer 17412
  scratchpad loads n=10000: alone 40019, with the transfer 40019
  scratchpad loads n=20000: alone 80019, with the transfer 80019
  RAM stores n=100: alone 423, with the transfer 17790
  RAM stores n=1000: alone 4020, with the transfer 21391
  RAM stores n=4000: alone 16020, with the transfer 33402
  RAM stores n=10000: alone 40021, with the transfer 57397
  RAM loads n=100: alone 929, with the transfer 18312
  RAM loads n=1000: alone 9162, with the transfer 26542
  RAM loads n=4000: alone 36586, with the transfer 53970
  RAM loads n=10000: alone 91444, with the transfer 108819
  CHCR loads n=100: alone 719, with the transfer 18094
  CHCR loads n=1000: alone 7019, with the transfer 24384
  CHCR loads n=4000: alone 28019, with the transfer 45394
  CHCR loads n=10000: alone 70019, with the transfer 87400
SPU write 16 words x 64 (CHCR 01000201):
  registers n=100: alone 419, with the transfer 419 (still busy after)
  registers n=1000: alone 4019, with the transfer 4019 (still busy after)
  registers n=4000: alone 16019, with the transfer 16019 (still busy after)
  registers n=10000: alone 40019, with the transfer 40019 (still busy after)
  RAM loads n=100: alone 930, with the transfer 1063 (still busy after)
  RAM loads n=1000: alone 9158, with the transfer 10481 (still busy after)
  RAM loads n=4000: alone 36586, with the transfer 41351 (still busy after)
  CHCR loads n=100: alone 719, with the transfer 850 (still busy after)
  CHCR loads n=1000: alone 7019, with the transfer 7946 (still busy after)
  CHCR loads n=4000: alone 28019, with the transfer 31752 (still busy after)
GPU write 2048 words SyncMode 0 chopped, DMA window 1 word, CPU window 128 clocks (CHCR 01700101):
  registers n=100: alone 424, with the transfer 432 (still busy after) (clock/8)
  registers n=1000: alone 4016, with the transfer 4040 (still busy after) (clock/8)
  registers n=4000: alone 16024, with the transfer 16040 (still busy after) (clock/8)
  registers n=10000: alone 40016, with the transfer 40032 (still busy after) (clock/8)
  RAM loads n=100: alone 928, with the transfer 976 (still busy after) (clock/8)
  RAM loads n=1000: alone 9160, with the transfer 9232 (still busy after) (clock/8)
  RAM loads n=4000: alone 36592, with the transfer 36800 (still busy after) (clock/8)
GPU write 2048 words SyncMode 0 not chopped (CHCR 01000001):
  registers n=100: alone 419, with the transfer 2215
  registers n=1000: alone 4019, with the transfer 4036
  registers n=4000: alone 16019, with the transfer 16036
  registers n=10000: alone 40019, with the transfer 40036
Done.
```

09DCH.txt:

```
===== 09 DCH DMA CHOP SHARE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
GPU write 2048 words SyncMode 0 chopped (CHCR 01xx0101), polling CHCR: clocks, polls (the CPU's share), MADR, BCR, CHCR after. Not chopped for scale first.
Not chopped: 2247, polls 1
DMA window   1 words, CPU window   1 clocks: 16720, polls 1040, MADR start8192, BCR 00000000, CHCR 00000101
DMA window   1 words, CPU window   4 clocks: 23376, polls 1547, MADR start8192, BCR 00000000, CHCR 00200101
DMA window   1 words, CPU window  16 clocks: 47880, polls 3412, MADR start8192, BCR 00000000, CHCR 00400101
DMA window   1 words, CPU window  32 clocks: 80688, polls 6141, MADR start8192, BCR 00000000, CHCR 00500101
DMA window   1 words, CPU window 128 clocks: 276648, polls 20471, MADR start8192, BCR 00000000, CHCR 00700101
DMA window   2 words, CPU window   1 clocks: 9440, polls 512, MADR start8192, BCR 00000000, CHCR 00010101
DMA window   2 words, CPU window   4 clocks: 13408, polls 1023, MADR start8192, BCR 00000000, CHCR 00210101
DMA window   2 words, CPU window  16 clocks: 24640, polls 1706, MADR start8192, BCR 00000000, CHCR 00410101
DMA window   2 words, CPU window  32 clocks: 41000, polls 3069, MADR start8192, BCR 00000000, CHCR 00510101
DMA window   2 words, CPU window 128 clocks: 139216, polls 10231, MADR start8192, BCR 00000000, CHCR 00710101
DMA window   4 words, CPU window   1 clocks: 5864, polls 267, MADR start8192, BCR 00000000, CHCR 00020101
DMA window   4 words, CPU window   4 clocks: 7352, polls 511, MADR start8192, BCR 00000000, CHCR 00220101
DMA window   4 words, CPU window  16 clocks: 13480, polls 1022, MADR start8192, BCR 00000000, CHCR 00420101
DMA window   4 words, CPU window  32 clocks: 21872, polls 1533, MADR start8192, BCR 00000000, CHCR 00520101
DMA window   4 words, CPU window 128 clocks: 70680, polls 5111, MADR start8192, BCR 00000000, CHCR 00720101
DMA window  16 words, CPU window   1 clocks: 3136, polls 127, MADR start8192, BCR 00000000, CHCR 00040101
DMA window  16 words, CPU window   4 clocks: 3488, polls 127, MADR start8192, BCR 00000000, CHCR 00240101
DMA window  16 words, CPU window  16 clocks: 5024, polls 254, MADR start8192, BCR 00000000, CHCR 00440101
DMA window  16 words, CPU window  32 clocks: 7064, polls 381, MADR start8192, BCR 00000000, CHCR 00540101
DMA window  16 words, CPU window 128 clocks: 19272, polls 1271, MADR start8192, BCR 00000000, CHCR 00740101
DMA window 128 words, CPU window   1 clocks: 2344, polls 15, MADR start8192, BCR 00000000, CHCR 00070101
DMA window 128 words, CPU window   4 clocks: 2392, polls 15, MADR start8192, BCR 00000000, CHCR 00270101
DMA window 128 words, CPU window  16 clocks: 2568, polls 30, MADR start8192, BCR 00000000, CHCR 00470101
DMA window 128 words, CPU window  32 clocks: 2800, polls 45, MADR start8192, BCR 00000000, CHCR 00570101
DMA window 128 words, CPU window 128 clocks: 4216, polls 151, MADR start8192, BCR 00000000, CHCR 00770101
Chopped 1 word / 128 clocks, as it runs:
  poll    t: CHCR MADR BCR GPUSTAT&1C000000
      0   427: 01700101 0015B3EC 000007FF 10000000
      1   838: 01700101 0015B3FC 000007FB 10000000
      2  1210: 01700101 0015B404 000007F8 10000000
      3  1583: 01700101 0015B410 000007F6 00000000
      4  1958: 01700101 0015B41C 000007F3 10000000
      5  2323: 01700101 0015B428 000007F0 10000000
      6  2695: 01700101 0015B430 000007ED 10000000
      7  3075: 01700101 0015B43C 000007EB 00000000
      8  3447: 01700101 0015B448 000007E8 10000000
      9  3812: 01700101 0015B454 000007E5 10000000
     10  4186: 01700101 0015B45C 000007E2 10000000
     11  4563: 01700101 0015B468 000007E0 00000000
     12  4939: 01700101 0015B474 000007DD 10000000
     13  5306: 01700101 0015B480 000007DA 10000000
     14  5677: 01700101 0015B488 000007D7 10000000
     15  6054: 01700101 0015B494 000007D5 00000000
     16  6430: 01700101 0015B4A0 000007D2 10000000
     17  6807: 01700101 0015B4AC 000007CF 10000000
     18  7181: 01700101 0015B4B4 000007CC 10000000
     19  7558: 01700101 0015B4C0 000007CA 00000000
  done after 949 polls (rows cut at 20)
SPU write 256 words SyncMode 0 chopped 16 words / 64 clocks (CHCR 01640101): 3206, polls 75, MADR start1024, BCR 00000000
SPU write 256 words SyncMode 0 not chopped: 2137, polls 1
Done.
```

10DPR.txt:

```
===== 10 DPR DMA PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Two channels armed with their DPCR enables off, then one DPCR write: which wrote each of 64 shared words last (O OTC, S SPU, G GPU, . untouched, ? other).
SPU read SyncMode 1, priority 1, OTC priority 5: 3905 clocks, 247 polls
  OOOOOOOOOOOOOOOOSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 5, OTC priority 1: 3905 clocks, 247 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 3, OTC priority 3: 3908 clocks, 247 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 1, OTC priority 5: 715 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
SPU read SyncMode 0, priority 5, OTC priority 1: 718 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 3, OTC priority 3: 718 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
GPU read SyncMode 1, priority 1, OTC priority 5: 258 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 1, priority 5, OTC priority 1: 277 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 1, priority 3, OTC priority 3: 271 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 0, priority 1, OTC priority 5: 265 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 0, priority 5, OTC priority 1: 265 clocks, 1 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
DPCR bits 28-30, CPU priority (channels.txt:105, dmachannels.txt:168):
DPCR 0B3B3B33, SPU write 16 words x 64: 73079, polls 4970; loop of 10000 alone 40025, with the SPU write 40019
DPCR 3B3B3B33, SPU write 16 words x 64: 73077, polls 4970; loop of 10000 alone 40025, with the SPU write 40019
DPCR 7B3B3B33, SPU write 16 words x 64: 73087, polls 4970; loop of 10000 alone 40025, with the SPU write 40019
Done.
```

11DMD.txt:

```
===== 11 DMD DMA MDEC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA0 and DMA1 with the MDEC: tables, then MDEC(1) on blocks of only a DC value (Q 1, DC 20h) and FE00h; DMA1 armed first. Clocks from the DMA0 start. Scale table zero.
Mono 8 bit, 1 block, out 16x1: quant 16 words 107, scale 32 words 68, decode: DMA0 done at 175, DMA1 done at 1013, 30 polls
  output sum 08080800, words 0 and last 80808080 80808080; MDEC status 8204FFFF
  DMA0 MADR start128 BCR 00000020 CHCR 00000201; DMA1 MADR start64 BCR 00000010 CHCR 00000200
Mono 8 bit, 4 blocks, out 16x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040010 CHCR 01000200
Mono 8 bit, 4 blocks, out 32x2: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00020020 CHCR 01000200
Mono 4 bit, 4 blocks, out 8x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999980, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040008 CHCR 01000200
Colour 15 bit, 1 macroblock, out 32x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 66666600, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040020 CHCR 01000200
Colour 24 bit, 1 macroblock, out 32x6: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999900, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00060020 CHCR 01000200
Colour 15 bit, 2 macroblocks, out 32x8: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum CCCCCC00, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00080020 CHCR 01000200
Done.
```

### 27 September 2026 card-g3

Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/00RUN.txt) · [01DRB.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/01DRB.txt) · [02DOT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/02DOT.txt) · [03DGL.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/03DGL.txt) · [04DGB.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/04DGB.txt) · [05DSP.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/05DSP.txt) · [06DMW.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/06DMW.txt) · [07DIC.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/07DIC.txt) · [08DCP.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/08DCP.txt) · [09DCH.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/09DCH.txt) · [10DPR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/10DPR.txt) · [11DMD.txt](/tests/raw/20260927T0000Z-5501a-card-g3/dmatime_safe/11DMD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010D338 PRId 00000002
```

01DRB.txt:

```
===== 01 DRB DMA READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA registers written and read back, each channel with its DPCR enable off.
1F8010F8h reads 7FE7581A, 1F8010FCh reads 00FFFFFF
Channel 0 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 0 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 0 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 0 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 1 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 1 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 1 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 1 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 2 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 2 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 2 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 2 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 3 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 3 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 3 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 3 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 4 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 4 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 4 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 4 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 5 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 5 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 5 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 5 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 6 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 6 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 6 CHCR: FFFFFFFF reads 51000002, 8E88F8FC reads 00000002, 60770703 reads 40000002 (at +Ch 40000002)
Channel 6 CHCR: 10000000 reads 10000002, byte 07 at +2 reads 00000002, 0 reads 00000002
DPCR was 33333B33. FFFFFFFF reads FFFFFFFF, 0 reads 00000000, 80000000 reads 80000000, 70000000 reads 70000000, byte 08 at +3 reads 08000000
DICR was 00000000. 0 reads 00000000, 7F reads 0000003F, 7F80 reads 00000000, FF0000 reads 00FF0000, 80000000 reads 00000000, IRQ3 0
DICR 8000 reads 80008000 with IRQ3 1; 0 reads 00000000; 8000 again IRQ3 0; 8000 while set IRQ3 1
DICR byte 80 at +2 reads 00800000, halfword 0080 at +2 reads 00800000
1F8010F8h reads 7FE7581A, 1F8010FCh reads 00FFFFFF, at +2 halfwords 7FE7 00FF
Done.
```

02DOT.txt:

```
===== 02 DOT DMA OTC TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA6 OTC, CHCR 11000002: system clocks from the CHCR write to the poll that sees bit 24 clear, four times each.
CHCR written 00000002, no transfer: 68, polls 0
OTC     1 words: 92 89 92 89 | polls 1, MADR start0, BCR 00000001, CHCR 00000002, table right
After the first OTC: 1F8010F8h 7FE3585A, 1F8010FCh 00FFFFFF
OTC     2 words: 90 90 94 90 | polls 1, MADR start0, BCR 00000002, CHCR 00000002, table right
OTC     3 words: 91 91 91 91 | polls 1, MADR start0, BCR 00000003, CHCR 00000002, table right
OTC     4 words: 92 92 92 92 | polls 1, MADR start0, BCR 00000004, CHCR 00000002, table right
OTC     8 words: 105 106 105 106 | polls 1, MADR start0, BCR 00000008, CHCR 00000002, table right
OTC    15 words: 108 113 108 108 | polls 1, MADR start0, BCR 0000000F, CHCR 00000002, table right
OTC    16 words: 109 114 114 113 | polls 1, MADR start0, BCR 00000010, CHCR 00000002, table right
OTC    17 words: 110 115 115 114 | polls 1, MADR start0, BCR 00000011, CHCR 00000002, table right
OTC    32 words: 125 128 125 129 | polls 1, MADR start0, BCR 00000020, CHCR 00000002, table right
OTC    64 words: 157 157 157 157 | polls 1, MADR start0, BCR 00000040, CHCR 00000002, table right
OTC   128 words: 221 221 231 221 | polls 1, MADR start0, BCR 00000080, CHCR 00000002, table right
OTC   256 words: 359 359 359 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000002, table right
OTC  1024 words: 1172 1172 1172 1172 | polls 1, MADR start0, BCR 00000400, CHCR 00000002, table right
OTC  4096 words: 4429 4431 4434 4429 | polls 1, MADR start0, BCR 00001000, CHCR 00000002, table right
OTC 16384 words: 17468 17461 17463 17464 | polls 1, MADR start0, BCR 00004000, CHCR 00000002, table right
OTC 65535 words: 69601 69593 69585 69588 | polls 1, MADR start0, BCR 0000FFFF, CHCR 00000002, table right
OTC 65536 words: 69601 69594 69586 69587 | polls 1, MADR start0, BCR 00000000, CHCR 00000002, table right
OTC 256 words, CHCR 51000002 (bit 30): 359 360 359 359 | CHCR after 40000002, table right
OTC BCR 00050010 (16 words, 5 in the upper half): 115 109 109 109 | BCR after 00050010, table right
After: 1F8010F8h 7FE3585A, 1F8010FCh 00FFFFFF
Done.
```

03DGL.txt:

```
===== 03 DGL DMA GPU LISTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA2 linked lists, CHCR 01000401, GP1(04h)=2: clocks from the CHCR write to bit 24 clear, and the polls the CPU made meanwhile. BCR written 00050010 first.
List    1 nodes of   0 NOP words: 90 (1 polls) 96 (1 polls) 94 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    2 nodes of   0 NOP words: 94 (1 polls) 94 (1 polls) 94 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of   0 NOP words: 114 (2 polls) 119 (2 polls) 114 (2 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   0 NOP words: 236 (8 polls) 235 (8 polls) 239 (8 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   64 nodes of   0 NOP words: 733 (34 polls) 728 (33 polls) 723 (33 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List  256 nodes of   0 NOP words: 2689 (133 polls) 2692 (133 polls) 2694 (133 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 1024 nodes of   0 NOP words: 10557 (532 polls) 10560 (532 polls) 10560 (532 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 2048 nodes of   0 NOP words: 21040 (1064 polls) 21043 (1065 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   1 NOP words: 325 (15 polls) 328 (15 polls) 329 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   2 NOP words: 347 (15 polls) 345 (15 polls) 343 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   4 NOP words: 382 (15 polls) 372 (15 polls) 373 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   8 NOP words: 450 (15 polls) 440 (15 polls) 446 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  15 NOP words: 572 (15 polls) 568 (15 polls) 568 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  16 NOP words: 584 (15 polls) 569 (15 polls) 584 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  32 NOP words: 858 (15 polls) 864 (15 polls) 864 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  64 NOP words: 1398 (15 polls) 1394 (15 polls) 1380 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 128 NOP words: 2460 (15 polls) 2474 (15 polls) 2478 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 255 NOP words: 4620 (15 polls) 4628 (15 polls) 4612 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    1 nodes of 255 NOP words: 361 (1 polls) 361 (1 polls) 361 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of 255 NOP words: 1204 (3 polls) 1204 (3 polls) 1210 (3 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
Done.
```

04DGB.txt:

```
===== 04 DGB DMA GPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA2 blocks to and from VRAM at 512,256: clocks from the CHCR write to bit 24 clear, twice each; polls, MADR, BCR and CHCR after.
Write SyncMode 1, 16 words x 1: 107 107 | polls 1, MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 130 134 | polls 1, MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 182 178 | polls 3, MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 517 512 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 1855 1870 | polls 63, MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 256: 7153 7126 | polls 257, MADR start16384, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 256: 2978 2983 | polls 193, MADR start1024, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 128: 1732 1733 | polls 127, MADR start1024, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 64: 983 988 | polls 63, MADR start1024, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 32: 677 673 | polls 31, MADR start1024, BCR 00000008, CHCR 00000201
Write SyncMode 1, 32 words x 8: 433 431 | polls 7, MADR start1024, BCR 00000020, CHCR 00000201
Write SyncMode 0, 256 words: 357 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0, 2048 words: 2247 2247 | polls 1, MADR start0, BCR 00000800, CHCR 00000001
Write SyncMode 0 bit 28, 256 words: 363 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 1 bit 28, 16 words x 16: 530 520 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+2, 16 words x 4: 178 183 | polls 3, MADR start254, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+1, 16 words x 4: 178 183 | polls 3, MADR start255, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 1: 109 109 | polls 1, MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 569 569 | polls 19, MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 2235 2237 | polls 91, MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 64: 929 920 | polls 63, MADR start1024, BCR 00000004, CHCR 00000200
Read SyncMode 0, 256 words: 359 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 0 bit 28, 256 words: 359 369 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 1, MADR+2, 16 words x 4: 179 174 | polls 3, MADR start254, BCR 00000010, CHCR 00000200
Read back words 0-3: 7FFF0000 7FFF0001 7FFF0002 7FFF0003
Done.
```

05DSP.txt:

```
===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 200931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 217 (1) 217 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1489 (89) 1288 (73) 1489 (89) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3836 (249) 3840 (250) 3849 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8547 (572) 8543 (572) 8547 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17781 (1202) 17790 (1202) 17789 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73086 (4970) 73078 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4089 (266) 4079 (265) 4088 (266) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4867 (330) 4895 (332) 4897 (332) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4487 (298) 4506 (300) 4493 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4286 (284) 4491 (300) 4295 (285) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 223 (1) 233 (2) 221 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3896 (254) 3566 (229) 3902 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17378 (1170) 17802 (1203) 17825 (1205) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73084 (4970) 73119 (4973) 73109 (4972) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4800 (325) 4795 (324) 4805 (326) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 219 (1) 222 (1) 222 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 601 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2143 (1) 2141 (1) 2137 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 601 (1) 602 (1) 605 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 634 (3) 644 (4) 644 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 613 (1) 613 (1) 614 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3846 (250) 3852 (250) 3849 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17776 (1201) 17774 (1201) 17344 (1167) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17805 (1203) 17797 (1202) 17809 (1204) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17584 (1186) 17348 (1167) 17693 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16858 (1215) 16872 (1216) 16871 (1215) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17814 (1204) 17813 (1204) 17825 (1205) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 55 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.
```

06DMW.txt:

```
===== 06 DMW DMA MIDWAY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
CHCR, MADR, BCR and DICR polled while a transfer runs: a row each time one changes (t is timer 2's low 16 bits). DICR flags need bit 23 and bit 16+n (dmachannels.txt:184-186); bits 0-6 may give a flag per slice (dmachannels.txt:174-177).
SPU write 16 words x 8, CHCR 01000201, DICR 00000000:
  poll    t: CHCR MADR BCR DICR
      0   551: 01000201 0002A428 00070010 00000000
      3  1657: 01000201 0002A468 00060010 00000000
      6  2728: 01000201 0002A4A8 00050010 00000000
     10  4079: 01000201 0002A4E8 00040010 00000000
     13  5141: 01000201 0002A528 00030010 00000000
     16  6215: 01000201 0002A568 00020010 00000000
     19  7289: 01000201 0002A568 00010010 00000000
     20  7655: 01000201 0002A5A8 00010010 00000000
     23  8715: 00000201 0002A5E8 00000010 00000000
  done after 23 polls
SPU write 16 words x 8, CHCR 11000201 (bit 28):
  poll    t: CHCR MADR BCR DICR
      0   515: 01000201 0002A428 00070010 00000000
      4  1899: 01000201 0002A468 00060010 00000000
      7  2968: 01000201 0002A4A8 00050010 00000000
     10  4038: 01000201 0002A4E8 00040010 00000000
     13  5105: 01000201 0002A528 00030010 00000000
     17  6469: 01000201 0002A568 00020010 00000000
     20  7528: 01000201 0002A5A8 00010010 00000000
     24  8877: 00000201 0002A5E8 00000010 00000000
  done after 24 polls
SPU write 16 words x 8, DICR 00900000 (bit 23, bit 20):
  poll    t: CHCR MADR BCR DICR
      0   519: 01000201 0002A428 00070010 00900000
      4  1907: 01000201 0002A468 00060010 00900000
      7  2974: 01000201 0002A4A8 00050010 00900000
     10  4045: 01000201 0002A4E8 00040010 00900000
     13  5116: 01000201 0002A528 00030010 00900000
     17  6467: 01000201 0002A568 00020010 00900000
     20  7529: 01000201 0002A5A8 00010010 00900000
     23  8604: 01000201 0002A5E8 00000010 90900000
     24  8976: 00000201 0002A5E8 00000010 90900000
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010 (bit 4 too, a flag per slice?):
  poll    t: CHCR MADR BCR DICR
      0   518: 01000201 0002A428 00070010 90900010
      4  1912: 01000201 0002A468 00060010 90900010
      7  2984: 01000201 0002A4A8 00050010 90900010
     10  4054: 01000201 0002A4E8 00040010 90900010
     13  5116: 01000201 0002A528 00030010 90900010
     17  6470: 01000201 0002A568 00020010 90900010
     20  7544: 01000201 0002A5A8 00010010 90900010
     24  8893: 00000201 0002A5E8 00000010 90900010
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010, I_STAT bit 3 in the last column:
  poll    t: CHCR MADR BCR I_STAT&8
      0   520: 01000201 0002A428 00070010 00000008
      4  1910: 01000201 0002A468 00060010 00000008
      7  2977: 01000201 0002A4A8 00050010 00000008
     10  4048: 01000201 0002A4E8 00040010 00000008
     13  5119: 01000201 0002A528 00030010 00000008
     17  6470: 01000201 0002A568 00020010 00000008
     20  7532: 01000201 0002A5A8 00010010 00000008
     23  8606: 01000201 0002A5E8 00000010 00000008
     24  8982: 00000201 0002A5E8 00000010 00000008
  done after 24 polls
SPU read 16 words x 8, CHCR 01000200:
  poll    t: CHCR MADR BCR DICR
      0   521: 01000200 0002A428 00070010 00000000
      4  1900: 01000200 0002A468 00060010 00000000
      7  2964: 01000200 0002A4A8 00050010 00000000
     10  4043: 01000200 0002A4E8 00040010 00000000
     13  5106: 01000200 0002A4E8 00030010 00000000
     14  5474: 01000200 0002A528 00030010 00000000
     17  6544: 01000200 0002A568 00020010 00000000
     20  7600: 01000200 0002A5A8 00010010 00000000
     23  8669: 00000200 0002A5E8 00000010 00000000
  done after 23 polls
GPU write 16 words x 8 to VRAM, CHCR 01000201:
  poll    t: CHCR MADR BCR DICR
      0   548: 01000201 0006B5E8 00000010 00000000
      1   943: 00000201 0006B5E8 00000010 00000000
  done after 1 polls
GPU list 8 nodes of 15 NOPs, DICR 00840004 (bit 2, a flag per entry?):
  list at 026248, nodes 64 bytes apart
  poll    t: CHCR MADR BCR DICR
      0   575: 01000401 00FFFFFF 00000000 84840004
      1   969: 00000401 00FFFFFF 00000000 84840004
  done after 1 polls
Done.
```

07DIC.txt:

```
===== 07 DIC DMA DICR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DICR around a 16 word OTC (channel 6: enable bit 22, flag bit 30). psx-spx sets the flag only with bit 23 and bit 22 (dmachannels.txt:184-186), nocash with bit 22 alone (channels.txt:122-123). IRQ3 is I_STAT bit 3, acknowledged before each OTC.
DICR 00000000 reads 00000000 (IRQ3 0); after OTC 00000000, IRQ3 0
DICR 00400000 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00800000 reads 00800000 (IRQ3 0); after OTC 00800000, IRQ3 0
DICR 00C00000 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00C00040 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00400040 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00BF0000 reads 00BF0000 (IRQ3 0); after OTC 00BF0000, IRQ3 0
DICR 00FF0000 reads 00FF0000 (IRQ3 0); after OTC C0FF0000, IRQ3 1
DICR 00008000 reads 80008000 (IRQ3 1); after OTC 80008000, IRQ3 0
DICR 00C08000 reads 80C08000 (IRQ3 1); after OTC C0C08000, IRQ3 0
DICR 0000003F reads 0000003F (IRQ3 0); after OTC 0000003F, IRQ3 0
A flag, then its enables taken away:
  after OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  bit 22 off: wrote 00800000, reads C0800000, IRQ3 0
  bit 23 off too: wrote 00000000, reads 40000000, IRQ3 0
  bit 23 on: wrote 00800000, reads C0800000, IRQ3 1
  bit 23 on again: wrote 00800000, reads C0800000, IRQ3 0
  flag acknowledged: wrote 40800000, reads 00800000, IRQ3 0
  bit 31 written: wrote 80800000, reads 00800000, IRQ3 0
Flag with bit 22 alone, then bit 23:
  after OTC: wrote 00400000, reads 40400000, IRQ3 0
  bit 23 on: wrote 00C00000, reads C0C00000, IRQ3 1
Bit 15 set, then a flag:
  bit 15 and 22 and 23: wrote 00C08000, reads 80C08000, IRQ3 1
  after OTC: wrote 00C08000, reads C0C08000, IRQ3 0
  bit 15 off: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
Two flags, one acknowledged:
  after first OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  after second OTC: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
  after third OTC: wrote 00C00000, reads C0C00000, IRQ3 1
OTC with bit 28 alone (no start, otc.c) and DICR 00C00000:
  after: wrote 00C00000, reads 00C00000, IRQ3 0
Done.
```

08DCP.txt:

```
===== 08 DCP DMA CPU DURING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
A loop from the i-cache started right after the CHCR write that starts a transfer, then a timer 2 read: clocks alone and with the transfer. A loop turn is its body, addiu, bnez, nop.
OTC 16384 words (CHCR 11000002):
  registers n=1: alone 23, with the transfer 17403
  registers n=100: alone 419, with the transfer 17407
  registers n=1000: alone 4019, with the transfer 17407
  registers n=4000: alone 16019, with the transfer 17402
  registers n=10000: alone 40019, with the transfer 40019
  registers n=20000: alone 80019, with the transfer 80019
  scratchpad loads n=100: alone 419, with the transfer 17403
  scratchpad loads n=1000: alone 4019, with the transfer 17408
  scratchpad loads n=4000: alone 16019, with the transfer 17408
  scratchpad loads n=10000: alone 40019, with the transfer 40019
  scratchpad loads n=20000: alone 80019, with the transfer 80019
  RAM stores n=100: alone 423, with the transfer 17801
  RAM stores n=1000: alone 4019, with the transfer 21390
  RAM stores n=4000: alone 16019, with the transfer 33391
  RAM stores n=10000: alone 40019, with the transfer 57402
  RAM loads n=100: alone 930, with the transfer 18309
  RAM loads n=1000: alone 9158, with the transfer 26542
  RAM loads n=4000: alone 36586, with the transfer 53970
  RAM loads n=10000: alone 91449, with the transfer 108825
  CHCR loads n=100: alone 719, with the transfer 18095
  CHCR loads n=1000: alone 7019, with the transfer 24394
  CHCR loads n=4000: alone 28019, with the transfer 45400
  CHCR loads n=10000: alone 70019, with the transfer 87400
SPU write 16 words x 64 (CHCR 01000201):
  registers n=100: alone 419, with the transfer 419 (still busy after)
  registers n=1000: alone 4019, with the transfer 4019 (still busy after)
  registers n=4000: alone 16019, with the transfer 16019 (still busy after)
  registers n=10000: alone 40019, with the transfer 40019 (still busy after)
  RAM loads n=100: alone 930, with the transfer 1063 (still busy after)
  RAM loads n=1000: alone 9157, with the transfer 10440 (still busy after)
  RAM loads n=4000: alone 36586, with the transfer 41201 (still busy after)
  CHCR loads n=100: alone 719, with the transfer 850 (still busy after)
  CHCR loads n=1000: alone 7019, with the transfer 7953 (still busy after)
  CHCR loads n=4000: alone 28019, with the transfer 31753 (still busy after)
GPU write 2048 words SyncMode 0 chopped, DMA window 1 word, CPU window 128 clocks (CHCR 01700101):
  registers n=100: alone 416, with the transfer 440 (still busy after) (clock/8)
  registers n=1000: alone 4016, with the transfer 4040 (still busy after) (clock/8)
  registers n=4000: alone 16024, with the transfer 16040 (still busy after) (clock/8)
  registers n=10000: alone 40016, with the transfer 40040 (still busy after) (clock/8)
  RAM loads n=100: alone 928, with the transfer 968 (still busy after) (clock/8)
  RAM loads n=1000: alone 9160, with the transfer 9232 (still busy after) (clock/8)
  RAM loads n=4000: alone 36592, with the transfer 36792 (still busy after) (clock/8)
GPU write 2048 words SyncMode 0 not chopped (CHCR 01000001):
  registers n=100: alone 419, with the transfer 2215
  registers n=1000: alone 4019, with the transfer 4036
  registers n=4000: alone 16019, with the transfer 16036
  registers n=10000: alone 40019, with the transfer 40036
Done.
```

09DCH.txt:

```
===== 09 DCH DMA CHOP SHARE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
GPU write 2048 words SyncMode 0 chopped (CHCR 01xx0101), polling CHCR: clocks, polls (the CPU's share), MADR, BCR, CHCR after. Not chopped for scale first.
Not chopped: 2247, polls 1
DMA window   1 words, CPU window   1 clocks: 16720, polls 1040, MADR start8192, BCR 00000000, CHCR 00000101
DMA window   1 words, CPU window   4 clocks: 23368, polls 1547, MADR start8192, BCR 00000000, CHCR 00200101
DMA window   1 words, CPU window  16 clocks: 47888, polls 3413, MADR start8192, BCR 00000000, CHCR 00400101
DMA window   1 words, CPU window  32 clocks: 80696, polls 6141, MADR start8192, BCR 00000000, CHCR 00500101
DMA window   1 words, CPU window 128 clocks: 276648, polls 20471, MADR start8192, BCR 00000000, CHCR 00700101
DMA window   2 words, CPU window   1 clocks: 9448, polls 513, MADR start8192, BCR 00000000, CHCR 00010101
DMA window   2 words, CPU window   4 clocks: 13400, polls 1023, MADR start8192, BCR 00000000, CHCR 00210101
DMA window   2 words, CPU window  16 clocks: 24640, polls 1706, MADR start8192, BCR 00000000, CHCR 00410101
DMA window   2 words, CPU window  32 clocks: 41000, polls 3069, MADR start8192, BCR 00000000, CHCR 00510101
DMA window   2 words, CPU window 128 clocks: 139216, polls 10231, MADR start8192, BCR 00000000, CHCR 00710101
DMA window   4 words, CPU window   1 clocks: 5864, polls 267, MADR start8192, BCR 00000000, CHCR 00020101
DMA window   4 words, CPU window   4 clocks: 7352, polls 511, MADR start8192, BCR 00000000, CHCR 00220101
DMA window   4 words, CPU window  16 clocks: 13464, polls 1022, MADR start8192, BCR 00000000, CHCR 00420101
DMA window   4 words, CPU window  32 clocks: 21872, polls 1533, MADR start8192, BCR 00000000, CHCR 00520101
DMA window   4 words, CPU window 128 clocks: 70712, polls 5111, MADR start8192, BCR 00000000, CHCR 00720101
DMA window  16 words, CPU window   1 clocks: 3136, polls 127, MADR start8192, BCR 00000000, CHCR 00040101
DMA window  16 words, CPU window   4 clocks: 3496, polls 127, MADR start8192, BCR 00000000, CHCR 00240101
DMA window  16 words, CPU window  16 clocks: 5024, polls 254, MADR start8192, BCR 00000000, CHCR 00440101
DMA window  16 words, CPU window  32 clocks: 7088, polls 381, MADR start8192, BCR 00000000, CHCR 00540101
DMA window  16 words, CPU window 128 clocks: 19296, polls 1271, MADR start8192, BCR 00000000, CHCR 00740101
DMA window 128 words, CPU window   1 clocks: 2360, polls 15, MADR start8192, BCR 00000000, CHCR 00070101
DMA window 128 words, CPU window   4 clocks: 2392, polls 15, MADR start8192, BCR 00000000, CHCR 00270101
DMA window 128 words, CPU window  16 clocks: 2568, polls 30, MADR start8192, BCR 00000000, CHCR 00470101
DMA window 128 words, CPU window  32 clocks: 2816, polls 45, MADR start8192, BCR 00000000, CHCR 00570101
DMA window 128 words, CPU window 128 clocks: 4192, polls 151, MADR start8192, BCR 00000000, CHCR 00770101
Chopped 1 word / 128 clocks, as it runs:
  poll    t: CHCR MADR BCR GPUSTAT&1C000000
      0   425: 01700101 0006B3EC 000007FF 10000000
      1   841: 01700101 0006B3FC 000007FB 10000000
      2  1209: 01700101 0006B404 000007F8 10000000
      3  1584: 01700101 0006B410 000007F6 00000000
      4  1960: 01700101 0006B41C 000007F3 10000000
      5  2339: 01700101 0006B428 000007F0 10000000
      6  2716: 01700101 0006B430 000007ED 10000000
      7  3090: 01700101 0006B43C 000007EB 10000000
      8  3461: 01700101 0006B448 000007E8 10000000
      9  3831: 01700101 0006B454 000007E5 10000000
     10  4211: 01700101 0006B45C 000007E2 10000000
     11  4583: 01700101 0006B468 000007E0 00000000
     12  4959: 01700101 0006B474 000007DD 10000000
     13  5324: 01700101 0006B480 000007DA 10000000
     14  5703: 01700101 0006B488 000007D7 10000000
     15  6076: 01700101 0006B494 000007D5 00000000
     16  6451: 01700101 0006B4A0 000007D2 10000000
     17  6824: 01700101 0006B4AC 000007CF 10000000
     18  7200: 01700101 0006B4B4 000007CC 10000000
     19  7572: 01700101 0006B4C0 000007CA 00000000
  done after 947 polls (rows cut at 20)
SPU write 256 words SyncMode 0 chopped 16 words / 64 clocks (CHCR 01640101): 3219, polls 76, MADR start1024, BCR 00000000
SPU write 256 words SyncMode 0 not chopped: 2141, polls 1
Done.
```

10DPR.txt:

```
===== 10 DPR DMA PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Two channels armed with their DPCR enables off, then one DPCR write: which wrote each of 64 shared words last (O OTC, S SPU, G GPU, . untouched, ? other).
SPU read SyncMode 1, priority 1, OTC priority 5: 3920 clocks, 247 polls
  OOOOOOOOOOOOOOOOSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 5, OTC priority 1: 3927 clocks, 248 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 3, OTC priority 3: 3925 clocks, 248 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 1, OTC priority 5: 720 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
SPU read SyncMode 0, priority 5, OTC priority 1: 721 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 3, OTC priority 3: 715 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
GPU read SyncMode 1, priority 1, OTC priority 5: 268 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 1, priority 5, OTC priority 1: 268 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 1, priority 3, OTC priority 3: 277 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 0, priority 1, OTC priority 5: 257 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 0, priority 5, OTC priority 1: 265 clocks, 1 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
DPCR bits 28-30, CPU priority (channels.txt:105, dmachannels.txt:168):
DPCR 0B3B3B33, SPU write 16 words x 64: 73074, polls 4969; loop of 10000 alone 40030, with the SPU write 40019
DPCR 3B3B3B33, SPU write 16 words x 64: 72637, polls 4935; loop of 10000 alone 40025, with the SPU write 40019
DPCR 7B3B3B33, SPU write 16 words x 64: 73076, polls 4969; loop of 10000 alone 40025, with the SPU write 40019
Done.
```

11DMD.txt:

```
===== 11 DMD DMA MDEC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA0 and DMA1 with the MDEC: tables, then MDEC(1) on blocks of only a DC value (Q 1, DC 20h) and FE00h; DMA1 armed first. Clocks from the DMA0 start. Scale table zero.
Mono 8 bit, 1 block, out 16x1: quant 16 words 107, scale 32 words 68, decode: DMA0 done at 175, DMA1 done at 1013, 30 polls
  output sum 08080800, words 0 and last 80808080 80808080; MDEC status 8204FFFF
  DMA0 MADR start128 BCR 00000020 CHCR 00000201; DMA1 MADR start64 BCR 00000010 CHCR 00000200
Mono 8 bit, 4 blocks, out 16x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040010 CHCR 01000200
Mono 8 bit, 4 blocks, out 32x2: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00020020 CHCR 01000200
Mono 4 bit, 4 blocks, out 8x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999980, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040008 CHCR 01000200
Colour 15 bit, 1 macroblock, out 32x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 66666600, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040020 CHCR 01000200
Colour 24 bit, 1 macroblock, out 32x6: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999900, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00060020 CHCR 01000200
Colour 15 bit, 2 macroblocks, out 32x8: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum CCCCCC00, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00080020 CHCR 01000200
Done.
```

### 28 September 2026 card-h

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/00RUN.txt) · [01DRB.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/01DRB.txt) · [02DOT.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/02DOT.txt) · [03DGL.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/03DGL.txt) · [04DGB.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/04DGB.txt) · [05DSP.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/05DSP.txt) · [06DMW.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/06DMW.txt) · [07DIC.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/07DIC.txt) · [08DCP.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/08DCP.txt) · [09DCH.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/09DCH.txt) · [10DPR.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/10DPR.txt) · [11DMD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/11DMD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010D338 PRId 00000002
```

01DRB.txt:

```
===== 01 DRB DMA READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA registers written and read back, each channel with its DPCR enable off.
1F8010F8h reads 7FE7581A, 1F8010FCh reads 00FFFFFF
Channel 0 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 0 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 0 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 0 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 1 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 1 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 1 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 1 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 2 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 2 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 2 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 2 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 3 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 3 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 3 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 3 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 4 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 4 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 4 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 4 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 5 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 5 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 5 CHCR: FFFFFFFF reads 71770703, 8E88F8FC reads 00000000, 60770703 reads 60770703 (at +Ch 60770703)
Channel 5 CHCR: 10000000 reads 10000000, byte 07 at +2 reads 00070000, 0 reads 00000000
Channel 6 MADR: FFFFFFFF reads 00FFFFFF, 00000003 reads 00000003
Channel 6 BCR: FFFFFFFF reads FFFFFFFF, halfword 1234 at +2 reads 12340000, then byte 56 at +1 reads 12345600
Channel 6 CHCR: FFFFFFFF reads 51000002, 8E88F8FC reads 00000002, 60770703 reads 40000002 (at +Ch 40000002)
Channel 6 CHCR: 10000000 reads 10000002, byte 07 at +2 reads 00000002, 0 reads 00000002
DPCR was 33333B33. FFFFFFFF reads FFFFFFFF, 0 reads 00000000, 80000000 reads 80000000, 70000000 reads 70000000, byte 08 at +3 reads 08000000
DICR was 00000000. 0 reads 00000000, 7F reads 0000003F, 7F80 reads 00000000, FF0000 reads 00FF0000, 80000000 reads 00000000, IRQ3 0
DICR 8000 reads 80008000 with IRQ3 1; 0 reads 00000000; 8000 again IRQ3 0; 8000 while set IRQ3 1
DICR byte 80 at +2 reads 00800000, halfword 0080 at +2 reads 00800000
1F8010F8h reads 7FE7581A, 1F8010FCh reads 00FFFFFF, at +2 halfwords 7FE7 00FF
Done.
```

02DOT.txt:

```
===== 02 DOT DMA OTC TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA6 OTC, CHCR 11000002: system clocks from the CHCR write to the poll that sees bit 24 clear, four times each.
CHCR written 00000002, no transfer: 68, polls 0
OTC     1 words: 89 89 89 89 | polls 1, MADR start0, BCR 00000001, CHCR 00000002, table right
After the first OTC: 1F8010F8h 7FE3585A, 1F8010FCh 00FFFFFF
OTC     2 words: 90 90 90 90 | polls 1, MADR start0, BCR 00000002, CHCR 00000002, table right
OTC     3 words: 91 91 91 91 | polls 1, MADR start0, BCR 00000003, CHCR 00000002, table right
OTC     4 words: 96 92 92 95 | polls 1, MADR start0, BCR 00000004, CHCR 00000002, table right
OTC     8 words: 101 101 101 101 | polls 1, MADR start0, BCR 00000008, CHCR 00000002, table right
OTC    15 words: 108 112 112 118 | polls 1, MADR start0, BCR 0000000F, CHCR 00000002, table right
OTC    16 words: 115 109 119 119 | polls 1, MADR start0, BCR 00000010, CHCR 00000002, table right
OTC    17 words: 110 115 115 114 | polls 1, MADR start0, BCR 00000011, CHCR 00000002, table right
OTC    32 words: 125 128 125 129 | polls 1, MADR start0, BCR 00000020, CHCR 00000002, table right
OTC    64 words: 157 157 157 157 | polls 1, MADR start0, BCR 00000040, CHCR 00000002, table right
OTC   128 words: 221 221 231 221 | polls 1, MADR start0, BCR 00000080, CHCR 00000002, table right
OTC   256 words: 359 359 359 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000002, table right
OTC  1024 words: 1172 1172 1172 1172 | polls 1, MADR start0, BCR 00000400, CHCR 00000002, table right
OTC  4096 words: 4429 4431 4434 4429 | polls 1, MADR start0, BCR 00001000, CHCR 00000002, table right
OTC 16384 words: 17468 17461 17463 17464 | polls 1, MADR start0, BCR 00004000, CHCR 00000002, table right
OTC 65535 words: 69601 69593 69585 69588 | polls 1, MADR start0, BCR 0000FFFF, CHCR 00000002, table right
OTC 65536 words: 69601 69594 69586 69587 | polls 1, MADR start0, BCR 00000000, CHCR 00000002, table right
OTC 256 words, CHCR 51000002 (bit 30): 359 360 359 359 | CHCR after 40000002, table right
OTC BCR 00050010 (16 words, 5 in the upper half): 115 109 109 109 | BCR after 00050010, table right
After: 1F8010F8h 7FE3585A, 1F8010FCh 00FFFFFF
Done.
```

03DGL.txt:

```
===== 03 DGL DMA GPU LISTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA2 linked lists, CHCR 01000401, GP1(04h)=2: clocks from the CHCR write to bit 24 clear, and the polls the CPU made meanwhile. BCR written 00050010 first.
List    1 nodes of   0 NOP words: 90 (1 polls) 90 (1 polls) 90 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    2 nodes of   0 NOP words: 94 (1 polls) 94 (1 polls) 94 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of   0 NOP words: 114 (2 polls) 118 (2 polls) 114 (2 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   0 NOP words: 236 (8 polls) 235 (8 polls) 239 (8 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   64 nodes of   0 NOP words: 733 (34 polls) 728 (33 polls) 723 (33 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List  256 nodes of   0 NOP words: 2689 (133 polls) 2692 (133 polls) 2694 (133 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 1024 nodes of   0 NOP words: 10557 (532 polls) 10560 (532 polls) 10560 (532 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List 2048 nodes of   0 NOP words: 21040 (1064 polls) 21043 (1065 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   1 NOP words: 325 (15 polls) 328 (15 polls) 329 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   2 NOP words: 347 (15 polls) 345 (15 polls) 343 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   4 NOP words: 382 (15 polls) 372 (15 polls) 373 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of   8 NOP words: 450 (15 polls) 440 (15 polls) 446 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  15 NOP words: 572 (15 polls) 568 (15 polls) 568 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  16 NOP words: 584 (15 polls) 569 (15 polls) 584 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  32 NOP words: 858 (15 polls) 864 (15 polls) 864 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of  64 NOP words: 1398 (15 polls) 1394 (15 polls) 1380 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 128 NOP words: 2460 (15 polls) 2474 (15 polls) 2478 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List   16 nodes of 255 NOP words: 4620 (15 polls) 4628 (15 polls) 4612 (15 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    1 nodes of 255 NOP words: 361 (1 polls) 361 (1 polls) 361 (1 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
List    4 nodes of 255 NOP words: 1204 (3 polls) 1204 (3 polls) 1210 (3 polls) | MADR 00FFFFFF, BCR 00050010, CHCR 00000401
Done.
```

04DGB.txt:

```
===== 04 DGB DMA GPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA2 blocks to and from VRAM at 512,256: clocks from the CHCR write to bit 24 clear, twice each; polls, MADR, BCR and CHCR after.
Write SyncMode 1, 16 words x 1: 107 107 | polls 1, MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 130 134 | polls 1, MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 182 178 | polls 3, MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 517 512 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 1855 1870 | polls 63, MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 256: 7153 7126 | polls 257, MADR start16384, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 256: 2978 2983 | polls 193, MADR start1024, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 128: 1732 1733 | polls 127, MADR start1024, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 64: 983 988 | polls 63, MADR start1024, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 32: 677 673 | polls 31, MADR start1024, BCR 00000008, CHCR 00000201
Write SyncMode 1, 32 words x 8: 433 431 | polls 7, MADR start1024, BCR 00000020, CHCR 00000201
Write SyncMode 0, 256 words: 357 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0, 2048 words: 2247 2247 | polls 1, MADR start0, BCR 00000800, CHCR 00000001
Write SyncMode 0 bit 28, 256 words: 363 357 | polls 1, MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 1 bit 28, 16 words x 16: 530 520 | polls 15, MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+2, 16 words x 4: 178 183 | polls 3, MADR start254, BCR 00000010, CHCR 00000201
Write SyncMode 1, MADR+1, 16 words x 4: 178 183 | polls 3, MADR start255, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 1: 109 109 | polls 1, MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 569 569 | polls 19, MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 2235 2237 | polls 91, MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 64: 929 920 | polls 63, MADR start1024, BCR 00000004, CHCR 00000200
Read SyncMode 0, 256 words: 359 359 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 0 bit 28, 256 words: 359 369 | polls 1, MADR start0, BCR 00000100, CHCR 00000000
Read SyncMode 1, MADR+2, 16 words x 4: 179 174 | polls 3, MADR start254, BCR 00000010, CHCR 00000200
Read back words 0-3: 7FFF0000 7FFF0001 7FFF0002 7FFF0003
Done.
```

05DSP.txt:

```
===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 200931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 221 (1) 217 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1493 (89) 1481 (88) 1285 (73) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3841 (250) 3518 (225) 3829 (249) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8543 (572) 8545 (572) 8124 (539) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17767 (1200) 17779 (1201) 17773 (1201) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73069 (4969) 73075 (4969) 73069 (4969) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4082 (265) 4077 (264) 4073 (264) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4863 (330) 4883 (331) 4897 (332) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4515 (301) 4490 (299) 4505 (300) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4476 (299) 4277 (284) 4299 (285) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 220 (1) 227 (2) 227 (2) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3555 (228) 3565 (229) 3928 (257) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17378 (1170) 17806 (1204) 17792 (1202) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73081 (4970) 73094 (4971) 73088 (4970) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4799 (325) 4797 (325) 4811 (326) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 217 (1) 217 (1) 219 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 603 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2141 (1) 2137 (1) 2141 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 605 (1) 601 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 626 (2) 649 (4) 629 (3) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 615 (1) 613 (1) 612 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3840 (250) 3518 (225) 3829 (249) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17782 (1202) 17341 (1167) 17773 (1201) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17807 (1204) 17389 (1171) 17804 (1204) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17598 (1188) 17363 (1169) 17687 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16867 (1215) 16873 (1215) 16887 (1216) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17375 (1170) 17806 (1204) 17792 (1202) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.
```

06DMW.txt:

```
===== 06 DMW DMA MIDWAY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
CHCR, MADR, BCR and DICR polled while a transfer runs: a row each time one changes (t is timer 2's low 16 bits). DICR flags need bit 23 and bit 16+n (dmachannels.txt:184-186); bits 0-6 may give a flag per slice (dmachannels.txt:174-177).
SPU write 16 words x 8, CHCR 01000201, DICR 00000000:
  poll    t: CHCR MADR BCR DICR
      0   555: 01000201 0002A428 00070010 00000000
      3  1672: 01000201 0002A468 00060010 00000000
      6  2731: 01000201 0002A4A8 00050010 00000000
     10  4076: 01000201 0002A4E8 00040010 00000000
     13  5138: 01000201 0002A528 00030010 00000000
     16  6207: 01000201 0002A568 00020010 00000000
     19  7276: 01000201 0002A568 00010010 00000000
     20  7644: 01000201 0002A5A8 00010010 00000000
     23  8719: 00000201 0002A5E8 00000010 00000000
  done after 23 polls
SPU write 16 words x 8, CHCR 11000201 (bit 28):
  poll    t: CHCR MADR BCR DICR
      0   517: 01000201 0002A428 00070010 00000000
      4  1895: 01000201 0002A468 00060010 00000000
      7  2965: 01000201 0002A4A8 00050010 00000000
     10  4033: 01000201 0002A4E8 00040010 00000000
     13  5102: 01000201 0002A4E8 00030010 00000000
     14  5464: 01000201 0002A528 00030010 00000000
     17  6525: 01000201 0002A568 00020010 00000000
     20  7597: 01000201 0002A5A8 00010010 00000000
     24  8950: 00000201 0002A5E8 00000010 00000000
  done after 24 polls
SPU write 16 words x 8, DICR 00900000 (bit 23, bit 20):
  poll    t: CHCR MADR BCR DICR
      0   519: 01000201 0002A428 00070010 00900000
      4  1908: 01000201 0002A468 00060010 00900000
      7  2974: 01000201 0002A4A8 00050010 00900000
     10  4051: 01000201 0002A4E8 00040010 00900000
     13  5119: 01000201 0002A528 00030010 00900000
     17  6478: 01000201 0002A568 00020010 00900000
     20  7540: 01000201 0002A5A8 00010010 00900000
     23  8610: 01000201 0002A5E8 00000010 90900000
     24  8972: 00000201 0002A5E8 00000010 90900000
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010 (bit 4 too, a flag per slice?):
  poll    t: CHCR MADR BCR DICR
      0   519: 01000201 0002A428 00070010 90900010
      4  1900: 01000201 0002A468 00060010 90900010
      7  2977: 01000201 0002A4A8 00050010 90900010
     10  4054: 01000201 0002A4A8 00040010 90900010
     11  4422: 01000201 0002A4E8 00040010 90900010
     13  5205: 01000201 0002A528 00030010 90900010
     17  6561: 01000201 0002A568 00020010 90900010
     20  7617: 01000201 0002A5A8 00010010 90900010
     23  8703: 01000201 0002A5A8 00000010 90900010
     24  9071: 00000201 0002A5E8 00000010 90900010
  done after 24 polls
  I_STAT bit 3 after: 1
SPU write 16 words x 8, DICR 00900010, I_STAT bit 3 in the last column:
  poll    t: CHCR MADR BCR I_STAT&8
      0   516: 01000201 0002A428 00070010 00000008
      4  1901: 01000201 0002A468 00060010 00000008
      7  2967: 01000201 0002A4A8 00050010 00000008
     10  4039: 01000201 0002A4E8 00040010 00000008
     13  5106: 01000201 0002A528 00030010 00000008
     17  6462: 01000201 0002A568 00020010 00000008
     20  7518: 01000201 0002A5A8 00010010 00000008
     23  8604: 01000201 0002A5A8 00000010 00000008
     24  8972: 00000201 0002A5E8 00000010 00000008
  done after 24 polls
SPU read 16 words x 8, CHCR 01000200:
  poll    t: CHCR MADR BCR DICR
      0   513: 01000200 0002A428 00070010 00000000
      4  1901: 01000200 0002A468 00060010 00000000
      7  2959: 01000200 0002A4A8 00050010 00000000
     10  4018: 01000200 0002A4E8 00040010 00000000
     13  5091: 01000200 0002A4E8 00030010 00000000
     14  5455: 01000200 0002A528 00030010 00000000
     17  6515: 01000200 0002A568 00020010 00000000
     20  7584: 01000200 0002A5A8 00010010 00000000
     23  8656: 00000200 0002A5E8 00000010 00000000
  done after 23 polls
GPU write 16 words x 8 to VRAM, CHCR 01000201:
  poll    t: CHCR MADR BCR DICR
      0   542: 01000201 0006B5E8 00000010 00000000
      1   934: 00000201 0006B5E8 00000010 00000000
  done after 1 polls
GPU list 8 nodes of 15 NOPs, DICR 00840004 (bit 2, a flag per entry?):
  list at 026248, nodes 64 bytes apart
  poll    t: CHCR MADR BCR DICR
      0   578: 01000401 00FFFFFF 00000000 84840004
      1   972: 00000401 00FFFFFF 00000000 84840004
  done after 1 polls
Done.
```

07DIC.txt:

```
===== 07 DIC DMA DICR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DICR around a 16 word OTC (channel 6: enable bit 22, flag bit 30). psx-spx sets the flag only with bit 23 and bit 22 (dmachannels.txt:184-186), nocash with bit 22 alone (channels.txt:122-123). IRQ3 is I_STAT bit 3, acknowledged before each OTC.
DICR 00000000 reads 00000000 (IRQ3 0); after OTC 00000000, IRQ3 0
DICR 00400000 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00800000 reads 00800000 (IRQ3 0); after OTC 00800000, IRQ3 0
DICR 00C00000 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00C00040 reads 00C00000 (IRQ3 0); after OTC C0C00000, IRQ3 1
DICR 00400040 reads 00400000 (IRQ3 0); after OTC 40400000, IRQ3 0
DICR 00BF0000 reads 00BF0000 (IRQ3 0); after OTC 00BF0000, IRQ3 0
DICR 00FF0000 reads 00FF0000 (IRQ3 0); after OTC C0FF0000, IRQ3 1
DICR 00008000 reads 80008000 (IRQ3 1); after OTC 80008000, IRQ3 0
DICR 00C08000 reads 80C08000 (IRQ3 1); after OTC C0C08000, IRQ3 0
DICR 0000003F reads 0000003F (IRQ3 0); after OTC 0000003F, IRQ3 0
A flag, then its enables taken away:
  after OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  bit 22 off: wrote 00800000, reads C0800000, IRQ3 0
  bit 23 off too: wrote 00000000, reads 40000000, IRQ3 0
  bit 23 on: wrote 00800000, reads C0800000, IRQ3 1
  bit 23 on again: wrote 00800000, reads C0800000, IRQ3 0
  flag acknowledged: wrote 40800000, reads 00800000, IRQ3 0
  bit 31 written: wrote 80800000, reads 00800000, IRQ3 0
Flag with bit 22 alone, then bit 23:
  after OTC: wrote 00400000, reads 40400000, IRQ3 0
  bit 23 on: wrote 00C00000, reads C0C00000, IRQ3 1
Bit 15 set, then a flag:
  bit 15 and 22 and 23: wrote 00C08000, reads 80C08000, IRQ3 1
  after OTC: wrote 00C08000, reads C0C08000, IRQ3 0
  bit 15 off: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
Two flags, one acknowledged:
  after first OTC: wrote 00C00000, reads C0C00000, IRQ3 1
  after second OTC: wrote 00C00000, reads C0C00000, IRQ3 0
  flag acknowledged: wrote 40C00000, reads 00C00000, IRQ3 0
  after third OTC: wrote 00C00000, reads C0C00000, IRQ3 1
OTC with bit 28 alone (no start, otc.c) and DICR 00C00000:
  after: wrote 00C00000, reads 00C00000, IRQ3 0
Done.
```

08DCP.txt:

```
===== 08 DCP DMA CPU DURING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
A loop from the i-cache started right after the CHCR write that starts a transfer, then a timer 2 read: clocks alone and with the transfer. A loop turn is its body, addiu, bnez, nop.
OTC 16384 words (CHCR 11000002):
  registers n=1: alone 23, with the transfer 17402
  registers n=100: alone 419, with the transfer 17397
  registers n=1000: alone 4019, with the transfer 17408
  registers n=4000: alone 16019, with the transfer 17402
  registers n=10000: alone 40019, with the transfer 40019
  registers n=20000: alone 80019, with the transfer 80019
  scratchpad loads n=100: alone 419, with the transfer 17407
  scratchpad loads n=1000: alone 4019, with the transfer 17408
  scratchpad loads n=4000: alone 16019, with the transfer 17408
  scratchpad loads n=10000: alone 40019, with the transfer 40019
  scratchpad loads n=20000: alone 80019, with the transfer 80019
  RAM stores n=100: alone 423, with the transfer 17801
  RAM stores n=1000: alone 4019, with the transfer 21390
  RAM stores n=4000: alone 16019, with the transfer 33391
  RAM stores n=10000: alone 40019, with the transfer 57402
  RAM loads n=100: alone 930, with the transfer 18309
  RAM loads n=1000: alone 9158, with the transfer 26542
  RAM loads n=4000: alone 36586, with the transfer 53970
  RAM loads n=10000: alone 91449, with the transfer 108825
  CHCR loads n=100: alone 719, with the transfer 18095
  CHCR loads n=1000: alone 7019, with the transfer 24394
  CHCR loads n=4000: alone 28019, with the transfer 45400
  CHCR loads n=10000: alone 70019, with the transfer 87400
SPU write 16 words x 64 (CHCR 01000201):
  registers n=100: alone 419, with the transfer 419 (still busy after)
  registers n=1000: alone 4019, with the transfer 4019 (still busy after)
  registers n=4000: alone 16019, with the transfer 16019 (still busy after)
  registers n=10000: alone 40019, with the transfer 40019 (still busy after)
  RAM loads n=100: alone 926, with the transfer 1067 (still busy after)
  RAM loads n=1000: alone 9158, with the transfer 10478 (still busy after)
  RAM loads n=4000: alone 36586, with the transfer 41354 (still busy after)
  CHCR loads n=100: alone 719, with the transfer 850 (still busy after)
  CHCR loads n=1000: alone 7019, with the transfer 7952 (still busy after)
  CHCR loads n=4000: alone 28019, with the transfer 31756 (still busy after)
GPU write 2048 words SyncMode 0 chopped, DMA window 1 word, CPU window 128 clocks (CHCR 01700101):
  registers n=100: alone 416, with the transfer 432 (still busy after) (clock/8)
  registers n=1000: alone 4016, with the transfer 4032 (still busy after) (clock/8)
  registers n=4000: alone 16016, with the transfer 16040 (still busy after) (clock/8)
  registers n=10000: alone 40024, with the transfer 40032 (still busy after) (clock/8)
  RAM loads n=100: alone 928, with the transfer 984 (still busy after) (clock/8)
  RAM loads n=1000: alone 9160, with the transfer 9232 (still busy after) (clock/8)
  RAM loads n=4000: alone 36584, with the transfer 36800 (still busy after) (clock/8)
GPU write 2048 words SyncMode 0 not chopped (CHCR 01000001):
  registers n=100: alone 419, with the transfer 2205
  registers n=1000: alone 4019, with the transfer 4036
  registers n=4000: alone 16019, with the transfer 16036
  registers n=10000: alone 40019, with the transfer 40036
Done.
```

09DCH.txt:

```
===== 09 DCH DMA CHOP SHARE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
GPU write 2048 words SyncMode 0 chopped (CHCR 01xx0101), polling CHCR: clocks, polls (the CPU's share), MADR, BCR, CHCR after. Not chopped for scale first.
Not chopped: 2247, polls 1
DMA window   1 words, CPU window   1 clocks: 16720, polls 1040, MADR start8192, BCR 00000000, CHCR 00000101
DMA window   1 words, CPU window   4 clocks: 23376, polls 1548, MADR start8192, BCR 00000000, CHCR 00200101
DMA window   1 words, CPU window  16 clocks: 47888, polls 3412, MADR start8192, BCR 00000000, CHCR 00400101
DMA window   1 words, CPU window  32 clocks: 80680, polls 6141, MADR start8192, BCR 00000000, CHCR 00500101
DMA window   1 words, CPU window 128 clocks: 276648, polls 20471, MADR start8192, BCR 00000000, CHCR 00700101
DMA window   2 words, CPU window   1 clocks: 9440, polls 513, MADR start8192, BCR 00000000, CHCR 00010101
DMA window   2 words, CPU window   4 clocks: 13400, polls 1023, MADR start8192, BCR 00000000, CHCR 00210101
DMA window   2 words, CPU window  16 clocks: 24640, polls 1706, MADR start8192, BCR 00000000, CHCR 00410101
DMA window   2 words, CPU window  32 clocks: 41000, polls 3069, MADR start8192, BCR 00000000, CHCR 00510101
DMA window   2 words, CPU window 128 clocks: 139208, polls 10231, MADR start8192, BCR 00000000, CHCR 00710101
DMA window   4 words, CPU window   1 clocks: 5864, polls 266, MADR start8192, BCR 00000000, CHCR 00020101
DMA window   4 words, CPU window   4 clocks: 7352, polls 511, MADR start8192, BCR 00000000, CHCR 00220101
DMA window   4 words, CPU window  16 clocks: 13472, polls 1022, MADR start8192, BCR 00000000, CHCR 00420101
DMA window   4 words, CPU window  32 clocks: 21856, polls 1533, MADR start8192, BCR 00000000, CHCR 00520101
DMA window   4 words, CPU window 128 clocks: 70704, polls 5111, MADR start8192, BCR 00000000, CHCR 00720101
DMA window  16 words, CPU window   1 clocks: 3136, polls 127, MADR start8192, BCR 00000000, CHCR 00040101
DMA window  16 words, CPU window   4 clocks: 3504, polls 127, MADR start8192, BCR 00000000, CHCR 00240101
DMA window  16 words, CPU window  16 clocks: 5032, polls 254, MADR start8192, BCR 00000000, CHCR 00440101
DMA window  16 words, CPU window  32 clocks: 7088, polls 381, MADR start8192, BCR 00000000, CHCR 00540101
DMA window  16 words, CPU window 128 clocks: 19280, polls 1271, MADR start8192, BCR 00000000, CHCR 00740101
DMA window 128 words, CPU window   1 clocks: 2352, polls 15, MADR start8192, BCR 00000000, CHCR 00070101
DMA window 128 words, CPU window   4 clocks: 2408, polls 15, MADR start8192, BCR 00000000, CHCR 00270101
DMA window 128 words, CPU window  16 clocks: 2576, polls 30, MADR start8192, BCR 00000000, CHCR 00470101
DMA window 128 words, CPU window  32 clocks: 2792, polls 45, MADR start8192, BCR 00000000, CHCR 00570101
DMA window 128 words, CPU window 128 clocks: 4240, polls 151, MADR start8192, BCR 00000000, CHCR 00770101
Chopped 1 word / 128 clocks, as it runs:
  poll    t: CHCR MADR BCR GPUSTAT&1C000000
      0   438: 01700101 0006B3EC 000007FF 10000000
      1   845: 01700101 0006B3FC 000007FB 10000000
      2  1211: 01700101 0006B404 000007F8 10000000
      3  1585: 01700101 0006B410 000007F6 00000000
      4  1963: 01700101 0006B41C 000007F3 10000000
      5  2340: 01700101 0006B428 000007F0 10000000
      6  2712: 01700101 0006B430 000007ED 10000000
      7  3086: 01700101 0006B43C 000007EB 00000000
      8  3462: 01700101 0006B448 000007E8 10000000
      9  3829: 01700101 0006B454 000007E5 10000000
     10  4203: 01700101 0006B45C 000007E2 10000000
     11  4580: 01700101 0006B468 000007E0 00000000
     12  4957: 01700101 0006B474 000007DD 10000000
     13  5331: 01700101 0006B480 000007DA 10000000
     14  5709: 01700101 0006B488 000007D7 10000000
     15  6083: 01700101 0006B494 000007D5 10000000
     16  6460: 01700101 0006B4A0 000007D2 10000000
     17  6827: 01700101 0006B4AC 000007CF 10000000
     18  7198: 01700101 0006B4B4 000007CC 10000000
     19  7575: 01700101 0006B4C0 000007CA 00000000
  done after 949 polls (rows cut at 20)
SPU write 256 words SyncMode 0 chopped 16 words / 64 clocks (CHCR 01640101): 3206, polls 76, MADR start1024, BCR 00000000
SPU write 256 words SyncMode 0 not chopped: 2138, polls 1
Done.
```

10DPR.txt:

```
===== 10 DPR DMA PRIORITY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Two channels armed with their DPCR enables off, then one DPCR write: which wrote each of 64 shared words last (O OTC, S SPU, G GPU, . untouched, ? other).
SPU read SyncMode 1, priority 1, OTC priority 5: 3916 clocks, 248 polls
  OOOOOOOOOOOOOOOOSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 5, OTC priority 1: 3928 clocks, 249 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 1, priority 3, OTC priority 3: 3918 clocks, 247 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 1, OTC priority 5: 723 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
SPU read SyncMode 0, priority 5, OTC priority 1: 726 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
SPU read SyncMode 0, priority 3, OTC priority 3: 727 clocks, 1 polls
  SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
GPU read SyncMode 1, priority 1, OTC priority 5: 262 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 1, priority 5, OTC priority 1: 277 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 1, priority 3, OTC priority 3: 277 clocks, 2 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
GPU read SyncMode 0, priority 1, OTC priority 5: 258 clocks, 1 polls
  OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GPU read SyncMode 0, priority 5, OTC priority 1: 265 clocks, 1 polls
  GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG
DPCR bits 28-30, CPU priority (channels.txt:105, dmachannels.txt:168):
DPCR 0B3B3B33, SPU write 16 words x 64: 73075, polls 4969; loop of 10000 alone 40025, with the SPU write 40019
DPCR 3B3B3B33, SPU write 16 words x 64: 73074, polls 4969; loop of 10000 alone 40025, with the SPU write 40019
DPCR 7B3B3B33, SPU write 16 words x 64: 73082, polls 4970; loop of 10000 alone 40025, with the SPU write 40019
Done.
```

11DMD.txt:

```
===== 11 DMD DMA MDEC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA0 and DMA1 with the MDEC: tables, then MDEC(1) on blocks of only a DC value (Q 1, DC 20h) and FE00h; DMA1 armed first. Clocks from the DMA0 start. Scale table zero.
Mono 8 bit, 1 block, out 16x1: quant 16 words 107, scale 32 words 78, decode: DMA0 done at 165, DMA1 done at 1003, 30 polls
  output sum 08080800, words 0 and last 80808080 80808080; MDEC status 8204FFFF
  DMA0 MADR start128 BCR 00000020 CHCR 00000201; DMA1 MADR start64 BCR 00000010 CHCR 00000200
Mono 8 bit, 4 blocks, out 16x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040010 CHCR 01000200
Mono 8 bit, 4 blocks, out 32x2: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 33333300, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00020020 CHCR 01000200
Mono 4 bit, 4 blocks, out 8x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999980, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040008 CHCR 01000200
Colour 15 bit, 1 macroblock, out 32x4: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 66666600, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00040020 CHCR 01000200
Colour 24 bit, 1 macroblock, out 32x6: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum 99999900, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00060020 CHCR 01000200
Colour 15 bit, 2 macroblocks, out 32x8: quant 16 words timeout, scale 32 words timeout, decode: DMA0 done at timeout, DMA1 done at timeout, 200001 polls
  output sum CCCCCC00, words 0 and last CCCCCCCC CCCCCCCC; MDEC status A004000D
  DMA0 MADR start0 BCR 00010020 CHCR 01000201; DMA1 MADR start0 BCR 00080020 CHCR 01000200
Done.
```

### 28 September 2026 card-h dmatime_drq1

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq1/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq1/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80023150 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off:
  GP1(04h)=0, CHCR 01000201 BCR 00040010: polled up to 20000 times, still busy; MADR start0 BCR 00040010 CHCR 01000201
  then GP1(04h)=2: done; MADR start256 BCR 00000010 CHCR 00000201
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq2

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq2/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq2/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off:
  GP1(04h)=0, CHCR 01000001 BCR 00000040: polled up to 20000 times, still busy; MADR start0 BCR 00000040 CHCR 01000001
  then GP1(04h)=2: done; MADR start0 BCR 00000040 CHCR 00000001
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq3

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq3/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq3/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80021028 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off:
  GP1(04h)=0, CHCR 11000001 BCR 00000040: polled up to 20000 times, done; MADR start0 BCR 00000040 CHCR 00000001
  then GP1(04h)=2: done; MADR start0 BCR 00000040 CHCR 00000001
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq4

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq4/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq4/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80110FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 01000201: polled up to 20000 times, still busy; MADR start0 BCR 00040010 SPUSTAT 0000
  then mode DMA write: done; MADR start256 BCR 00000010 SPUSTAT 0020
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq5

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq5/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq5/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 01000001: polled up to 20000 times, still busy; MADR start0 BCR 00000040 SPUSTAT 0000
  then mode DMA write: done; MADR start0 BCR 00000040 SPUSTAT 0020
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq6

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq6/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq6/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80110FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop:
  SPUCNT mode stop, CHCR 11000001: polled up to 20000 times, done; MADR start0 BCR 00000040 SPUSTAT 0000
  then mode DMA write: done; MADR start0 BCR 00000040 SPUSTAT 0800
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq7

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq7/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq7/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80020FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh:
  list of 4 ending FFFFFF: 116, MADR 00FFFFFF, CHCR 00000401, DICR 00000000, IRQ3 0
  DICR with bit 15 written 0: 00000000
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq8

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq8/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq8/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80110FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh:
  list of 4 ending FFFFFE: 133, MADR 00FFFFFE, CHCR 00000401, DICR 80008000, IRQ3 1
  DICR with bit 15 written 0: 00000000
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq9

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq9/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq9/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h:
  list of 4 ending 800000: 129, MADR 00800000, CHCR 00000401, DICR 80008000, IRQ3 1
  DICR with bit 15 written 0: 00000000
OTC of 3 words from address 4: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_drq10

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq10/00RUN.txt) · [01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq10/01DRQ.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DRQ.txt:

```
===== 01 DRQ DMA NO REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Transfers whose device is not asking, and the ends of the address range.
GPU SyncMode 1 with the GPU request off: not run in this table.
GPU SyncMode 0 with the GPU request off: not run in this table.
GPU SyncMode 0 bit 28 with the GPU request off: not run in this table.
SPU SyncMode 1 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 with SPU transfer mode stop: not run in this table.
SPU SyncMode 0 bit 28 with SPU transfer mode stop: not run in this table.
GPU list ended by FFFFFFh: not run in this table.
GPU list ended by FFFFFEh: not run in this table.
GPU list ended by 800000h: not run in this table.
OTC of 3 words from address 4:
  word 4 00000000, word 0 00FFFFFC, word 1FFFFCh 22222222 (was 22222222); MADR 00000004 CHCR 00000002
Done.
```

### 28 September 2026 card-h dmatime_odd1

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd1/00RUN.txt) · [01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd1/01DOD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DOD.txt:

```
===== 01 DOD DMA ODD BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR bits 8, 29 and 30 where psx-spx leaves them open.
Bit 30:
  GPU write 16 x 16: CHCR 01000201 494, 41000201 480, CHCR after 40000201
  SPU write 16 x 16: CHCR 01000201 17700, 41000201 17356, CHCR after 40000201
Bits 28 and 29 in SyncMode 1: not run in this table.
Bit 8 in a linked list: not run in this table.
Bit 29 in a forced burst: not run in this table.
Bit 8 in SyncMode 1: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_odd2

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd2/00RUN.txt) · [01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd2/01DOD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DOD.txt:

```
===== 01 DOD DMA ODD BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR bits 8, 29 and 30 where psx-spx leaves them open.
Bit 30: not run in this table.
Bits 28 and 29 in SyncMode 1:
  poll    t: CHCR MADR BCR DICR
      0  1482: 20000201 0002A3C0 00000010 90900000
  done after 0 polls
Bit 8 in a linked list: not run in this table.
Bit 29 in a forced burst: not run in this table.
Bit 8 in SyncMode 1: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_odd3

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd3/00RUN.txt) · [01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd3/01DOD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80020FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
```

01DOD.txt:

```
===== 01 DOD DMA ODD BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR bits 8, 29 and 30 where psx-spx leaves them open.
Bit 30: not run in this table.
Bits 28 and 29 in SyncMode 1: not run in this table.
Bit 8 in a linked list:
  16 nodes of 1, CHCR 01000401: 308, 01000501: 310, MADR 00FFFFFF CHCR 00000501 GPUSTAT 5602220A
Bit 29 in a forced burst: not run in this table.
Bit 8 in SyncMode 1: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_odd4

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd4/00RUN.txt) · [01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd4/01DOD.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80110FE0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC4 PRId 00000002
```

01DOD.txt:

```
===== 01 DOD DMA ODD BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CHCR bits 8, 29 and 30 where psx-spx leaves them open.
Bit 30: not run in this table.
Bits 28 and 29 in SyncMode 1: not run in this table.
Bit 8 in a linked list: not run in this table.
Bit 29 in a forced burst:
  GPU SyncMode 0, CHCR 31000001: polled up to 20000 times, done; MADR start0 BCR 00000100 CHCR 30000001
Bit 8 in SyncMode 1: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_pio1

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio1/00RUN.txt) · [01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio1/01DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 8001D3C4 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8001DF30 PRId 00000002
```

01DPI.txt:

```
===== 01 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words:
  CHCR 01000200 BCR 00010004: busy after 20000 polls, 109029; MADR start0 BCR 00010004 CHCR 01000200; words 0-1 CCCCCCCC CCCCCCCC
SyncMode 0, 4 words, no bit 28: not run in this table.
SyncMode 0 bit 28, 1 word: not run in this table.
SyncMode 0 bit 28, 16 words: not run in this table.
SyncMode 0 bit 28, 64 words: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_pio2

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio2/00RUN.txt) · [01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio2/01DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BB0 PRId 00000002
```

01DPI.txt:

```
===== 01 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words: not run in this table.
SyncMode 0, 4 words, no bit 28:
  CHCR 01000000 BCR 00000004: busy after 20000 polls, 109026; MADR start0 BCR 00000004 CHCR 01000000; words 0-1 CCCCCCCC CCCCCCCC
SyncMode 0 bit 28, 1 word: not run in this table.
SyncMode 0 bit 28, 16 words: not run in this table.
SyncMode 0 bit 28, 64 words: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_pio3

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio3/00RUN.txt) · [01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio3/01DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BB0 PRId 00000002
```

01DPI.txt:

```
===== 01 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words: not run in this table.
SyncMode 0, 4 words, no bit 28: not run in this table.
SyncMode 0 bit 28, 1 word:
  CHCR 11000000 BCR 00000001: done at 111; MADR start0 BCR 00000001 CHCR 00000000; words 0-1 FFFFFFFF CCCCCCCC
SyncMode 0 bit 28, 16 words: not run in this table.
SyncMode 0 bit 28, 64 words: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_pio4

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio4/00RUN.txt) · [01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio4/01DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80110FCC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BB0 PRId 00000002
```

01DPI.txt:

```
===== 01 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words: not run in this table.
SyncMode 0, 4 words, no bit 28: not run in this table.
SyncMode 0 bit 28, 1 word: not run in this table.
SyncMode 0 bit 28, 16 words:
  CHCR 11000000 BCR 00000010: done at 411; MADR start0 BCR 00000010 CHCR 00000000; words 0-1 FFFFFFFF FFFFFFFF
SyncMode 0 bit 28, 64 words: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_pio5

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio5/00RUN.txt) · [01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio5/01DPI.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80021014 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BB0 PRId 00000002
```

01DPI.txt:

```
===== 01 DPI DMA PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA5, expansion port to RAM. EXP1 delay/size 0013243F, base 1F000000.
SyncMode 1, 4 words: not run in this table.
SyncMode 0, 4 words, no bit 28: not run in this table.
SyncMode 0 bit 28, 1 word: not run in this table.
SyncMode 0 bit 28, 16 words: not run in this table.
SyncMode 0 bit 28, 64 words:
  CHCR 11000000 BCR 00000040: done at 1388; MADR start0 BCR 00000040 CHCR 00000000; words 0-1 FFFFFFFF FFFFFFFF
Done.
```

### 28 September 2026 card-h dmatime_unk1

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk1/00RUN.txt) · [01DUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk1/01DUN.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8001E498 PRId 00000002
```

01DUN.txt:

```
===== 01 DUN DMA F8 FC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
1F8010F8h and 1F8010FCh, "might be remaining length and address?" (channels.txt:132-141): read at the start 3FF33A0A 00FFFFFF, while an SPU write runs, after transfers, then written.
While SPU write 16 words x 16 runs:
  poll    t: CHCR F8 FC MADR
      0   552: 01000201 3FF30A53 00FFFFFF 0011A200
      3  1654: 01000201 3FF30A53 00FFFFFF 0011A240
      6  2722: 01000201 3FF30A53 00FFFFFF 0011A280
     10  4081: 01000201 3FF30A53 00FFFFFF 0011A2C0
     13  5143: 01000201 3FF30A53 00FFFFFF 0011A300
     16  6212: 01000201 3FF30A53 00FFFFFF 0011A340
     19  7282: 01000201 3FF30A53 00FFFFFF 0011A380
     23  8628: 01000201 3FF30A53 00FFFFFF 0011A3C0
     26  9698: 01000201 3FF30A53 00FFFFFF 0011A400
     29 10774: 01000201 3FF30A53 00FFFFFF 0011A440
     32 11842: 01000201 3FF30A53 00FFFFFF 0011A480
     36 13191: 01000201 3FF30A53 00FFFFFF 0011A4C0
     39 14259: 01000201 3FF30A53 00FFFFFF 0011A500
     43 15601: 01000201 3FF30A53 00FFFFFF 0011A540
     46 16663: 01000201 3FF30A53 00FFFFFF 0011A580
     49 17732: 01000201 3FF30A53 00FFFFFF 0011A5C0
     50 18098: 00000201 3FF30A53 00FFFFFF 0011A5C0
  done after 50 polls
After transfers: not run in this table.
Written: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_unk2

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk2/00RUN.txt) · [01DUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk2/01DUN.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC0 PRId 00000002
```

01DUN.txt:

```
===== 01 DUN DMA F8 FC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
1F8010F8h and 1F8010FCh, "might be remaining length and address?" (channels.txt:132-141): read at the start 3FF31A13 00FFFFFF, while an SPU write runs, after transfers, then written.
While SPU write 16 words x 16 runs: not run in this table.
After transfers:
  after an OTC: F8 3FE32A5C FC 00FFFFFF
  after an SPU read: F8 3FE70A9C FC 00FFFFFF
  after an OTC from MADR+2: F8 3FE31A9C FC 00FFFFFF
Written: not run in this table.
Done.
```

### 28 September 2026 card-h dmatime_unk3

Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk3/00RUN.txt) · [01DUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_unk3/01DUN.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80021024 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC0 PRId 00000002
```

01DUN.txt:

```
===== 01 DUN DMA F8 FC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
1F8010F8h and 1F8010FCh, "might be remaining length and address?" (channels.txt:132-141): read at the start 3FE72A1C 00FFFFFF, while an SPU write runs, after transfers, then written.
While SPU write 16 words x 16 runs: not run in this table.
After transfers: not run in this table.
Written:
  F8 was 3FE72A1C: 0 reads 3FE72A1C, FFFFFFFF reads 3FE72A1C; FC was 00FFFFFF: 0 reads 00FFFFFF, FFFFFFFF reads 00FFFFFF; now 3FE72A1C 00FFFFFF
Done.
```

### 5 October 2026 card-q

Raw output: [00RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/dmatime_lsn/00RUN.txt) · [01LSN.txt](/tests/raw/20261005T0000Z-5501a-card-q/dmatime_lsn/01LSN.txt)

00RUN.txt:

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 8001FD9C DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 80020950 PRId 00000002
```

01LSN.txt:

```
===== 01 LSN DMA SHORT LISTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA2 lists of n nodes of k GP0(00h) words ending FFFFFFh, GP1(04h)=2: clocks from the CHCR
write to bit 24 clear, three runs; with DICR 7F000000h written first, then without (row 112).
DICR written, 1 nodes of 0:  75  65  65
DICR written, 2 nodes of 0:  85  82  82
DICR written, 3 nodes of 0:  85  85  85
DICR written, 4 nodes of 0:  98  98  98
DICR written, 1 nodes of 1:  68  68  69
DICR written, 2 nodes of 1:  95  97  91
DICR written, 3 nodes of 1:  97  101  103
DICR written, 4 nodes of 1:  113  113  113
DICR written, 1 nodes of 2:  69  69  69
DICR written, 2 nodes of 2:  93  93  93
DICR written, 3 nodes of 2:  100  100  106
DICR written, 4 nodes of 2:  117  117  117
no DICR write, 1 nodes of 0:  65  65  65
no DICR write, 2 nodes of 0:  85  82  82
no DICR write, 3 nodes of 0:  85  85  85
no DICR write, 4 nodes of 0:  98  98  98
no DICR write, 1 nodes of 1:  68  68  74
no DICR write, 2 nodes of 1:  97  91  91
no DICR write, 3 nodes of 1:  102  103  97
no DICR write, 4 nodes of 1:  118  117  113
no DICR write, 1 nodes of 2:  69  69  69
no DICR write, 2 nodes of 2:  93  93  93
no DICR write, 3 nodes of 2:  100  100  100
no DICR write, 4 nodes of 2:  117  117  117
Done.
```

## References

[^run]: SCPH-5501 output: [dmatime_safe/02DOT.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/02DOT.txt).
[^h-dot]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/02DOT.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/02DOT.txt).
[^h-drb]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/01DRB.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/01DRB.txt).
[^c-dun]: Run 20260927T0000Z-5501a-card-c: [dmatime_rest/01DUN.txt](/tests/raw/20260927T0000Z-5501a-card-c/dmatime_rest/01DUN.txt).
[^h-drq10]: Run 20260928T0000Z-5501a-card-h: [dmatime_drq10/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq10/01DRQ.txt).
[^h-dgl]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/03DGL.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/03DGL.txt).
[^h-drq789]: Run 20260928T0000Z-5501a-card-h: [dmatime_drq7/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq7/01DRQ.txt), [dmatime_drq8/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq8/01DRQ.txt), [dmatime_drq9/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq9/01DRQ.txt).
[^h-dgb]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/04DGB.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/04DGB.txt).
[^h-drq123]: Run 20260928T0000Z-5501a-card-h: [dmatime_drq1/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq1/01DRQ.txt), [dmatime_drq2/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq2/01DRQ.txt), [dmatime_drq3/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq3/01DRQ.txt).
[^h-dsp]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/05DSP.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/05DSP.txt).
[^h-drq456]: Run 20260928T0000Z-5501a-card-h: [dmatime_drq4/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq4/01DRQ.txt), [dmatime_drq5/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq5/01DRQ.txt), [dmatime_drq6/01DRQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_drq6/01DRQ.txt).
[^h-dmw]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/06DMW.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/06DMW.txt).
[^h-dcp]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/08DCP.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/08DCP.txt).
[^h-dch]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/09DCH.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/09DCH.txt).
[^h-dpr]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/10DPR.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/10DPR.txt).
[^h-dic]: Run 20260928T0000Z-5501a-card-h: [dmatime_safe/07DIC.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_safe/07DIC.txt).
[^h-odd]: Run 20260928T0000Z-5501a-card-h: [dmatime_odd1/01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd1/01DOD.txt), [dmatime_odd3/01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd3/01DOD.txt), [dmatime_odd4/01DOD.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_odd4/01DOD.txt).
[^b-dod]: Run 20260927T0000Z-5501a-card-b: [dmatime/13DOD.txt](/tests/raw/20260927T0000Z-5501a-card-b/dmatime/13DOD.txt).
[^c-dpi]: Runs 20260927T0000Z-5501a-card-c and 20260928T0000Z-5501a-card-h: [dmatime_rest/02DPI.txt](/tests/raw/20260927T0000Z-5501a-card-c/dmatime_rest/02DPI.txt), [dmatime_pio1/01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio1/01DPI.txt), [dmatime_pio5/01DPI.txt](/tests/raw/20260928T0000Z-5501a-card-h/dmatime_pio5/01DPI.txt).
[^q-lsn]: Run 20261005T0000Z-5501a-card-q: [dmatime_lsn/01LSN.txt](/tests/raw/20261005T0000Z-5501a-card-q/dmatime_lsn/01LSN.txt).