DMA Timing: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The groups that can hang the console run last, each in a separate program image, so that a hang loses only that row. The variants dmatime_drq1 to drq10, odd1 to odd4, pio1 to pio5 and unk1 to unk3 each hold one such row.[^run] | The groups that can hang the console run last, each in a separate program image, so that a hang loses only that row. The variants dmatime_drq1 to drq10, odd1 to odd4, pio1 to pio5 and unk1 to unk3 each hold one such row.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | |||
| ## Results | ## Results | ||
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| 64 words were written to sound RAM and read back. After SyncMode 1 transfers 56 words matched, and after SyncMode 0 transfers 16 matched.[^h-dsp] | 64 words were written to sound RAM and read back. After SyncMode 1 transfers 56 words matched, and after SyncMode 0 transfers 16 matched.[^h-dsp] | ||
| − | With the SPU transfer mode set to stop, a SyncMode 0 or 1 transfer stays busy until the mode is set to DMA write. With CHCR bit 28 it runs to the end.[^h-drq456] | + | With the SPU transfer mode set to stop, a SyncMode 0 or 1 transfer stays busy until the mode is set to DMA write. With CHCR bit 28 it runs to the end.[^h-drq456] During a SyncMode 1 SPU write, MADR advances and BCR counts down one block at a time, and the CPU polls between blocks.[^h-dmw] |
| − | During a SyncMode 1 SPU write, MADR advances and BCR counts down one block at a time, and the CPU polls between blocks.[^h-dmw] | ||
| − | |||
| ### CPU During a Transfer | ### CPU During a Transfer | ||
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| ### Priority | ### Priority | ||
| − | Two channels were armed with their DPCR enables off and then started by one DPCR write, both writing the same 64 words. In SyncMode 0 the channel with the higher priority (the lower number) ran first and the other channel's data was left in memory. At equal priority, channel 6 ran before channel 4 and before channel 2.[^h-dpr] | + | Two channels were armed with their DPCR enables off and then started by one DPCR write, both writing the same 64 words. In SyncMode 0 the channel with the higher priority (the lower number) ran first and the other channel's data was left in memory. At equal priority, channel 6 ran before channel 4 and before channel 2.[^h-dpr] DPCR bits 28 to 30 made no difference to an SPU write or to a CPU loop running beside it.[^h-dpr] |
| − | DPCR bits 28 to 30 made no difference to an SPU write or to a CPU loop running beside it.[^h-dpr] | ||
| − | |||
| ### DICR Interrupts | ### DICR Interrupts | ||