GPUSTAT DMA Bits: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ## Overview | ## Overview | ||
| − | The program draws by CPU writes to GP0 and by a [DMA](/hardware/dma/) list. It also draws by DMA in sync mode 1 with GP1(04h) direction 1 (FIFO) and with direction 2 (CPU to GP0). Before, during and after each draw it checks bits 25 to 30 of [GPUSTAT](/hardware/gpu/gpustat/) against its own expected values.[^src] | + | The program draws by CPU writes to GP0 and by a [DMA](/hardware/dma/) list. It also draws by DMA in sync mode 1 with GP1(04h) direction 1 (FIFO) and with direction 2 (CPU to GP0). Before, during and after each draw it checks bits 25 to 30 of [GPUSTAT](/hardware/gpu/gpustat/) against its own expected values.[^src] The bits it checks are bit 25 (DMA request), bit 26 (ready to receive a command word), bit 27 (ready to send VRAM to the CPU), bit 28 (ready to receive a DMA block) and bits 29 and 30 (DMA direction).[^run] |
| − | The bits it checks are bit 25 (DMA request), bit 26 (ready to receive a command word), bit 27 (ready to send VRAM to the CPU), bit 28 (ready to receive a DMA block) and bits 29 and 30 (DMA direction).[^run] | ||
| − | |||
| ## Results | ## Results | ||