Load Delay Slot Collisions: Difference between revisions

Revision as of 05:41, 23 October 2026
RemmyLee
(Hardware tests: See also links back from 37 existing pages to the new ones)

Revision as of 05:49, 23 October 2026
RemmyLee
(Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed)

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---

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title: Load Delay Slot Collisions

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type: test

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summary: Measures the time a counted loop takes when the instruction in a load's delay slot, or the one after it, writes, reads or loads the load's destination register, by load width, data region and code segment.

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category: Hardware tests

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info: Machine = SCPH-5501

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info: Program = col1

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---

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## Overview

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The program is a set of 2,016 small programs, each timed whole for 16 passes of a counted loop and called eight times; the first call is cold. Each pass is a lui of the address, a load L into t1, an instruction N, and j NOPs. N sits in the load's delay slot ("slot") or one word later after a NOP ("late"). Each line's name gives L, N, the data region, the code segment, j and the position, and the line gives the eight times twice, as run1 and run2.[^run]

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Table: The parts of a name

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| Part | Values |

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| --- | --- |

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| L | lw, lh, lhu, lb, lbu, lwl, lwr |

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| N | wd (addiu t1: writes t1 only), wds (or t1 from another register), rd (or t1 from t1), lw (a second load into t1), mfhi (into t1), ctl (addiu into another register) |

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| Data | k0, k1 and ku (RAM through KSEG0, KSEG1 and KUSEG), spad (the scratchpad) |

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| Code | k0 (cached), k1 (uncached) |

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| j | 0, 1 or 3 NOPs after N |

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| Position | slot or late |

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Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones)	Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed)
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	+	---
	+	title: Load Delay Slot Collisions
	+	type: test
	+	summary: Measures the time a counted loop takes when the instruction in a load's delay slot, or the one after it, writes, reads or loads the load's destination register, by load width, data region and code segment.
	+	category: Hardware tests
	+	info: Machine = SCPH-5501
	+	info: Program = col1
	+	---
	+
	+	## Overview
	+
	+	The program is a set of 2,016 small programs, each timed whole for 16 passes of a counted loop and called eight times; the first call is cold. Each pass is a lui of the address, a load L into t1, an instruction N, and j NOPs. N sits in the load's delay slot ("slot") or one word later after a NOP ("late"). Each line's name gives L, N, the data region, the code segment, j and the position, and the line gives the eight times twice, as run1 and run2.[^run]
	+
	+	Table: The parts of a name
	+
	+	\| Part \| Values \|
	+	\| --- \| --- \|
	+	\| L \| lw, lh, lhu, lb, lbu, lwl, lwr \|
	+	\| N \| wd (addiu t1: writes t1 only), wds (or t1 from another register), rd (or t1 from t1), lw (a second load into t1), mfhi (into t1), ctl (addiu into another register) \|
	+	\| Data \| k0, k1 and ku (RAM through KSEG0, KSEG1 and KUSEG), spad (the scratchpad) \|
	+	\| Code \| k0 (cached), k1 (uncached) \|
	+	\| j \| 0, 1 or 3 NOPs after N \|
	+	\| Position \| slot or late \|
	+
	+	See also:
	+
	+	- [Load Landing and Device Loads](/tests/load-landing/)
	+
	+	## Results
	+
	+	In all 2,016 lines run1 and run2 hold the same eight times. The control ctl, which writes another register, is the time of the loop without a collision, and the times below are the median of calls 2 to 8.[^run]
	+
	+	With RAM data and cached code, any N that wrote t1, read it or moved HI into it in the delay slot took 47 to 49 counts more than the control over the 16 passes, which is about 3 a pass. A second load into t1 took 112 to 116 counts more. With N one word later the cost was 64 to 66 counts, and 129 for the second load. With scratchpad data none of the N cost anything over the control.[^run]
	+
	+	Table: Counts for 16 passes of lw with j 0 and RAM through KSEG0
	+
	+	\| Code \| Position \| ctl \| wd \| wds \| rd \| lw \| mfhi \|
	+	\| --- \| --- \| --- \| --- \| --- \| --- \| --- \| --- \|
	+	\| Cached \| Slot \| 150 \| 197 \| 197 \| 197 \| 266 \| 197 \|
	+	\| Cached \| Late \| 149 \| 215 \| 213 \| 215 \| 278 \| 213 \|
	+	\| Uncached \| Slot \| 661 \| 698 \| 696 \| 694 \| 762 \| 696 \|
	+	\| Uncached \| Late \| 762 \| 794 \| 762 \| 792 \| 858 \| 762 \|
	+
	+	From uncached code with N one word later, wd and rd still cost 30 to 32 counts, but wds and mfhi cost nothing. In the delay slot from uncached code every N cost 27 to 37 counts and the second load 97 to 101.[^run]
	+
	+	The load width changed these costs by at most 8 counts. RAM data through KSEG0, KSEG1 or KUSEG gave times within 5 counts of each other in every program.[^run]
	+
	+	Table: Counts for 16 passes of lw with scratchpad data
	+
	+	\| Code \| Position \| ctl \| wd \| wds \| rd \| lw \| mfhi \|
	+	\| --- \| --- \| --- \| --- \| --- \| --- \| --- \| --- \|
	+	\| Cached \| Slot \| 101 \| 101 \| 101 \| 101 \| 101 \| 101 \|
	+	\| Cached \| Late \| 117 \| 117 \| 117 \| 117 \| 117 \| 117 \|
	+	\| Uncached \| Slot \| 596 \| 596 \| 596 \| 598 \| 596 \| 596 \|
	+	\| Uncached \| Late \| 698 \| 696 \| 698 \| 698 \| 698 \| 698 \|
	+
	+	## Runs
	+
	+	### 9 October 2026
	+
	+	[col1/COL1.txt](/tests/raw/20261009T0000Z-5501a-fuzz-col1/col1/COL1.txt)
	+
	+	## References
	+
	+	[^run]: SCPH-5501 output: [col1/COL1.txt](/tests/raw/20261009T0000Z-5501a-fuzz-col1/col1/COL1.txt)