SPU 32-bit Stores: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| SXSPU32 makes 16 runs of 64 stores to 1C08h, the ADSR register of voice 0, with every voice keyed off. Each run zeroes root counter 2 at a different phase, waits for a sample tick seen in SPUSTAT bit 0, and notes the counter at that tick as T. Store i is made at T + 1536(i + 1) + 3i cycles, and each value is read back with LW.[^run32] SXSPU32B prints the memory control registers as found, then makes four runs of the same stores under each of three COM_DELAY values: the value as found, 00031125h and 00001325h.[^run32b] | SXSPU32 makes 16 runs of 64 stores to 1C08h, the ADSR register of voice 0, with every voice keyed off. Each run zeroes root counter 2 at a different phase, waits for a sample tick seen in SPUSTAT bit 0, and notes the counter at that tick as T. Store i is made at T + 1536(i + 1) + 3i cycles, and each value is read back with LW.[^run32] SXSPU32B prints the memory control registers as found, then makes four runs of the same stores under each of three COM_DELAY values: the value as found, 00031125h and 00001325h.[^run32b] | ||
| + | See also: | ||
| + | |||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | - [SPU Envelope Grid and GPU Fill Timing](/tests/spu-envelope-grid-gpu-fill/) | ||
| + | |||
| ## Results | ## Results | ||