SPU 32-bit Stores

Checks whether a 32-bit store to an SPU register loses one of its halves at any store timing.

This is an old revision of this page, as edited by RemmyLee at 05:49, 23 October 2026. Edit this revision | Latest revision

Overview

A 32-bit store to the SPU is split into two 16-bit writes. In an earlier card run the console lost the low half of every store whose root counter 2 reading just before it was 1 mod 8. The loss showed in all four registers that run tried.¹ These probes repeat the stores to find the clock that decides the loss.²

SXSPU32 makes 16 runs of 64 stores to 1C08h, the ADSR register of voice 0, with every voice keyed off. Each run zeroes root counter 2 at a different phase, waits for a sample tick seen in SPUSTAT bit 0, and notes the counter at that tick as T. Store i is made at T + 1536(i + 1) + 3i cycles, and each value is read back with LW.² SXSPU32B prints the memory control registers as found, then makes four runs of the same stores under each of three COM_DELAY values: the value as found, 00031125h and 00001325h.³

See also:

• Bus Access and Device Register Timing
• SPU Envelope Grid and GPU Fill Timing

Results

No store lost a half in either probe. SXSPU32 made 1024 stores across every counter phase mod 8 and every phase from the sample tick, and all 1024 read back whole.²

SXSPU32B found 1F801014h at 220931E1h and COM_DELAY at 00031125h. It made 768 stores under COM_DELAY 00031125h and 00001325h, and all read back whole.³

The loss in the card run therefore did not depend on the store's phase or on COM_DELAY alone. It depended on some other state that the card program had set.²

Runs

Run 5501a-link on 15 October 2026

Raw output: SXSPU32.txt

SXSPU32.txt:

SXDEV I_MASK at init 3C020100
SXSPU32 start
SXSPU32 run 0 T 2 poll 47 lost 0 of 64 by t mod 8: 4/0 12/0 5/0 9/0 5/0 11/0 8/0 10/0 by (t-T) mod 8: 5/0 9/0 5/0 11/0 8/0 10/0 4/0 12/0 high 0
SXSPU32 run 1 T 5 poll 37 lost 0 of 64 by t mod 8: 4/0 9/0 8/0 10/0 5/0 13/0 5/0 10/0 by (t-T) mod 8: 13/0 5/0 10/0 4/0 9/0 8/0 10/0 5/0 high 0
SXSPU32 run 2 T 7 poll 43 lost 0 of 64 by t mod 8: 8/0 10/0 5/0 13/0 4/0 10/0 5/0 9/0 by (t-T) mod 8: 9/0 8/0 10/0 5/0 13/0 4/0 10/0 5/0 high 0
SXSPU32 run 3 T 5 poll 40 lost 0 of 64 by t mod 8: 5/0 13/0 4/0 10/0 5/0 9/0 8/0 10/0 by (t-T) mod 8: 9/0 8/0 10/0 5/0 13/0 4/0 10/0 5/0 high 0
SXSPU32 run 4 T 6 poll 37 lost 0 of 64 by t mod 8: 9/0 8/0 11/0 5/0 13/0 4/0 9/0 5/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32 run 5 T 5 poll 42 lost 0 of 64 by t mod 8: 5/0 13/0 4/0 10/0 5/0 9/0 8/0 10/0 by (t-T) mod 8: 9/0 8/0 10/0 5/0 13/0 4/0 10/0 5/0 high 0
SXSPU32 run 6 T 2 poll 37 lost 0 of 64 by t mod 8: 5/0 10/0 5/0 10/0 7/0 9/0 5/0 13/0 by (t-T) mod 8: 5/0 10/0 7/0 9/0 5/0 13/0 5/0 10/0 high 0
SXSPU32 run 7 T 3 poll 37 lost 0 of 64 by t mod 8: 5/0 13/0 4/0 9/0 5/0 9/0 8/0 11/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32 run 8 T 6 poll 37 lost 0 of 64 by t mod 8: 5/0 14/0 5/0 10/0 4/0 9/0 8/0 9/0 by (t-T) mod 8: 8/0 9/0 5/0 14/0 5/0 10/0 4/0 9/0 high 0
SXSPU32 run 9 T 0 poll 37 lost 0 of 64 by t mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32 run 10 T 7 poll 58 lost 0 of 64 by t mod 8: 9/0 5/0 14/0 8/0 10/0 4/0 9/0 5/0 by (t-T) mod 8: 5/0 9/0 5/0 14/0 8/0 10/0 4/0 9/0 high 0
SXSPU32 run 11 T 6 poll 37 lost 0 of 64 by t mod 8: 9/0 8/0 11/0 5/0 13/0 4/0 9/0 5/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32 run 12 T 4 poll 37 lost 0 of 64 by t mod 8: 11/0 5/0 13/0 4/0 9/0 5/0 9/0 8/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32 run 13 T 3 poll 47 lost 0 of 64 by t mod 8: 9/0 8/0 10/0 5/0 14/0 4/0 9/0 5/0 by (t-T) mod 8: 5/0 14/0 4/0 9/0 5/0 9/0 8/0 10/0 high 0
SXSPU32 run 14 T 3 poll 37 lost 0 of 64 by t mod 8: 8/0 10/0 5/0 13/0 5/0 10/0 4/0 9/0 by (t-T) mod 8: 13/0 5/0 10/0 4/0 9/0 8/0 10/0 5/0 high 0
SXSPU32 run 15 T 1 poll 37 lost 0 of 64 by t mod 8: 13/0 5/0 9/0 5/0 10/0 8/0 10/0 4/0 by (t-T) mod 8: 5/0 9/0 5/0 10/0 8/0 10/0 4/0 13/0 high 0
SXSPU32 end PASS

Run 5501a-link on 15 October 2026

Raw output: SXSPU32B.txt

SXSPU32B.txt:

SXDEV I_MASK at init 3C040100
SXSPU32B start
SXSPU32B memctrl 1F801000 1F000000
SXSPU32B memctrl 1F801004 1F802000
SXSPU32B memctrl 1F801008 0013243F
SXSPU32B memctrl 1F80100C 00003022
SXSPU32B memctrl 1F801010 0013243F
SXSPU32B memctrl 1F801014 220931E1
SXSPU32B memctrl 1F801018 00020843
SXSPU32B memctrl 1F80101C 00070777
SXSPU32B memctrl 1F801020 00031125
SXSPU32B com 00031125 run 0 T 4 poll 61 lost 0 of 64 by t mod 8: 5/0 13/0 5/0 9/0 5/0 10/0 7/0 10/0 by (t-T) mod 8: 5/0 10/0 7/0 10/0 5/0 13/0 5/0 9/0 high 0
SXSPU32B com 00031125 run 5 T 0 poll 37 lost 0 of 64 by t mod 8: 4/0 9/0 7/0 11/0 6/0 12/0 5/0 10/0 by (t-T) mod 8: 4/0 9/0 7/0 11/0 6/0 12/0 5/0 10/0 high 0
SXSPU32B com 00031125 run 10 T 5 poll 37 lost 0 of 64 by t mod 8: 9/0 5/0 9/0 8/0 10/0 5/0 14/0 4/0 by (t-T) mod 8: 5/0 14/0 4/0 9/0 5/0 9/0 8/0 10/0 high 0
SXSPU32B com 00031125 run 15 T 2 poll 37 lost 0 of 64 by t mod 8: 9/0 5/0 10/0 7/0 11/0 5/0 12/0 5/0 by (t-T) mod 8: 10/0 7/0 11/0 5/0 12/0 5/0 9/0 5/0 high 0
SXSPU32B com 00031125 run 0 T 7 poll 22 lost 0 of 64 by t mod 8: 7/0 11/0 4/0 12/0 5/0 9/0 6/0 10/0 by (t-T) mod 8: 10/0 7/0 11/0 4/0 12/0 5/0 9/0 6/0 high 0
SXSPU32B com 00031125 run 5 T 5 poll 37 lost 0 of 64 by t mod 8: 9/0 5/0 9/0 8/0 10/0 5/0 14/0 4/0 by (t-T) mod 8: 5/0 14/0 4/0 9/0 5/0 9/0 8/0 10/0 high 0
SXSPU32B com 00031125 run 10 T 3 poll 37 lost 0 of 64 by t mod 8: 9/0 6/0 9/0 7/0 12/0 5/0 12/0 4/0 by (t-T) mod 8: 7/0 12/0 5/0 12/0 4/0 9/0 6/0 9/0 high 0
SXSPU32B com 00031125 run 15 T 1 poll 37 lost 0 of 64 by t mod 8: 7/0 11/0 4/0 9/0 5/0 9/0 6/0 13/0 by (t-T) mod 8: 11/0 4/0 9/0 5/0 9/0 6/0 13/0 7/0 high 0
SXSPU32B com 00001325 run 0 T 0 poll 37 lost 0 of 64 by t mod 8: 7/0 12/0 6/0 12/0 4/0 9/0 5/0 9/0 by (t-T) mod 8: 7/0 12/0 6/0 12/0 4/0 9/0 5/0 9/0 high 0
SXSPU32B com 00001325 run 5 T 5 poll 39 lost 0 of 64 by t mod 8: 5/0 13/0 4/0 10/0 5/0 9/0 8/0 10/0 by (t-T) mod 8: 9/0 8/0 10/0 5/0 13/0 4/0 10/0 5/0 high 0
SXSPU32B com 00001325 run 10 T 2 poll 37 lost 0 of 64 by t mod 8: 9/0 5/0 10/0 7/0 11/0 5/0 12/0 5/0 by (t-T) mod 8: 10/0 7/0 11/0 5/0 12/0 5/0 9/0 5/0 high 0
SXSPU32B com 00001325 run 15 T 6 poll 37 lost 0 of 64 by t mod 8: 9/0 8/0 11/0 5/0 13/0 4/0 9/0 5/0 by (t-T) mod 8: 9/0 5/0 9/0 8/0 11/0 5/0 13/0 4/0 high 0
SXSPU32B end PASS

References