SPU Memory Transfer: Difference between revisions

Revision as of 04:48, 23 October 2026 RemmyLee (Main page: drop the Hardware Tests lede)	Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)
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	+	---
	+	title: SPU Memory Transfer
	+	type: test
	+	summary: Checks sound RAM access through the data port and DMA channel 4.
	+	category: Hardware tests
	+	info: Machine = SCPH-5501
	+	info: Program = spu/memory-transfer (ps1-tests)
	+	---
	+
	+	## Overview
	+
	+	The program writes the data transfer control register at 1F801DACh and reads it back, writes sound RAM through the data port and checks that SPUSTAT bit 10 clears, and moves a test string to and from sound RAM by [DMA](/hardware/dma/) channel 4. It times a DMA write and a DMA read against a window the test sets, runs both in sync mode 0, and checks that the transfer mode bits of SPUCNT appear in SPUSTAT.[^src]
	+
	+	## Results
	+
	+	The SCPH-5501 passed all 9 checks in every run.[^run]
	+
	+	The data transfer control register read back every value written. The string came back intact by DMA in both directions, and both transfers finished within the test's timing window. DMA in sync mode 0 completed in both directions, and the SPUCNT transfer mode bits appeared in SPUSTAT.[^run]
	+
	+	## Runs
	+
	+	### 25 September 2026
	+
	+	[09SPU.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	### 27 September 2026
	+
	+	[09SPU.txt](/tests/raw/20260927T0000Z-5501a-card-2/main/s024/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	### 27 September 2026 run 2
	+
	+	[09SPU.txt](/tests/raw/20260927T0000Z-5501a-card-b/main/s034/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	### 27 September 2026 run 3
	+
	+	[09SPU.txt](/tests/raw/20260927T0000Z-5501a-card-g/main/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	### 27 September 2026 run 4
	+
	+	[09SPU.txt](/tests/raw/20260927T0000Z-5501a-card-g3/main/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	### 28 September 2026
	+
	+	[09SPU.txt](/tests/raw/20260928T0000Z-5501a-card-h/main/09SPU.txt)
	+
	+	```
	+	===== 09 SPU SPU TRANSFER \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+
	+	spu/memory-transfer
	+	Test SPU memory access using DMA and regular IO.
	+
	+	pass - testDtcRegister
	+	pass - testManualWriteToSpuRam
	+	pass - testDMAReadFromSpuRam
	+	pass - testDMAWriteToSpuRam
	+	pass - testDMAWriteTiming
	+	pass - testDMAReadTiming
	+	pass - testDMAWriteToRamSyncMode0
	+	pass - testDMAReadToRamSyncMode0
	+	pass - testControlBitsAreCopiedToStatusRegister
	+	Done.
	+	```
	+
	+	## References
	+
	+	[^src]: ps1-tests, spu/memory-transfer. https://github.com/JaCzekanski/ps1-tests.
	+	[^run]: SCPH-5501 output: [main/09SPU.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/09SPU.txt) and the files beside it, with the other runs listed under Runs.

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