SPU Memory Transfer
Checks sound RAM access through the data port and DMA channel 4.
| Machine | SCPH-5501 |
|---|---|
| Program | spu/memory-transfer (ps1-tests) |
Overview
The program writes the data transfer control register at 1F801DACh and reads it back, writes sound RAM through the data port and checks that SPUSTAT bit 10 clears, and moves a test string to and from sound RAM by DMA channel 4. It times a DMA write and a DMA read against a window the test sets, runs both in sync mode 0, and checks that the transfer mode bits of SPUCNT appear in SPUSTAT.1
Results
The SCPH-5501 passed all 9 checks in every run.2
The data transfer control register read back every value written. The string came back intact by DMA in both directions, and both transfers finished within the test's timing window. DMA in sync mode 0 completed in both directions, and the SPUCNT transfer mode bits appeared in SPUSTAT.2
Runs
25 September 2026
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
27 September 2026
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
27 September 2026 run 2
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
27 September 2026 run 3
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
27 September 2026 run 4
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
28 September 2026
===== 09 SPU SPU TRANSFER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
spu/memory-transfer
Test SPU memory access using DMA and regular IO.
pass - testDtcRegister
pass - testManualWriteToSpuRam
pass - testDMAReadFromSpuRam
pass - testDMAWriteToSpuRam
pass - testDMAWriteTiming
pass - testDMAReadTiming
pass - testDMAWriteToRamSyncMode0
pass - testDMAReadToRamSyncMode0
pass - testControlBitsAreCopiedToStatusRegister
Done.
References
-
^ ps1-tests, spu/memory-transfer. https://github.com/JaCzekanski/ps1-tests.
-
^ a b SCPH-5501 output: main/09SPU.txt and the files beside it, with the other runs listed under Runs.