MDEC Reset and Store Timing: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
| Line 12: | Line 12: | ||
| The programs write an [MDEC](/hardware/mdec/) reset to MDEC1, then the command 40000001h (load the quant tables) to MDEC0 a few instructions later, and read the MDEC status. A status of A004001Fh means the command was kept and the MDEC waits for 32 table words. A status of 80040000h means the command was lost.[^r1] | The programs write an [MDEC](/hardware/mdec/) reset to MDEC1, then the command 40000001h (load the quant tables) to MDEC0 a few instructions later, and read the MDEC status. A status of A004001Fh means the command was kept and the MDEC waits for 32 table words. A status of 80040000h means the command was lost.[^r1] | ||
| − | Each row runs one shape of code three times. The code runs either straight from RAM with the instruction cache cold (c) or a second time from the cache (w, warm). Before the reset store there is nothing (n), one RAM store (r), two RAM stores (rr), a scratchpad store (s) or an I/O store (i). Between the reset and the command there are 0, 1, 2 or 4 NOPs, or a status read (l).[^r1] | + | Each row runs one shape of code three times. The code runs either straight from RAM with the instruction cache cold (c) or a second time from the cache (w, warm). Before the reset store there is nothing (n), one RAM store (r), two RAM stores (rr), a scratchpad store (s) or an I/O store (i). Between the reset and the command there are 0, 1, 2 or 4 NOPs, or a status read (l).[^r1] The later programs time the same stores in system clock cycles on root counters 2 and 1.[^r2][^r3][^r8] |
| − | The later programs time the same stores in system clock cycles on root counters 2 and 1.[^r2][^r3][^r8] | ||
| − | |||
| ## Results | ## Results | ||