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--- title: MDEC Reset and Store Timing type: test summary: Measures whether the MDEC accepts a command written soon after a reset, and how long stores to RAM and I/O registers take. category: Hardware tests info: Machine = SCPH-5501 info: Program = sxmdrst, sxmdrst2 to sxmdrst5, sxmdrst7 and sxmdrst8 --- ## Overview The programs write an [MDEC](/hardware/mdec/) reset to MDEC1, then the command 40000001h (load the quant tables) to MDEC0 a few instructions later, and read the MDEC status. A status of A004001Fh means the command was kept and the MDEC waits for 32 table words. A status of 80040000h means the command was lost.[^r1] Each row runs one shape of code three times. The code runs either straight from RAM with the instruction cache cold (c) or a second time from the cache (w, warm). Before the reset store there is nothing (n), one RAM store (r), two RAM stores (rr), a scratchpad store (s) or an I/O store (i). Between the reset and the command there are 0, 1, 2 or 4 NOPs, or a status read (l).[^r1] The later programs time the same stores in system clock cycles on root counters 2 and 1.[^r2][^r3][^r8] See also: - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) - [MDEC Block Timing](/tests/mdec-block-timing/) - [SPU Voice Start and MDEC Reset](/tests/spu-voice-start-mdec-reset/) ## Results ### Command After a Reset From cold code the command was kept in every shape. From warm code it was lost with 1, 2 or 4 NOPs after the reset in every shape, and it was kept when a status read came between. With no NOPs it was kept only after one RAM store: after two RAM stores, a scratchpad store, an I/O store or nothing it was lost. The MDEC idle and the MDEC part way through a decode gave the same results.[^r1] The number of NOPs needed in warm code depends on the stores before the reset.[^r2] Table: NOPs between the MDEC reset and the MDEC0 command in warm code | Before the reset | Command lost | Command kept | | --- | --- | --- | | nothing | up to 5 NOPs | 6 NOPs or more | | one RAM store | up to 7 | 8 or more | | two RAM stores | up to 8 | 12 or more (10 kept 2 times of 3) | | a RAM store and a NOP | up to 6 | 7 or more | | a RAM store and two NOPs | up to 5 | 7 or more (6 kept 2 times of 3) | From cold code the reset store could sit at any word of a cache line, with 0 to 6 NOPs before the command, and the command was kept in all 28 shapes.[^r3] ### Store Timing Root counter 2 read across a reset store followed by N NOPs gave 6, 6, 7, 9 and 13 cycles for N of 0, 1, 2, 4 and 8.[^r2] Table: Cycles across the MDEC reset store | Before the store | Warm | Cold | | --- | --- | --- | | nothing | 6 | 13 | | one RAM store | 7 | 17 | | two RAM stores | 9 | 19 | | an I/O store | 6 | 13 | A run of K RAM stores costs 2K+14 cycles for K from 1 to 24. Some samples took 5 or 10 cycles more at random values of K.[^r8] A store to I_MASK, the root counter 2 target or the GPU took 10 cycles with nothing before it and 13 with a RAM store before it. A load from the same registers took 8 and 11 cycles.[^r5] ## Runs ### 16 October 2026 link sxmdrst Raw output: [sxmdrst/SXMDRST.txt](/tests/raw/20261016T0159Z-5501a-link/sxmdrst/SXMDRST.txt) ``` SXDEV I_MASK at init AE420100 SXMDRST start SXMDRST idle c n 0: A004001F A004001F A004001F SXMDRST idle c n 1: A004001F A004001F A004001F SXMDRST idle c n 2: A004001F A004001F A004001F SXMDRST idle c n 4: A004001F A004001F A004001F SXMDRST idle c n l: A004001F A004001F A004001F SXMDRST idle c r 0: A004001F A004001F A004001F SXMDRST idle c r 1: A004001F A004001F A004001F SXMDRST idle c r 2: A004001F A004001F A004001F SXMDRST idle c r 4: A004001F A004001F A004001F SXMDRST idle c r l: A004001F A004001F A004001F SXMDRST idle c rr 0: A004001F A004001F A004001F SXMDRST idle c rr 1: A004001F A004001F A004001F SXMDRST idle c rr 2: A004001F A004001F A004001F SXMDRST idle c rr 4: A004001F A004001F A004001F SXMDRST idle c rr l: A004001F A004001F A004001F SXMDRST idle c s 0: A004001F A004001F A004001F SXMDRST idle c s 1: A004001F A004001F A004001F SXMDRST idle c s 2: A004001F A004001F A004001F SXMDRST idle c s 4: A004001F A004001F A004001F SXMDRST idle c s l: A004001F A004001F A004001F SXMDRST idle c i 0: A004001F A004001F A004001F SXMDRST idle c i 1: A004001F A004001F A004001F SXMDRST idle c i 2: A004001F A004001F A004001F SXMDRST idle c i 4: A004001F A004001F A004001F SXMDRST idle c i l: A004001F A004001F A004001F SXMDRST idle w n 0: 80040000 80040000 80040000 SXMDRST idle w n 1: 80040000 80040000 80040000 SXMDRST idle w n 2: 80040000 80040000 80040000 SXMDRST idle w n 4: 80040000 80040000 80040000 SXMDRST idle w n l: A004001F A004001F A004001F SXMDRST idle w r 0: A004001F A004001F A004001F SXMDRST idle w r 1: 80040000 80040000 80040000 SXMDRST idle w r 2: 80040000 80040000 80040000 SXMDRST idle w r 4: 80040000 80040000 80040000 SXMDRST idle w r l: A004001F A004001F A004001F SXMDRST idle w rr 0: 80040000 80040000 80040000 SXMDRST idle w rr 1: 80040000 80040000 80040000 SXMDRST idle w rr 2: 80040000 80040000 80040000 SXMDRST idle w rr 4: 80040000 80040000 80040000 SXMDRST idle w rr l: A004001F A004001F A004001F SXMDRST idle w s 0: 80040000 80040000 80040000 SXMDRST idle w s 1: 80040000 80040000 80040000 SXMDRST idle w s 2: 80040000 80040000 80040000 SXMDRST idle w s 4: 80040000 80040000 80040000 SXMDRST idle w s l: A004001F A004001F A004001F SXMDRST idle w i 0: 80040000 80040000 80040000 SXMDRST idle w i 1: 80040000 80040000 80040000 SXMDRST idle w i 2: 80040000 80040000 80040000 SXMDRST idle w i 4: 80040000 80040000 80040000 SXMDRST idle w i l: A004001F A004001F A004001F SXMDRST mid c n 0: A004001F A004001F A004001F SXMDRST mid c n 1: A004001F A004001F A004001F SXMDRST mid c n 2: A004001F A004001F A004001F SXMDRST mid c n 4: A004001F A004001F A004001F SXMDRST mid c n l: A004001F A004001F A004001F SXMDRST mid c r 0: A004001F A004001F A004001F SXMDRST mid c r 1: A004001F A004001F A004001F SXMDRST mid c r 2: A004001F A004001F A004001F SXMDRST mid c r 4: A004001F A004001F A004001F SXMDRST mid c r l: A004001F A004001F A004001F SXMDRST mid c rr 0: A004001F A004001F A004001F SXMDRST mid c rr 1: A004001F A004001F A004001F SXMDRST mid c rr 2: A004001F A004001F A004001F SXMDRST mid c rr 4: A004001F A004001F A004001F SXMDRST mid c rr l: A004001F A004001F A004001F SXMDRST mid c s 0: A004001F A004001F A004001F SXMDRST mid c s 1: A004001F A004001F A004001F SXMDRST mid c s 2: A004001F A004001F A004001F SXMDRST mid c s 4: A004001F A004001F A004001F SXMDRST mid c s l: A004001F A004001F A004001F SXMDRST mid c i 0: A004001F A004001F A004001F SXMDRST mid c i 1: A004001F A004001F A004001F SXMDRST mid c i 2: A004001F A004001F A004001F SXMDRST mid c i 4: A004001F A004001F A004001F SXMDRST mid c i l: A004001F A004001F A004001F SXMDRST mid w n 0: 80040000 80040000 80040000 SXMDRST mid w n 1: 80040000 80040000 80040000 SXMDRST mid w n 2: 80040000 80040000 80040000 SXMDRST mid w n 4: 80040000 80040000 80040000 SXMDRST mid w n l: A004001F A004001F A004001F SXMDRST mid w r 0: A004001F A004001F A004001F SXMDRST mid w r 1: 80040000 80040000 80040000 SXMDRST mid w r 2: 80040000 80040000 80040000 SXMDRST mid w r 4: 80040000 80040000 80040000 SXMDRST mid w r l: A004001F A004001F A004001F SXMDRST mid w rr 0: 80040000 80040000 80040000 SXMDRST mid w rr 1: 80040000 80040000 80040000 SXMDRST mid w rr 2: 80040000 80040000 80040000 SXMDRST mid w rr 4: 80040000 80040000 80040000 SXMDRST mid w rr l: A004001F A004001F A004001F SXMDRST mid w s 0: 80040000 80040000 80040000 SXMDRST mid w s 1: 80040000 80040000 80040000 SXMDRST mid w s 2: 80040000 80040000 80040000 SXMDRST mid w s 4: 80040000 80040000 80040000 SXMDRST mid w s l: A004001F A004001F A004001F SXMDRST mid w i 0: 80040000 80040000 80040000 SXMDRST mid w i 1: 80040000 80040000 80040000 SXMDRST mid w i 2: 80040000 80040000 80040000 SXMDRST mid w i 4: 80040000 80040000 80040000 SXMDRST mid w i l: A004001F A004001F A004001F SXMDRST end PASS ``` ### 16 October 2026 link sxmdrst2 Raw output: [sxmdrst2/SXMDRST2.txt](/tests/raw/20261016T0210Z-5501a-link/sxmdrst2/SXMDRST2.txt) ``` SXDEV I_MASK at init 3C020100 SXMDRST2 start SXMDRST2 n 0: 80040000 80040000 80040000 SXMDRST2 n 1: 80040000 80040000 80040000 SXMDRST2 n 2: 80040000 80040000 80040000 SXMDRST2 n 3: 80040000 80040000 80040000 SXMDRST2 n 4: 80040000 80040000 80040000 SXMDRST2 n 5: 80040000 80040000 80040000 SXMDRST2 n 6: A004001F A004001F A004001F SXMDRST2 n 7: A004001F A004001F A004001F SXMDRST2 n 8: A004001F A004001F A004001F SXMDRST2 n 10: A004001F A004001F A004001F SXMDRST2 n 12: A004001F A004001F A004001F SXMDRST2 n 16: A004001F A004001F A004001F SXMDRST2 n 24: A004001F A004001F A004001F SXMDRST2 n 32: A004001F A004001F A004001F SXMDRST2 r 0: 80040000 80040000 80040000 SXMDRST2 r 1: 80040000 80040000 80040000 SXMDRST2 r 2: 80040000 80040000 80040000 SXMDRST2 r 3: 80040000 80040000 80040000 SXMDRST2 r 4: 80040000 80040000 80040000 SXMDRST2 r 5: 80040000 80040000 80040000 SXMDRST2 r 6: 80040000 80040000 80040000 SXMDRST2 r 7: 80040000 80040000 80040000 SXMDRST2 r 8: A004001F A004001F A004001F SXMDRST2 r 10: A004001F A004001F A004001F SXMDRST2 r 12: A004001F A004001F A004001F SXMDRST2 r 16: A004001F A004001F A004001F SXMDRST2 r 24: A004001F A004001F A004001F SXMDRST2 r 32: A004001F A004001F A004001F SXMDRST2 rr 0: 80040000 80040000 80040000 SXMDRST2 rr 1: 80040000 80040000 80040000 SXMDRST2 rr 2: 80040000 80040000 80040000 SXMDRST2 rr 3: 80040000 80040000 80040000 SXMDRST2 rr 4: 80040000 80040000 80040000 SXMDRST2 rr 5: 80040000 80040000 80040000 SXMDRST2 rr 6: 80040000 80040000 80040000 SXMDRST2 rr 7: 80040000 80040000 80040000 SXMDRST2 rr 8: 80040000 80040000 80040000 SXMDRST2 rr 10: 80040000 A004001F A004001F SXMDRST2 rr 12: A004001F A004001F A004001F SXMDRST2 rr 16: A004001F A004001F A004001F SXMDRST2 rr 24: A004001F A004001F A004001F SXMDRST2 rr 32: A004001F A004001F A004001F SXMDRST2 r1 0: 80040000 80040000 80040000 SXMDRST2 r1 1: 80040000 80040000 80040000 SXMDRST2 r1 2: 80040000 80040000 80040000 SXMDRST2 r1 3: 80040000 80040000 80040000 SXMDRST2 r1 4: 80040000 80040000 80040000 SXMDRST2 r1 5: 80040000 80040000 80040000 SXMDRST2 r1 6: 80040000 80040000 80040000 SXMDRST2 r1 7: A004001F A004001F A004001F SXMDRST2 r1 8: A004001F A004001F A004001F SXMDRST2 r1 10: A004001F A004001F A004001F SXMDRST2 r1 12: A004001F A004001F A004001F SXMDRST2 r1 16: A004001F A004001F A004001F SXMDRST2 r1 24: A004001F A004001F A004001F SXMDRST2 r1 32: A004001F A004001F A004001F SXMDRST2 r2 0: 80040000 80040000 80040000 SXMDRST2 r2 1: 80040000 80040000 80040000 SXMDRST2 r2 2: 80040000 80040000 80040000 SXMDRST2 r2 3: 80040000 80040000 80040000 SXMDRST2 r2 4: 80040000 80040000 80040000 SXMDRST2 r2 5: 80040000 80040000 80040000 SXMDRST2 r2 6: A004001F 80040000 A004001F SXMDRST2 r2 7: A004001F A004001F A004001F SXMDRST2 r2 8: A004001F A004001F A004001F SXMDRST2 r2 10: A004001F A004001F A004001F SXMDRST2 r2 12: A004001F A004001F A004001F SXMDRST2 r2 16: A004001F A004001F A004001F SXMDRST2 r2 24: A004001F A004001F A004001F SXMDRST2 r2 32: A004001F A004001F A004001F SXMDRST2 T 0: 6 6 6 SXMDRST2 T 1: 6 6 6 SXMDRST2 T 2: 7 7 7 SXMDRST2 T 4: 9 9 9 SXMDRST2 T 8: 13 13 13 SXMDRST2 end PASS ``` ### 16 October 2026 link sxmdrst3 Raw output: [sxmdrst3/SXMDRST3.txt](/tests/raw/20261016T0222Z-5501a-link/sxmdrst3/SXMDRST3.txt) ``` SXDEV I_MASK at init AE420100 SXMDRST3 start SXMDRST3 T w n: 6 6 6 SXMDRST3 T w r: 7 7 7 SXMDRST3 T w rr: 9 9 9 SXMDRST3 T w r1: 7 7 7 SXMDRST3 T w r2: 9 9 9 SXMDRST3 T w i: 6 6 6 SXMDRST3 T c n: 13 13 13 SXMDRST3 T c r: 17 17 17 SXMDRST3 T c rr: 19 19 19 SXMDRST3 T c r1: 17 17 17 SXMDRST3 T c r2: 25 25 25 SXMDRST3 T c i: 13 13 13 SXMDRST3 D 0 n 0: A004001F A004001F A004001F SXMDRST3 D 0 n 1: A004001F A004001F A004001F SXMDRST3 D 0 n 2: A004001F A004001F A004001F SXMDRST3 D 0 n 3: A004001F A004001F A004001F SXMDRST3 D 0 n 4: A004001F A004001F A004001F SXMDRST3 D 0 n 6: A004001F A004001F A004001F SXMDRST3 D 0 r 0: A004001F A004001F A004001F SXMDRST3 D 1 n 0: A004001F A004001F A004001F SXMDRST3 D 1 n 1: A004001F A004001F A004001F SXMDRST3 D 1 n 2: A004001F A004001F A004001F SXMDRST3 D 1 n 3: A004001F A004001F A004001F SXMDRST3 D 1 n 4: A004001F A004001F A004001F SXMDRST3 D 1 n 6: A004001F A004001F A004001F SXMDRST3 D 1 r 0: A004001F A004001F A004001F SXMDRST3 D 2 n 0: A004001F A004001F A004001F SXMDRST3 D 2 n 1: A004001F A004001F A004001F SXMDRST3 D 2 n 2: A004001F A004001F A004001F SXMDRST3 D 2 n 3: A004001F A004001F A004001F SXMDRST3 D 2 n 4: A004001F A004001F A004001F SXMDRST3 D 2 n 6: A004001F A004001F A004001F SXMDRST3 D 2 r 0: A004001F A004001F A004001F SXMDRST3 D 3 n 0: A004001F A004001F A004001F SXMDRST3 D 3 n 1: A004001F A004001F A004001F SXMDRST3 D 3 n 2: A004001F A004001F A004001F SXMDRST3 D 3 n 3: A004001F A004001F A004001F SXMDRST3 D 3 n 4: A004001F A004001F A004001F SXMDRST3 D 3 n 6: A004001F A004001F A004001F SXMDRST3 D 3 r 0: A004001F A004001F A004001F SXMDRST3 end PASS ``` ### 16 October 2026 link sxmdrst4 Raw output: [sxmdrst4/SXMDRST4.txt](/tests/raw/20261016T0256Z-5501a-link/sxmdrst4/SXMDRST4.txt) ``` SXDEV I_MASK at init 3C020100 SXMDRST4 start SXMDRST4 A 0 w: 4 4 4 SXMDRST4 A 1 w: 4 4 4 SXMDRST4 A 2 w: 4 4 4 SXMDRST4 A 3 w: 4 4 4 SXMDRST4 B 0 w: 7 7 7 SXMDRST4 B 1 w: 7 7 7 SXMDRST4 B 2 w: 17 7 7 SXMDRST4 B 3 w: 7 7 7 SXMDRST4 C 0 w: 7 7 7 SXMDRST4 C 1 w: 7 7 7 SXMDRST4 C 2 w: 7 7 7 SXMDRST4 C 3 w: 12 7 7 SXMDRST4 D 0 w: 8 8 9 SXMDRST4 E 1 w: 7 7 7 SXMDRST4 E 2 w: 11 9 9 SXMDRST4 E 3 w: 11 11 11 SXMDRST4 E 4 w: 13 13 13 SXMDRST4 A 0 c: 4 4 4 SXMDRST4 A 1 c: 12 16 11 SXMDRST4 A 2 c: 4 4 4 SXMDRST4 A 3 c: 4 4 4 SXMDRST4 B 0 c: 17 17 17 SXMDRST4 B 1 c: 11 11 11 SXMDRST4 B 2 c: 7 7 7 SXMDRST4 B 3 c: 7 7 7 SXMDRST4 C 0 c: 17 23 17 SXMDRST4 C 1 c: 11 11 11 SXMDRST4 C 2 c: 7 7 7 SXMDRST4 C 3 c: 17 17 17 SXMDRST4 D 0 c: 18 18 18 SXMDRST4 E 1 c: 17 17 23 SXMDRST4 E 2 c: 19 19 19 SXMDRST4 E 3 c: 24 19 19 SXMDRST4 E 4 c: 25 25 25 SXMDRST4 W rr 9: A004001F 80040000 A004001F A004001F A004001F A004001F A004001F A004001F A004001F SXMDRST4 W rr 10: A004001F A004001F A004001F A004001F A004001F A004001F A004001F A004001F A004001F SXMDRST4 W r2 6: A004001F A004001F A004001F 80040000 A004001F A004001F A004001F A004001F 80040000 SXMDRST4 end PASS ``` ### 16 October 2026 link sxmdrst5 Raw output: [sxmdrst5/SXMDRST5.txt](/tests/raw/20261016T0308Z-5501a-link/sxmdrst5/SXMDRST5.txt) ``` SXDEV I_MASK at init AC400100 SXMDRST5 start SXMDRST5 R imask n sw: 10 10 10 SXMDRST5 R imask r sw: 13 17 13 SXMDRST5 R imask n lw: 8 8 8 SXMDRST5 R imask r lw: 11 11 11 SXMDRST5 R t2tgt n sw: 10 10 10 SXMDRST5 R t2tgt r sw: 13 13 13 SXMDRST5 R t2tgt n lw: 8 8 8 SXMDRST5 R t2tgt r lw: 11 11 11 SXMDRST5 R gpu n sw: 10 10 10 SXMDRST5 R gpu r sw: 13 13 13 SXMDRST5 R gpu n lw: 8 8 8 SXMDRST5 R gpu r lw: 11 11 11 SXMDRST5 R dpcr n sw: 10 10 10 SXMDRST5 R dpcr r sw: 13 13 13 SXMDRST5 R dpcr n lw: 8 8 8 SXMDRST5 R dpcr r lw: 11 11 11 SXMDRST5 R spu n sw: 31 31 31 SXMDRST5 R spu r sw: 34 34 34 SXMDRST5 R spu n lw: 23 23 23 SXMDRST5 R spu r lw: 26 26 26 SXMDRST5 R mdec n sw: 10 10 10 SXMDRST5 R mdec r sw: 13 13 13 SXMDRST5 R mdec n lw: 8 8 8 SXMDRST5 R mdec r lw: 11 11 11 SXMDRST5 F 0 0 a: 4 4 4 SXMDRST5 F 0 1 a: 13 13 13 SXMDRST5 F 0 2 a: 9 9 9 SXMDRST5 F 0 3 a: 9 9 9 SXMDRST5 F 0 4 a: 10 10 10 SXMDRST5 F 0 5 a: 18 18 18 SXMDRST5 F 0 6 a: 18 18 18 SXMDRST5 F 1 0 a: 11 11 11 SXMDRST5 F 1 1 a: 9 9 9 SXMDRST5 F 1 2 a: 9 9 9 SXMDRST5 F 1 3 a: 15 10 10 SXMDRST5 F 1 4 a: 18 18 18 SXMDRST5 F 1 5 a: 18 18 18 SXMDRST5 F 1 6 a: 18 18 18 SXMDRST5 F 2 0 a: 4 4 4 SXMDRST5 F 2 1 a: 6 6 6 SXMDRST5 F 2 2 a: 6 6 6 SXMDRST5 F 2 3 a: 13 13 13 SXMDRST5 F 2 4 a: 9 9 9 SXMDRST5 F 2 5 a: 9 9 9 SXMDRST5 F 2 6 a: 10 10 10 SXMDRST5 F 3 0 a: 4 4 4 SXMDRST5 F 3 1 a: 6 6 6 SXMDRST5 F 3 2 a: 13 13 13 SXMDRST5 F 3 3 a: 9 9 9 SXMDRST5 F 3 4 a: 9 9 9 SXMDRST5 F 3 5 a: 10 10 10 SXMDRST5 F 3 6 a: 18 18 18 SXMDRST5 F 0 0 b: 17 17 17 SXMDRST5 F 0 1 b: 17 17 17 SXMDRST5 F 0 2 b: 22 17 17 SXMDRST5 F 0 3 b: 18 18 18 SXMDRST5 F 0 4 b: 26 26 26 SXMDRST5 F 0 5 b: 26 26 26 SXMDRST5 F 0 6 b: 26 26 26 SXMDRST5 F 1 0 b: 11 11 11 SXMDRST5 F 1 1 b: 11 11 11 SXMDRST5 F 1 2 b: 15 15 15 SXMDRST5 F 1 3 b: 25 25 25 SXMDRST5 F 1 4 b: 25 25 25 SXMDRST5 F 1 5 b: 25 25 25 SXMDRST5 F 1 6 b: 26 26 26 SXMDRST5 F 2 0 b: 7 7 7 SXMDRST5 F 2 1 b: 7 7 7 SXMDRST5 F 2 2 b: 17 17 17 SXMDRST5 F 2 3 b: 17 17 17 SXMDRST5 F 2 4 b: 17 17 17 SXMDRST5 F 2 5 b: 18 18 18 SXMDRST5 F 2 6 b: 26 26 26 SXMDRST5 F 3 0 b: 7 7 7 SXMDRST5 F 3 1 b: 17 17 17 SXMDRST5 F 3 2 b: 17 17 17 SXMDRST5 F 3 3 b: 17 17 17 SXMDRST5 F 3 4 b: 18 18 18 SXMDRST5 F 3 5 b: 32 26 26 SXMDRST5 F 3 6 b: 26 26 26 SXMDRST5 end PASS ``` ### 16 October 2026 link sxmdrst7 Raw output: [sxmdrst7/SXMDRST7.txt](/tests/raw/20261016T1500Z-5501a-link/sxmdrst7/SXMDRST7.txt) ``` SXDEV I_MASK at init 3C040100 SXMDRST7 start SXMDRST7 c n 0 A: 61 61 61 SXMDRST7 c n 0 B: 70 70 74 SXMDRST7 c n 1 A: 62 68 62 SXMDRST7 c n 1 B: 79 79 79 SXMDRST7 c n 2 A: 74 70 70 SXMDRST7 c n 2 B: 85 79 79 SXMDRST7 c n 4 A: 79 79 79 SXMDRST7 c n 4 B: 89 93 89 SXMDRST7 c n l A: 71 71 71 SXMDRST7 c n l B: 83 83 87 SXMDRST7 c r 0 A: 61 61 61 SXMDRST7 c r 0 B: 76 70 70 SXMDRST7 c r 1 A: 61 61 61 SXMDRST7 c r 1 B: 70 74 70 SXMDRST7 c r 2 A: 67 61 67 SXMDRST7 c r 2 B: 83 79 83 SXMDRST7 c r 4 A: 70 70 70 SXMDRST7 c r 4 B: 83 79 79 SXMDRST7 c r l A: 70 75 70 SXMDRST7 c r l B: 83 83 83 SXMDRST7 c rr 0 A: 61 66 61 SXMDRST7 c rr 0 B: 70 75 70 SXMDRST7 c rr 1 A: 66 62 62 SXMDRST7 c rr 1 B: 76 70 75 SXMDRST7 c rr 2 A: 61 61 61 SXMDRST7 c rr 2 B: 70 70 70 SXMDRST7 c rr 4 A: 70 70 70 SXMDRST7 c rr 4 B: 79 79 79 SXMDRST7 c rr l A: 71 71 71 SXMDRST7 c rr l B: 75 79 75 SXMDRST7 c s 0 A: 62 66 62 SXMDRST7 c s 0 B: 79 83 79 SXMDRST7 c s 1 A: 74 70 70 SXMDRST7 c s 1 B: 79 79 83 SXMDRST7 c s 2 A: 71 71 71 SXMDRST7 c s 2 B: 79 83 79 SXMDRST7 c s 4 A: 75 71 75 SXMDRST7 c s 4 B: 89 89 93 SXMDRST7 c s l A: 71 74 71 SXMDRST7 c s l B: 90 86 86 SXMDRST7 c i 0 A: 53 57 53 SXMDRST7 c i 0 B: 70 74 70 SXMDRST7 c i 1 A: 65 61 61 SXMDRST7 c i 1 B: 74 70 76 SXMDRST7 c i 2 A: 62 62 62 SXMDRST7 c i 2 B: 70 74 70 SXMDRST7 c i 4 A: 66 62 62 SXMDRST7 c i 4 B: 79 79 79 SXMDRST7 c i l A: 71 71 71 SXMDRST7 c i l B: 79 75 75 SXMDRST7 w n 0 A: 30 30 30 SXMDRST7 w n 0 B: 32 32 32 SXMDRST7 w n 1 A: 31 31 31 SXMDRST7 w n 1 B: 33 33 33 SXMDRST7 w n 2 A: 31 31 31 SXMDRST7 w n 2 B: 34 34 34 SXMDRST7 w n 4 A: 31 31 31 SXMDRST7 w n 4 B: 36 36 36 SXMDRST7 w n l A: 61 61 61 SXMDRST7 w n l B: 39 39 39 SXMDRST7 w r 0 A: 28 28 28 SXMDRST7 w r 0 B: 35 35 35 SXMDRST7 w r 1 A: 23 29 29 SXMDRST7 w r 1 B: 31 31 31 SXMDRST7 w r 2 A: 30 30 30 SXMDRST7 w r 2 B: 32 32 32 SXMDRST7 w r 4 A: 31 31 31 SXMDRST7 w r 4 B: 34 34 34 SXMDRST7 w r l A: 31 31 31 SXMDRST7 w r l B: 35 35 35 SXMDRST7 w rr 0 A: 27 27 27 SXMDRST7 w rr 0 B: 29 29 29 SXMDRST7 w rr 1 A: 28 22 28 SXMDRST7 w rr 1 B: 30 30 30 SXMDRST7 w rr 2 A: 29 29 29 SXMDRST7 w rr 2 B: 31 31 31 SXMDRST7 w rr 4 A: 31 31 31 SXMDRST7 w rr 4 B: 33 33 33 SXMDRST7 w rr l A: 31 31 31 SXMDRST7 w rr l B: 35 35 35 SXMDRST7 w s 0 A: 42 42 42 SXMDRST7 w s 0 B: 32 32 32 SXMDRST7 w s 1 A: 31 31 31 SXMDRST7 w s 1 B: 38 38 38 SXMDRST7 w s 2 A: 31 31 31 SXMDRST7 w s 2 B: 34 34 34 SXMDRST7 w s 4 A: 31 31 31 SXMDRST7 w s 4 B: 36 36 36 SXMDRST7 w s l A: 31 31 31 SXMDRST7 w s l B: 39 39 39 SXMDRST7 w i 0 A: 29 29 29 SXMDRST7 w i 0 B: 31 31 31 SXMDRST7 w i 1 A: 30 30 30 SXMDRST7 w i 1 B: 32 32 32 SXMDRST7 w i 2 A: 31 31 31 SXMDRST7 w i 2 B: 33 33 33 SXMDRST7 w i 4 A: 31 31 31 SXMDRST7 w i 4 B: 35 35 35 SXMDRST7 w i l A: 31 31 31 SXMDRST7 w i l B: 35 35 35 SXMDRST7 end PASS ``` ### 17 October 2026 link sxmdrst8 Raw output: [sxmdrst8/SXMDRST8.txt](/tests/raw/20261017T0054Z-5501a-link/sxmdrst8/SXMDRST8.txt) ``` SXDEV I_MASK at init 3C040100 SXMDRST8 start SXMDRST8 T 1: 16 16 16 16 16 16 16 16 SXMDRST8 T 2: 18 23 18 18 18 23 18 18 SXMDRST8 T 3: 20 20 20 20 20 20 20 20 SXMDRST8 T 4: 22 22 22 22 22 22 22 22 SXMDRST8 T 5: 24 24 24 24 24 24 24 24 SXMDRST8 T 6: 26 26 26 26 26 26 26 26 SXMDRST8 T 7: 28 28 28 28 28 28 28 28 SXMDRST8 T 8: 30 30 40 30 30 30 30 30 SXMDRST8 T 9: 37 32 32 37 32 32 32 32 SXMDRST8 T 10: 34 34 44 34 34 34 44 34 SXMDRST8 T 11: 36 36 36 36 36 36 36 36 SXMDRST8 T 12: 38 38 38 38 48 38 48 38 SXMDRST8 T 13: 40 40 50 40 40 50 49 40 SXMDRST8 T 14: 42 42 42 42 52 42 42 42 SXMDRST8 T 15: 44 44 44 44 44 44 44 54 SXMDRST8 T 16: 46 46 46 46 46 46 46 46 SXMDRST8 T 17: 48 48 58 48 58 48 48 58 SXMDRST8 T 18: 50 50 50 50 50 50 50 50 SXMDRST8 T 19: 52 52 52 52 52 52 52 52 SXMDRST8 T 20: 54 64 54 54 59 54 54 64 SXMDRST8 T 21: 56 56 56 65 56 56 56 56 SXMDRST8 T 22: 58 58 58 58 68 58 58 58 SXMDRST8 T 23: 113 108 108 108 113 114 108 108 SXMDRST8 T 24: 62 62 62 62 62 62 62 62 SXMDRST8 M 0 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 0 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 0 5: A004001F A004001F A004001F A004001F SXMDRST8 M 0 6: A004001F A004001F A004001F A004001F SXMDRST8 M 0 7: A004001F A004001F A004001F A004001F SXMDRST8 M 0 8: A004001F A004001F A004001F A004001F SXMDRST8 M 0 10: A004001F A004001F A004001F A004001F SXMDRST8 M 0 12: A004001F A004001F A004001F A004001F SXMDRST8 M 0 14: A004001F A004001F A004001F A004001F SXMDRST8 M 0 16: A004001F A004001F A004001F A004001F SXMDRST8 M 1 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 1 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 1 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 1 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 1 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 1 8: 80040000 80040000 A004001F A004001F SXMDRST8 M 1 10: 80040000 80040000 A004001F A004001F SXMDRST8 M 1 12: 80040000 80040000 A004001F A004001F SXMDRST8 M 1 14: 80040000 80040000 A004001F A004001F SXMDRST8 M 1 16: 80040000 80040000 A004001F A004001F SXMDRST8 M 2 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 2 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 7: A004001F A004001F A004001F A004001F SXMDRST8 M 3 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 3 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 4 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 8 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 7: A004001F A004001F A004001F A004001F SXMDRST8 M 9 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 9 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 10 16: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 3: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 4: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 5: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 6: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 7: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 8: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 10: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 12: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 14: 80040000 80040000 80040000 80040000 SXMDRST8 M 11 16: 80040000 80040000 80040000 80040000 SXMDRST8 end PASS ``` ## References [^r1]: Hardware test run 20261016T0159Z-5501a-link: [SXMDRST.txt](/tests/raw/20261016T0159Z-5501a-link/sxmdrst/SXMDRST.txt). [^r2]: Hardware test run 20261016T0210Z-5501a-link: [SXMDRST2.txt](/tests/raw/20261016T0210Z-5501a-link/sxmdrst2/SXMDRST2.txt). [^r3]: Hardware test run 20261016T0222Z-5501a-link: [SXMDRST3.txt](/tests/raw/20261016T0222Z-5501a-link/sxmdrst3/SXMDRST3.txt). [^r5]: Hardware test run 20261016T0308Z-5501a-link: [SXMDRST5.txt](/tests/raw/20261016T0308Z-5501a-link/sxmdrst5/SXMDRST5.txt). [^r8]: Hardware test run 20261017T0054Z-5501a-link: [SXMDRST8.txt](/tests/raw/20261017T0054Z-5501a-link/sxmdrst8/SXMDRST8.txt).