MDEC Reset and Store Timing: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 14: | Line 14: | ||
| Each row runs one shape of code three times. The code runs either straight from RAM with the instruction cache cold (c) or a second time from the cache (w, warm). Before the reset store there is nothing (n), one RAM store (r), two RAM stores (rr), a scratchpad store (s) or an I/O store (i). Between the reset and the command there are 0, 1, 2 or 4 NOPs, or a status read (l).[^r1] The later programs time the same stores in system clock cycles on root counters 2 and 1.[^r2][^r3][^r8] | Each row runs one shape of code three times. The code runs either straight from RAM with the instruction cache cold (c) or a second time from the cache (w, warm). Before the reset store there is nothing (n), one RAM store (r), two RAM stores (rr), a scratchpad store (s) or an I/O store (i). Between the reset and the command there are 0, 1, 2 or 4 NOPs, or a status read (l).[^r1] The later programs time the same stores in system clock cycles on root counters 2 and 1.[^r2][^r3][^r8] | ||
| + | See also: | ||
| + | |||
| + | - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) | ||
| + | - [MDEC Block Timing](/tests/mdec-block-timing/) | ||
| + | |||
| ## Results | ## Results | ||