Root Counter Behavior: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| Every group masks IRQ4 to IRQ6 in I_MASK and polls I_STAT itself with interrupts off. Two counter reads in a row on root counter 2 are 4 system clock cycles apart, so a histogram of read values samples the counter every 4 cycles.[^run][^h-rc2] | Every group masks IRQ4 to IRQ6 in I_MASK and polls I_STAT itself with interrupts off. Two counter reads in a row on root counter 2 are 4 system clock cycles apart, so a histogram of read values samples the counter every 4 cycles.[^run][^h-rc2] | ||
| + | See also: | ||
| + | |||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | - [Timer Sync and SIO0 Timing](/tests/timer-sync-sio0-timing/) | ||
| + | |||
| ## Results | ## Results | ||