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--- title: Root Counter Behavior type: test summary: Measures root counter mode bits, counter writes, flags, interrupts, periods, clock sources and sync modes. category: Hardware tests info: Machine = SCPH-5501 info: Program = timers2 --- ## Overview The program tests the three [root counters](/hardware/timers/) at the points the register descriptions leave open. It writes each mode bit alone, writes the counter and target in different states, and counts how often each value is read with reset at small targets. It also follows flags 11 and 12 and the IRQ modes, and measures periods for every clock source, the delay to the first tick and the four sync modes. Its last group reads and writes the unused addresses.[^run] Every group masks IRQ4 to IRQ6 in I_MASK and polls I_STAT itself with interrupts off. Two counter reads in a row on root counter 2 are 4 system clock cycles apart, so a histogram of read values samples the counter every 4 cycles.[^run][^h-rc2] See also: - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) - [Timer Sync and SIO0 Timing](/tests/timer-sync-sio0-timing/) ## Results ### Mode Register Mode bits 0 to 9 keep the value written. Any write sets bit 10, and bits 11 to 15 read 0 after a write.[^h-rc1] The target register keeps 16 bits, and a 32-bit write keeps the lower half. The upper half of a 32-bit read of the target read 0000h on counters 1 and 2 and 0C04h on counter 0.[^h-rc1] ### Counter Writes A stopped counter (sync mode 0 on root counter 2) keeps a written value, and a 32-bit write keeps the lower half. Writing the counter equal to the target or to FFFFh on a stopped counter set flag 11: the mode read 0C01h. A mode write sets the counter to 0.[^h-rc2] A counter read straight after a counter write returns the value written, and a read straight after a mode write returns 0. On root counter 1 the read after a mode write returned 7.[^h-rc2] A running counter written onto its target sets flag 11. A counter written one past the target does not.[^h-rc4] ### Reset at Target With reset at target n and counting system clock cycles, the reads fit a period of n+2 cycles in which the counter holds 0 for two cycles. At target 3, 0 was read 1199 times and 1, 2 and 3 about 600 times each out of 3000. With target 0 and reset, the counter always reads 0 and flag 11 stays set.[^h-rc3][^h-rc4] On system clock / 8 the counter never reads the target value: with target 1 every read was 0, and with target 10 the reads ran from 0 to 9.[^h-rc3] ### Flags Flag 11 (target reached) and flag 12 (FFFFh reached) are set whether or not reset is on, and reading the mode clears them. A byte read of the mode's upper byte also clears them.[^h-rc4][^h-rc9] Polling saw flag 11 a few counts after the target: at counter 5017 with target 5000 and no reset, and at counter 15 after a reset at 5000. On system clock / 8, with target 100, the flag was first seen at 102.[^h-rc4] ### Interrupt Modes Table: Interrupt request at each event with IRQ at target on root counter 2 | Mode | IRQ | Bit 10 | | --- | --- | --- | | Pulse, repeat | every event | stays 1 except for a short pulse | | Pulse, one-shot | first event only | stays 1 | | Toggle, repeat | every other event | changes at each event | | Toggle, one-shot | first event only | stays 0 after the first event | Bit 10 read 0 in 236 of 4000 polls in pulse mode with target 30. With target 0 no IRQ occurred in pulse or toggle mode: bit 10 stayed 1 in pulse mode and 0 in toggle mode. With IRQ at FFFFh only and reset at target, no IRQ occurred because the counter never reached FFFFh.[^h-rc5] With IRQ at both target and FFFFh in repeat mode, both events raised an IRQ. In one-shot mode only the first event did. A new mode write sets bit 10 again and arms a one-shot counter for one more IRQ.[^h-rc5] ### Periods and Clock Sources Counter 0 on the dot clock counts dots, and the dots in one line depend on the horizontal resolution. The cycles per dot come from 8 periods of target 999.[^h-rc6] Table: Counter 0 on the dot clock | Horizontal resolution | System clocks per dot | Dots between two hblank ticks | | --- | --- | --- | | 256 | 6.30 to 6.31 | 339 to 341 | | 320 | 5.05 to 5.06 | 423 to 427 | | 368 | 4.42 | 484 to 488 | | 512 | 3.16 | 677 to 683 | | 640 | 2.53 | 849 to 854 | Counter 0 counted 2143 to 2154 system clock cycles between two hblank ticks of counter 1.[^h-rc8] ### First Tick After a mode write, root counter 2 counting system clock cycles first ticked 31 to 32 cycles later. The first sample of each row read about 60 cycles. On system clock / 8 and on the dot clock the first tick came 31 to 69 cycles later. Counter 1 on hblank first ticked 1681 to 2105 cycles after the mode write.[^h-rc7] ### Sync Modes Table: Sync modes on counters 0 and 1 | Counter | Sync mode | Result | | --- | --- | --- | | 0, system clock | 0, pause in hblank | 1613 to 1614 counts a line | | 0, system clock | 1, reset at hblank | 1625 to 1633 at a tick | | 0, system clock | 2, count in hblank only | 9 to 21 at a tick | | 0, dot clock 640 | 0, pause in hblank | 639 to 640 dots a line | | 1, hblank | free run | 263 lines from one vblank IRQ to the next | | 1, hblank | 0, pause in vblank | 239 lines between IRQs | | 1, hblank | 1, reset at vblank | 237 at the vblank IRQ | | 1, system clock | 1, reset at vblank | 55443 to 57883 at the vblank IRQ | In sync mode 3 bit 0 stays set in the mode register 5000 cycles after the blank. In that time counter 0 counted 3543 system clock cycles and counter 1 counted 240 hblanks.[^h-rc8] ### Unused Addresses and Narrow Access A word read of 1F80110Ch, 1F80111Ch or 1F80112Ch to 1F80113Ch returned 3C025A5Ah. The upper halfword of a word read of a mode or target register returned 3C02h. A halfword read of 1F801122h returned 03E0h and other unused halfwords 0000h. Byte reads of the counter and target return their bytes.[^h-rc9] A byte store to the counter at offset +0 writes the byte as the whole counter: AB at 1F801120h gave 00ABh. At offset +1 the byte lands in the upper half and the lower half is cleared, so AB gave AB00h. A byte store of the register 87654321h at offset +0 wrote 4321h, which is the lower halfword of the register. A byte store of 02h to 1F801125h wrote 0200h to the mode and reset the counter.[^h-rc9] ## Runs ### 27 September 2026 card-b Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/00RUN.txt) · [01RC1.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/01RC1.txt) · [02RC2.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/02RC2.txt) · [03RC3.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/03RC3.txt) · [04RC4.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/04RC4.txt) · [05RC5.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/05RC5.txt) · [06RC6.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/06RC6.txt) · [07RC7.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/07RC7.txt) · [08RC8.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/08RC8.txt) · [09RC9.txt](/tests/raw/20260927T0000Z-5501a-card-b/timers2/09RC9.txt) 00RUN.txt: ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 9 tests A chain program, linked at 80010000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR 8010E538 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010F0EC PRId 00000002 ``` 01RC1.txt: ``` ===== 01 RC1 TIMER MODE READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer modes at the start: 1C00 1D00 1C00, targets 0000 0000 0000 Each mode bit written alone, then two reads: Timer0 write 0001: read 0401 then 0401 Timer0 write 0002: read 0402 then 0402 Timer0 write 0004: read 0404 then 0404 Timer0 write 0008: read 0408 then 0408 Timer0 write 0010: read 0410 then 0410 Timer0 write 0020: read 0420 then 0420 Timer0 write 0040: read 0440 then 0440 Timer0 write 0080: read 0480 then 0480 Timer0 write 0100: read 0500 then 0500 Timer0 write 0200: read 0600 then 0600 Timer0 write 0400: read 0400 then 0400 Timer0 write 0800: read 0400 then 0400 Timer0 write 1000: read 0400 then 0400 Timer0 write 2000: read 0400 then 0400 Timer0 write 4000: read 0400 then 0400 Timer0 write 8000: read 0400 then 0400 Timer0 write 0000: read 0400 then 0400 Timer1 write 0001: read 0401 then 0401 Timer1 write 0002: read 0402 then 0402 Timer1 write 0004: read 0404 then 0404 Timer1 write 0008: read 0408 then 0408 Timer1 write 0010: read 0410 then 0410 Timer1 write 0020: read 0420 then 0420 Timer1 write 0040: read 0440 then 0440 Timer1 write 0080: read 0480 then 0480 Timer1 write 0100: read 0500 then 0500 Timer1 write 0200: read 0600 then 0600 Timer1 write 0400: read 0400 then 0400 Timer1 write 0800: read 0400 then 0400 Timer1 write 1000: read 0400 then 0400 Timer1 write 2000: read 0400 then 0400 Timer1 write 4000: read 0400 then 0400 Timer1 write 8000: read 0400 then 0400 Timer1 write 0000: read 0400 then 0400 Timer2 write 0001: read 0401 then 0401 Timer2 write 0002: read 0402 then 0402 Timer2 write 0004: read 0404 then 0404 Timer2 write 0008: read 0408 then 0408 Timer2 write 0010: read 0410 then 0410 Timer2 write 0020: read 0420 then 0420 Timer2 write 0040: read 0440 then 0440 Timer2 write 0080: read 0480 then 0480 Timer2 write 0100: read 0500 then 0500 Timer2 write 0200: read 0600 then 0600 Timer2 write 0400: read 0400 then 0400 Timer2 write 0800: read 0400 then 0400 Timer2 write 1000: read 0400 then 0400 Timer2 write 2000: read 0400 then 0400 Timer2 write 4000: read 0400 then 0400 Timer2 write 8000: read 0400 then 0400 Timer2 write 0000: read 0400 then 0400 Timer0 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0C00 Timer1 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Timer2 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Done. ``` 02RC2.txt: ``` ===== 02 RC2 TIMER COUNTER WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped (sync mode 0): write 1234 reads 1234, after 1000 cycles 1234 Timer2 stopped: 32 bit write ABCD4321 reads 4321, write FFFF reads FFFF Timer2 stopped: counter written = target 8000, mode after 500 cycles 0C01 Timer2 stopped: counter written FFFF, mode after 500 cycles 0C01 Timer2 stopped: counter 4321 then mode write, counter 0000, mode 0401 Timer2 sysclock, two counter reads in a row, the difference: 4 4 4 4 4 4 4 4 Timer2 sysclock, counter written 1000, read at once: 1000 1000 1000 1000 1000 1000 1000 1000 Timer2 sysclock, mode written 0, counter read at once: 0 0 0 0 0 0 0 0 Timer2 sysclock, no reset at target, counter written FFFC FFFD FFFE FFFF 0000, read at once: FFFC FFFD FFFE FFFF 0000 Timer2 sysclock, reset at target 1000, counter written 0FFC 0FFD 0FFE 0FFF 1000, read at once: 0FFC 0FFD 0FFE 0FFF 1000 Timer2 reset at target 1000, counter written 1100, after 400 cycles 12AD, mode 1C08 Timer2 reset at target, target lowered to 100 under the counter, after 400 cycles 0979, mode 0408 Timer2 sysclock/8, counter written 1000, after 800 cycles 1103 Timer0 and Timer1 sysclock, counter written 1000, read at once: 1000 1000 Timer0 and Timer1 sysclock, mode written 0, counter read at once: 0 7 Done. ``` 03RC3.txt: ``` ===== 03 RC3 TIMER HISTOGRAMS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 1, reads of each value of 3000: 0:1991 1:1009 2:0 3:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 2, reads of each value of 3000: 0:0 1:2961 2:39 3:0 4:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 3, reads of each value of 3000: 0:1200 1:599 2:600 3:601 4:0 5:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 10, reads of each value of 3000: 0:1016 1:0 2:0 3:977 4:9 5:1 6:9 7:983 8:0 9:0 10:5 11:0 12:0 higher:0 mode 0C08 Timer2 sysclock/8, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 1, reads of each value of 3000: 0:3000 1:0 2:0 3:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 10, reads of each value of 3000: 0:348 1:254 2:349 3:252 4:347 5:251 6:348 7:252 8:350 9:249 10:0 11:0 12:0 higher:0 mode 0E08 Timer0 sysclock, reset at target 10, reads of each value of 3000: 0:0 1:0 2:996 3:0 4:0 5:1 6:1003 7:0 8:0 9:0 10:1000 11:0 12:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 10, reads of each value of 3000: 0:990 1:0 2:0 3:991 4:0 5:1 6:19 7:991 8:0 9:0 10:8 11:0 12:0 higher:0 mode 0C08 Timer0 sysclock, reset at target 1, reads of each value of 3000: 0:1996 1:1004 2:0 3:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer0 dotclock 640 wide, reset at target 2, reads of each value of 3000: 0:1142 1:765 2:1090 3:3 4:0 higher:0 mode 0D08 Timer2 sysclock sync mode 1, reset at target 3, reads of each value of 3000: 0:1198 1:601 2:600 3:601 4:0 5:0 higher:0 mode 0C0B Done. ``` 04RC4.txt: ``` ===== 04 RC4 TIMER FLAGS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 target 300, no reset, after 2000 cycles: mode 0C00 then 0400, counter 2054 Timer2 target 0, no reset, after 200 cycles: mode 0C00 then 0400, counter 235 Timer2 target 0, reset at target, after 200 cycles: mode 0C08 then 0C08, counter 0 Timer2 counter written FFF0, after 200 cycles: mode 1400, counter 210 Timer2 running, counter written onto target 8000: mode after 40 cycles 0C00 Timer2 running, counter written 8001 past target 8000: mode after 40 cycles 0400 Timers 1 and 2 past target: Timer1 mode 0C00, then Timer2 mode 0C00 then 0400 Timer2 sysclock target 5000 no reset, counter when bit 11 is first seen: 5025 5017 5017 5017 5017 5017 5017 5017 Timer2 sysclock target 5000 reset, counter when bit 11 is first seen: 20 15 15 15 15 15 15 15 Timer2 sysclock/8 target 100 no reset, counter when bit 11 is first seen: 102 102 102 102 102 103 101 102 Timer2 sysclock from F000, counter when bit 12 is first seen: 22 20 20 20 20 20 20 20 Done. ``` 05RC5.txt: ``` ===== 05 RC5 TIMER IRQ | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Each event: bit 10 before>at the flag, flags (1 target, 2 FFFF), I_STAT bit 6 at once and 16 cycles on Pulse, repeat, IRQ at target (mode 0258): 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>0 f1 i11; polls with bit 10 clear 1, I_STAT 400 cycles after the last 0, mode 0658 Pulse, one-shot, IRQ at target (mode 0218): 1>1 f1 i11 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0618 Toggle, repeat, IRQ at target (mode 02D8): 1>1 f1 i11 0>1 f1 i00 1>1 f1 i11 0>1 f1 i00 1>0 f1 i11 0>1 f1 i00 1>0 f1 i11 0>0 f1 i00; polls with bit 10 clear 267, I_STAT 400 cycles after the last 0, mode 06D8 Toggle, one-shot, IRQ at target (mode 0298): 1>1 f1 i11 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00; polls with bit 10 clear 469, I_STAT 400 cycles after the last 0, mode 0298 No IRQ enabled, repeat (mode 0248): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0648 IRQ at FFFF only, reset at target (mode 0268): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0668 Sysclock, IRQ at target 8000 and FFFF, repeat (mode 0070): 1>1 f1 i11 1>1 f2 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0470 Sysclock, IRQ at target 8000 and FFFF, one-shot (mode 0030): 1>1 f1 i11 1>1 f2 i00 1>1 f1 i00 1>1 f2 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0430 Toggle, repeat, IRQ at target 8000 and FFFF (mode 00F0): 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00; polls with bit 10 clear 4265, I_STAT 400 cycles after the last 0, mode 04F0 Pulse, repeat, IRQ at target FFFF with reset (mode 0078): 1>1 f3 i11 1>1 f3 i11 1>1 f3 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0478 Sysclock pulse repeat, target 30 (mode 0058): of 4000 polls bit 10 read 0 236, bit 11 set 3529, I_STAT bit 6 seen 3060 Sysclock pulse repeat, target 0 (mode 0058): of 4000 polls bit 10 read 0 0, bit 11 set 4000, I_STAT bit 6 seen 0 Sysclock toggle repeat, target 0 (mode 00D8): of 4000 polls bit 10 read 0 4000, bit 11 set 4000, I_STAT bit 6 seen 0 Toggle one-shot (mode 0298): first event mode 0A98 I_STAT 1; next two 0A98 0A98 I_STAT 0; mode written again reads 0698; next event 0A98 I_STAT 1; next 0A98 I_STAT 0 Pulse one-shot (mode 0218): first event mode 0E18 I_STAT 1; next two 0E18 0E18 I_STAT 0; mode written again reads 0618; next event 0A18 I_STAT 1; next 0E18 I_STAT 0 Toggle repeat (mode 02D8): first event mode 0ED8 I_STAT 1; next two 0ED8 0AD8 I_STAT 1; mode written again reads 06D8; next event 0AD8 I_STAT 1; next 0ED8 I_STAT 0 Sysclock target 5000 reset, counter when I_STAT bit 6 is first seen: 28 16 20 24 16 20 24 16 Sysclock target 5000 reset, counter when bit 11 is first seen: 13 16 10 16 10 16 10 16 Sysclock target 5000 reset, first counter read after the reset: 0 8 11 1 4 7 10 0 Done. ``` 06RC6.txt: ``` ===== 06 RC6 TIMER PERIODS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock reset at target 999, 64 periods, cycles: 65067 65046 66073 66066 Timer1 sysclock reset at target 999, 64 periods, cycles: 64050 66065 65050 66084 Timer0 sysclock reset at target 999, 64 periods, cycles: 65059 66067 65049 65046 Timer2 sysclock reset at target FFFF, 16 periods, cycles: 1114136 1048547 Timer2 sysclock no reset (wrap at FFFF), 16 periods, cycles: 1048553 1048564 Timer2 sysclock/8 reset at target 999, 16 periods, cycles: 127846 127847 127887 127877 Timer2 sysclock/8 no reset (wrap at FFFF), 2 periods, cycles: 1048576 1048550 Timer1 hblank reset at target 99, 4 periods, cycles: 852404 852404 Timer1 hblank reset at target 0, 64 periods, cycles: 3476 3464 Timer0 dotclock 256 wide reset at target 999, 8 periods, cycles: 50432 44144 Timer0 dotclock 256 wide, dots between two hblank ticks: 341 339 341 339 341 339 341 340 Timer0 dotclock 320 wide reset at target 999, 8 periods, cycles: 35382 40396 Timer0 dotclock 320 wide, dots between two hblank ticks: 423 426 426 426 426 426 427 427 Timer0 dotclock 368 wide reset at target 999, 8 periods, cycles: 30945 35328 Timer0 dotclock 368 wide, dots between two hblank ticks: 485 487 484 487 484 487 487 487 Timer0 dotclock 512 wide reset at target 999, 8 periods, cycles: 25242 25242 Timer0 dotclock 512 wide, dots between two hblank ticks: 681 682 679 682 682 682 682 682 Timer0 dotclock 640 wide reset at target 999, 8 periods, cycles: 20224 20173 Timer0 dotclock 640 wide, dots between two hblank ticks: 848 849 853 853 853 853 854 854 Done. ``` 07RC7.txt: ``` ===== 07 RC7 TIMER FIRST TICK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, mode write to first tick: 61 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Timer2 sysclock, counter write to first tick: 59 32 32 32 32 32 37 32 32 32 32 32 32 32 32 32 Timer2 sysclock/8, mode write to first tick: 61 31 68 31 31 48 48 48 31 31 48 48 48 31 31 48 Timer2 sysclock/8, counter write to first tick: 59 69 32 49 49 32 49 49 32 49 49 32 49 49 32 49 Timer0 dotclock 640 wide, mode write to first tick: 61 68 48 31 48 48 37 31 48 31 31 48 48 31 31 48 Timer0 dotclock 640 wide, counter write to first tick: 59 69 49 32 32 32 32 32 32 32 32 32 32 32 49 32 Timer0 dotclock 256 wide, mode write to first tick: 61 31 68 48 48 48 48 48 48 48 48 31 48 48 48 48 Timer1 hblank, mode write to first tick: 1659 2105 2105 2094 2083 2072 2061 2050 2039 2028 2006 2006 1984 1973 1973 1951 Done. ``` 08RC8.txt: ``` ===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer0 sysclock free, cycles between two hblank ticks: 2146 2154 2143 2154 2143 2154 2154 2154 Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1613 1613 1613 1614 1614 1614 Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1637 1630 1634 1627 1630 1623 1627 1631 Timer0 sysclock sync 2 (count in hblank only), value at a tick: 25 18 11 15 19 12 16 19 Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 639 640 639 639 639 Timer0 dotclock sync 1, value at a tick: 647 644 641 644 644 642 643 645 Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55425 57884 57876 57880 Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20165 20113 20094 20121 Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239 Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263 Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237 Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3547 Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1923 Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240 Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5146 Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28492 Done. ``` 09RC9.txt: ``` ===== 09 RC9 TIMER UNUSED ADDR | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped at 1234, target 5678. Reads: lw 1F801100: 0000DAA3 lw 1F801104: 3C021C00 lw 1F801108: 3C020000 lw 1F80110C: 3C025A5A lw 1F80111C: 3C025A5A lw 1F80112C: 3C025A5A lw 1F801130: 3C025A5A lw 1F801134: 3C025A5A lw 1F801138: 3C025A5A lw 1F80113C: 3C025A5A lhu 1F801122: 000003E0 lhu 1F801126: 00000000 lhu 1F80112A: 00000000 lhu 1F80112E: 00000000 lhu 1F801132: 00000000 lhu 1F80113E: 00000000 lbu 1F801120: 00000034 lbu 1F801121: 00000012 lbu 1F801128: 00000078 lbu 1F801129: 00000056 lbu 1F80112C: 00000000 lbu 1F801130: 00000000 lbu 1F801131: 00000000 lbu 1F80113F: 00000090 Timer2 past target: lbu 1F801125 0C, then lhu mode 0400 Timer2 past target: lbu 1F801124 00, then lhu mode 0400 Narrow stores to stopped Timer2 (counter 1234, target 5678): sb 000000AB at 1F801120: counter 00AB mode 0401 target 5678 sb 000000AB at 1F801121: counter AB00 mode 0401 target 5678 sb 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 00004321 at 1F801122: counter 0000 mode 0401 target 5678 sb 00000002 at 1F801125: counter 0002 mode 0600 target 5678 sb 00000011 at 1F801128: counter 1234 mode 0401 target 0011 sb 00000011 at 1F801129: counter 1234 mode 0401 target 1100 sh 00000011 at 1F80112A: counter 1234 mode 0401 target 0000 sb 00000011 at 1F80112C: counter 1234 mode 0401 target 5678 Done. ``` ### 27 September 2026 card-g Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/00RUN.txt) · [01RC1.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/01RC1.txt) · [02RC2.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/02RC2.txt) · [03RC3.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/03RC3.txt) · [04RC4.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/04RC4.txt) · [05RC5.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/05RC5.txt) · [06RC6.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/06RC6.txt) · [07RC7.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/07RC7.txt) · [08RC8.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/08RC8.txt) · [09RC9.txt](/tests/raw/20260927T0000Z-5501a-card-g/timers2/09RC9.txt) 00RUN.txt: ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 9 tests A chain program, linked at 80010000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR 8010E780 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010F2EC PRId 00000002 ``` 01RC1.txt: ``` ===== 01 RC1 TIMER MODE READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer modes at the start: 1C00 1D00 1C00, targets 0000 0000 0000 Each mode bit written alone, then two reads: Timer0 write 0001: read 0401 then 0401 Timer0 write 0002: read 0402 then 0402 Timer0 write 0004: read 0404 then 0404 Timer0 write 0008: read 0408 then 0408 Timer0 write 0010: read 0410 then 0410 Timer0 write 0020: read 0420 then 0420 Timer0 write 0040: read 0440 then 0440 Timer0 write 0080: read 0480 then 0480 Timer0 write 0100: read 0500 then 0500 Timer0 write 0200: read 0600 then 0600 Timer0 write 0400: read 0400 then 0400 Timer0 write 0800: read 0400 then 0400 Timer0 write 1000: read 0400 then 0400 Timer0 write 2000: read 0400 then 0400 Timer0 write 4000: read 0400 then 0400 Timer0 write 8000: read 0400 then 0400 Timer0 write 0000: read 0400 then 0400 Timer1 write 0001: read 0401 then 0401 Timer1 write 0002: read 0402 then 0402 Timer1 write 0004: read 0404 then 0404 Timer1 write 0008: read 0408 then 0408 Timer1 write 0010: read 0410 then 0410 Timer1 write 0020: read 0420 then 0420 Timer1 write 0040: read 0440 then 0440 Timer1 write 0080: read 0480 then 0480 Timer1 write 0100: read 0500 then 0500 Timer1 write 0200: read 0600 then 0600 Timer1 write 0400: read 0400 then 0400 Timer1 write 0800: read 0400 then 0400 Timer1 write 1000: read 0400 then 0400 Timer1 write 2000: read 0400 then 0400 Timer1 write 4000: read 0400 then 0400 Timer1 write 8000: read 0400 then 0400 Timer1 write 0000: read 0400 then 0400 Timer2 write 0001: read 0401 then 0401 Timer2 write 0002: read 0402 then 0402 Timer2 write 0004: read 0404 then 0404 Timer2 write 0008: read 0408 then 0408 Timer2 write 0010: read 0410 then 0410 Timer2 write 0020: read 0420 then 0420 Timer2 write 0040: read 0440 then 0440 Timer2 write 0080: read 0480 then 0480 Timer2 write 0100: read 0500 then 0500 Timer2 write 0200: read 0600 then 0600 Timer2 write 0400: read 0400 then 0400 Timer2 write 0800: read 0400 then 0400 Timer2 write 1000: read 0400 then 0400 Timer2 write 2000: read 0400 then 0400 Timer2 write 4000: read 0400 then 0400 Timer2 write 8000: read 0400 then 0400 Timer2 write 0000: read 0400 then 0400 Timer0 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0C00 Timer1 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Timer2 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Done. ``` 02RC2.txt: ``` ===== 02 RC2 TIMER COUNTER WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped (sync mode 0): write 1234 reads 1234, after 1000 cycles 1234 Timer2 stopped: 32 bit write ABCD4321 reads 4321, write FFFF reads FFFF Timer2 stopped: counter written = target 8000, mode after 500 cycles 0C01 Timer2 stopped: counter written FFFF, mode after 500 cycles 0C01 Timer2 stopped: counter 4321 then mode write, counter 0000, mode 0401 Timer2 sysclock, two counter reads in a row, the difference: 4 4 4 4 4 4 4 4 Timer2 sysclock, counter written 1000, read at once: 1000 1000 1000 1000 1000 1000 1000 1000 Timer2 sysclock, mode written 0, counter read at once: 0 0 0 0 0 0 0 0 Timer2 sysclock, no reset at target, counter written FFFC FFFD FFFE FFFF 0000, read at once: FFFC FFFD FFFE FFFF 0000 Timer2 sysclock, reset at target 1000, counter written 0FFC 0FFD 0FFE 0FFF 1000, read at once: 0FFC 0FFD 0FFE 0FFF 1000 Timer2 reset at target 1000, counter written 1100, after 400 cycles 12AD, mode 1C08 Timer2 reset at target, target lowered to 100 under the counter, after 400 cycles 0979, mode 0408 Timer2 sysclock/8, counter written 1000, after 800 cycles 1103 Timer0 and Timer1 sysclock, counter written 1000, read at once: 1000 1000 Timer0 and Timer1 sysclock, mode written 0, counter read at once: 0 7 Done. ``` 03RC3.txt: ``` ===== 03 RC3 TIMER HISTOGRAMS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 1, reads of each value of 3000: 0:2010 1:990 2:0 3:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 2, reads of each value of 3000: 0:37 1:1 2:2962 3:0 4:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 3, reads of each value of 3000: 0:1199 1:600 2:600 3:601 4:0 5:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 10, reads of each value of 3000: 0:0 1:989 2:0 3:0 4:0 5:986 6:27 7:0 8:0 9:988 10:10 11:0 12:0 higher:0 mode 0C08 Timer2 sysclock/8, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 1, reads of each value of 3000: 0:3000 1:0 2:0 3:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 10, reads of each value of 3000: 0:348 1:254 2:349 3:252 4:347 5:251 6:348 7:252 8:350 9:249 10:0 11:0 12:0 higher:0 mode 0E08 Timer0 sysclock, reset at target 10, reads of each value of 3000: 0:0 1:0 2:996 3:0 4:0 5:1 6:1003 7:0 8:0 9:0 10:1000 11:0 12:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 10, reads of each value of 3000: 0:990 1:0 2:0 3:991 4:0 5:1 6:19 7:991 8:0 9:0 10:8 11:0 12:0 higher:0 mode 0C08 Timer0 sysclock, reset at target 1, reads of each value of 3000: 0:1996 1:1004 2:0 3:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer0 dotclock 640 wide, reset at target 2, reads of each value of 3000: 0:1617 1:620 2:637 3:126 4:0 higher:0 mode 0D08 Timer2 sysclock sync mode 1, reset at target 3, reads of each value of 3000: 0:1198 1:601 2:600 3:601 4:0 5:0 higher:0 mode 0C0B Done. ``` 04RC4.txt: ``` ===== 04 RC4 TIMER FLAGS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 target 300, no reset, after 2000 cycles: mode 0C00 then 0400, counter 2054 Timer2 target 0, no reset, after 200 cycles: mode 0C00 then 0400, counter 238 Timer2 target 0, reset at target, after 200 cycles: mode 0C08 then 0C08, counter 0 Timer2 counter written FFF0, after 200 cycles: mode 1400, counter 210 Timer2 running, counter written onto target 8000: mode after 40 cycles 0C00 Timer2 running, counter written 8001 past target 8000: mode after 40 cycles 0400 Timers 1 and 2 past target: Timer1 mode 0C00, then Timer2 mode 0C00 then 0400 Timer2 sysclock target 5000 no reset, counter when bit 11 is first seen: 5025 5017 5017 5017 5017 5017 5017 5017 Timer2 sysclock target 5000 reset, counter when bit 11 is first seen: 20 15 15 15 15 15 15 15 Timer2 sysclock/8 target 100 no reset, counter when bit 11 is first seen: 103 102 102 102 102 102 102 102 Timer2 sysclock from F000, counter when bit 12 is first seen: 22 20 20 20 20 20 20 20 Done. ``` 05RC5.txt: ``` ===== 05 RC5 TIMER IRQ | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Each event: bit 10 before>at the flag, flags (1 target, 2 FFFF), I_STAT bit 6 at once and 16 cycles on Pulse, repeat, IRQ at target (mode 0258): 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0658 Pulse, one-shot, IRQ at target (mode 0218): 1>1 f1 i11 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0618 Toggle, repeat, IRQ at target (mode 02D8): 1>0 f1 i11 0>1 f1 i00 1>1 f1 i11 0>1 f1 i00 1>0 f1 i11 0>1 f1 i00 1>0 f1 i11 0>1 f1 i00; polls with bit 10 clear 266, I_STAT 400 cycles after the last 0, mode 06D8 Toggle, one-shot, IRQ at target (mode 0298): 1>1 f1 i11 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00; polls with bit 10 clear 469, I_STAT 400 cycles after the last 0, mode 0298 No IRQ enabled, repeat (mode 0248): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0648 IRQ at FFFF only, reset at target (mode 0268): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0668 Sysclock, IRQ at target 8000 and FFFF, repeat (mode 0070): 1>1 f1 i11 1>1 f2 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0470 Sysclock, IRQ at target 8000 and FFFF, one-shot (mode 0030): 1>1 f1 i11 1>1 f2 i00 1>1 f1 i00 1>1 f2 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0430 Toggle, repeat, IRQ at target 8000 and FFFF (mode 00F0): 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00; polls with bit 10 clear 4265, I_STAT 400 cycles after the last 0, mode 04F0 Pulse, repeat, IRQ at target FFFF with reset (mode 0078): 1>1 f3 i11 1>1 f3 i11 1>1 f3 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0478 Sysclock pulse repeat, target 30 (mode 0058): of 4000 polls bit 10 read 0 236, bit 11 set 3529, I_STAT bit 6 seen 3060 Sysclock pulse repeat, target 0 (mode 0058): of 4000 polls bit 10 read 0 0, bit 11 set 4000, I_STAT bit 6 seen 0 Sysclock toggle repeat, target 0 (mode 00D8): of 4000 polls bit 10 read 0 4000, bit 11 set 4000, I_STAT bit 6 seen 0 Toggle one-shot (mode 0298): first event mode 0A98 I_STAT 1; next two 0A98 0A98 I_STAT 0; mode written again reads 0698; next event 0A98 I_STAT 1; next 0A98 I_STAT 0 Pulse one-shot (mode 0218): first event mode 0E18 I_STAT 1; next two 0E18 0E18 I_STAT 0; mode written again reads 0618; next event 0A18 I_STAT 1; next 0E18 I_STAT 0 Toggle repeat (mode 02D8): first event mode 0ED8 I_STAT 1; next two 0ED8 0AD8 I_STAT 1; mode written again reads 06D8; next event 0AD8 I_STAT 1; next 0ED8 I_STAT 0 Sysclock target 5000 reset, counter when I_STAT bit 6 is first seen: 28 16 20 24 16 20 24 16 Sysclock target 5000 reset, counter when bit 11 is first seen: 13 16 10 16 10 16 10 16 Sysclock target 5000 reset, first counter read after the reset: 0 8 11 1 4 7 10 0 Done. ``` 06RC6.txt: ``` ===== 06 RC6 TIMER PERIODS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock reset at target 999, 64 periods, cycles: 65061 65047 66065 65050 Timer1 sysclock reset at target 999, 64 periods, cycles: 65045 65046 64051 65070 Timer0 sysclock reset at target 999, 64 periods, cycles: 66069 66073 65050 65060 Timer2 sysclock reset at target FFFF, 16 periods, cycles: 1048583 1048559 Timer2 sysclock no reset (wrap at FFFF), 16 periods, cycles: 1048547 1048559 Timer2 sysclock/8 reset at target 999, 16 periods, cycles: 127846 127877 127887 127877 Timer2 sysclock/8 no reset (wrap at FFFF), 2 periods, cycles: 1048576 1048550 Timer1 hblank reset at target 99, 4 periods, cycles: 852404 852404 Timer1 hblank reset at target 0, 64 periods, cycles: 3476 3464 Timer0 dotclock 256 wide reset at target 999, 8 periods, cycles: 50432 50483 Timer0 dotclock 256 wide, dots between two hblank ticks: 339 341 339 341 339 341 340 342 Timer0 dotclock 320 wide reset at target 999, 8 periods, cycles: 40397 40396 Timer0 dotclock 320 wide, dots between two hblank ticks: 423 424 426 424 426 426 426 426 Timer0 dotclock 368 wide reset at target 999, 8 periods, cycles: 30976 35344 Timer0 dotclock 368 wide, dots between two hblank ticks: 484 484 487 488 487 487 487 487 Timer0 dotclock 512 wide reset at target 999, 8 periods, cycles: 25242 25242 Timer0 dotclock 512 wide, dots between two hblank ticks: 677 683 679 682 678 682 679 682 Timer0 dotclock 640 wide reset at target 999, 8 periods, cycles: 20224 20172 Timer0 dotclock 640 wide, dots between two hblank ticks: 847 849 854 849 853 853 853 853 Done. ``` 07RC7.txt: ``` ===== 07 RC7 TIMER FIRST TICK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, mode write to first tick: 61 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Timer2 sysclock, counter write to first tick: 59 32 32 32 32 32 37 32 32 32 32 32 32 32 32 32 Timer2 sysclock/8, mode write to first tick: 61 31 68 31 31 48 48 48 31 31 48 48 48 31 31 48 Timer2 sysclock/8, counter write to first tick: 59 69 32 49 49 32 49 49 32 49 49 32 49 49 32 49 Timer0 dotclock 640 wide, mode write to first tick: 61 31 33 31 68 31 31 48 48 31 31 48 48 31 31 48 Timer0 dotclock 640 wide, counter write to first tick: 59 69 49 32 32 32 32 32 32 32 32 32 32 32 49 32 Timer0 dotclock 256 wide, mode write to first tick: 61 68 48 48 48 48 31 48 48 48 48 48 48 31 48 31 Timer1 hblank, mode write to first tick: 1736 2105 2105 2094 2094 2072 2061 2039 2039 2028 2010 2006 1984 1973 1973 1951 Done. ``` 08RC8.txt: ``` ===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer0 sysclock free, cycles between two hblank ticks: 2140 2154 2154 2154 2143 2154 2143 2154 Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1614 1614 1614 1614 1614 1613 Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1634 1627 1631 1624 1628 1632 1625 1629 Timer0 sysclock sync 2 (count in hblank only), value at a tick: 16 9 13 17 15 19 12 16 Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 639 639 639 639 639 Timer0 dotclock sync 1, value at a tick: 646 644 641 642 644 641 643 644 Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55470 57885 57877 57881 Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20169 20117 20102 20109 Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239 Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263 Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237 Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3578 Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1941 Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240 Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5155 Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28484 Done. ``` 09RC9.txt: ``` ===== 09 RC9 TIMER UNUSED ADDR | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped at 1234, target 5678. Reads: lw 1F801100: 0000DA3D lw 1F801104: 3C021C00 lw 1F801108: 3C020000 lw 1F80110C: 3C025A5A lw 1F80111C: 3C025A5A lw 1F80112C: 3C025A5A lw 1F801130: 3C025A5A lw 1F801134: 3C025A5A lw 1F801138: 3C025A5A lw 1F80113C: 3C025A5A lhu 1F801122: 000003E0 lhu 1F801126: 00000000 lhu 1F80112A: 00000000 lhu 1F80112E: 00000000 lhu 1F801132: 00000000 lhu 1F80113E: 00000000 lbu 1F801120: 00000034 lbu 1F801121: 00000012 lbu 1F801128: 00000078 lbu 1F801129: 00000056 lbu 1F80112C: 00000000 lbu 1F801130: 00000000 lbu 1F801131: 00000000 lbu 1F80113F: 00000090 Timer2 past target: lbu 1F801125 0C, then lhu mode 0400 Timer2 past target: lbu 1F801124 00, then lhu mode 0400 Narrow stores to stopped Timer2 (counter 1234, target 5678): sb 000000AB at 1F801120: counter 00AB mode 0401 target 5678 sb 000000AB at 1F801121: counter AB00 mode 0401 target 5678 sb 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 00004321 at 1F801122: counter 0000 mode 0401 target 5678 sb 00000002 at 1F801125: counter 0003 mode 0600 target 5678 sb 00000011 at 1F801128: counter 1234 mode 0401 target 0011 sb 00000011 at 1F801129: counter 1234 mode 0401 target 1100 sh 00000011 at 1F80112A: counter 1234 mode 0401 target 0000 sb 00000011 at 1F80112C: counter 1234 mode 0401 target 5678 Done. ``` ### 27 September 2026 card-g3 Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/00RUN.txt) · [01RC1.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/01RC1.txt) · [02RC2.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/02RC2.txt) · [03RC3.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/03RC3.txt) · [04RC4.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/04RC4.txt) · [05RC5.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/05RC5.txt) · [06RC6.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/06RC6.txt) · [07RC7.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/07RC7.txt) · [08RC8.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/08RC8.txt) · [09RC9.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers2/09RC9.txt) 00RUN.txt: ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 9 tests A chain program, linked at 80100000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR 8001BB54 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 40000000 Cause 00000020 EPC 80020100 PRId 00000002 ``` 01RC1.txt: ``` ===== 01 RC1 TIMER MODE READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer modes at the start: 1C00 1D00 1C00, targets 0000 0000 0000 Each mode bit written alone, then two reads: Timer0 write 0001: read 0401 then 0401 Timer0 write 0002: read 0402 then 0402 Timer0 write 0004: read 0404 then 0404 Timer0 write 0008: read 0408 then 0408 Timer0 write 0010: read 0410 then 0410 Timer0 write 0020: read 0420 then 0420 Timer0 write 0040: read 0440 then 0440 Timer0 write 0080: read 0480 then 0480 Timer0 write 0100: read 0500 then 0500 Timer0 write 0200: read 0600 then 0600 Timer0 write 0400: read 0400 then 0400 Timer0 write 0800: read 0400 then 0400 Timer0 write 1000: read 0400 then 0400 Timer0 write 2000: read 0400 then 0400 Timer0 write 4000: read 0400 then 0400 Timer0 write 8000: read 0400 then 0400 Timer0 write 0000: read 0400 then 0400 Timer1 write 0001: read 0401 then 0401 Timer1 write 0002: read 0402 then 0402 Timer1 write 0004: read 0404 then 0404 Timer1 write 0008: read 0408 then 0408 Timer1 write 0010: read 0410 then 0410 Timer1 write 0020: read 0420 then 0420 Timer1 write 0040: read 0440 then 0440 Timer1 write 0080: read 0480 then 0480 Timer1 write 0100: read 0500 then 0500 Timer1 write 0200: read 0600 then 0600 Timer1 write 0400: read 0400 then 0400 Timer1 write 0800: read 0400 then 0400 Timer1 write 1000: read 0400 then 0400 Timer1 write 2000: read 0400 then 0400 Timer1 write 4000: read 0400 then 0400 Timer1 write 8000: read 0400 then 0400 Timer1 write 0000: read 0400 then 0400 Timer2 write 0001: read 0401 then 0401 Timer2 write 0002: read 0402 then 0402 Timer2 write 0004: read 0404 then 0404 Timer2 write 0008: read 0408 then 0408 Timer2 write 0010: read 0410 then 0410 Timer2 write 0020: read 0420 then 0420 Timer2 write 0040: read 0440 then 0440 Timer2 write 0080: read 0480 then 0480 Timer2 write 0100: read 0500 then 0500 Timer2 write 0200: read 0600 then 0600 Timer2 write 0400: read 0400 then 0400 Timer2 write 0800: read 0400 then 0400 Timer2 write 1000: read 0400 then 0400 Timer2 write 2000: read 0400 then 0400 Timer2 write 4000: read 0400 then 0400 Timer2 write 8000: read 0400 then 0400 Timer2 write 0000: read 0400 then 0400 Timer0 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0C04 Timer1 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Timer2 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Done. ``` 02RC2.txt: ``` ===== 02 RC2 TIMER COUNTER WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped (sync mode 0): write 1234 reads 1234, after 1000 cycles 1234 Timer2 stopped: 32 bit write ABCD4321 reads 4321, write FFFF reads FFFF Timer2 stopped: counter written = target 8000, mode after 500 cycles 0C01 Timer2 stopped: counter written FFFF, mode after 500 cycles 0C01 Timer2 stopped: counter 4321 then mode write, counter 0000, mode 0401 Timer2 sysclock, two counter reads in a row, the difference: 4 4 4 4 4 4 4 4 Timer2 sysclock, counter written 1000, read at once: 1000 1000 1000 1000 1000 1000 1000 1000 Timer2 sysclock, mode written 0, counter read at once: 0 0 0 0 0 0 0 0 Timer2 sysclock, no reset at target, counter written FFFC FFFD FFFE FFFF 0000, read at once: FFFC FFFD FFFE FFFF 0000 Timer2 sysclock, reset at target 1000, counter written 0FFC 0FFD 0FFE 0FFF 1000, read at once: 0FFC 0FFD 0FFE 0FFF 1000 Timer2 reset at target 1000, counter written 1100, after 400 cycles 12AD, mode 1C08 Timer2 reset at target, target lowered to 100 under the counter, after 400 cycles 0979, mode 0408 Timer2 sysclock/8, counter written 1000, after 800 cycles 1103 Timer0 and Timer1 sysclock, counter written 1000, read at once: 1000 1000 Timer0 and Timer1 sysclock, mode written 0, counter read at once: 0 7 Done. ``` 03RC3.txt: ``` ===== 03 RC3 TIMER HISTOGRAMS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 1, reads of each value of 3000: 0:2010 1:990 2:0 3:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 2, reads of each value of 3000: 0:37 1:1 2:2962 3:0 4:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 3, reads of each value of 3000: 0:1201 1:602 2:599 3:598 4:0 5:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 10, reads of each value of 3000: 0:1016 1:0 2:0 3:977 4:9 5:1 6:9 7:983 8:0 9:0 10:5 11:0 12:0 higher:0 mode 0C08 Timer2 sysclock/8, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 1, reads of each value of 3000: 0:3000 1:0 2:0 3:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 10, reads of each value of 3000: 0:348 1:254 2:349 3:252 4:347 5:251 6:348 7:252 8:350 9:249 10:0 11:0 12:0 higher:0 mode 0E08 Timer0 sysclock, reset at target 10, reads of each value of 3000: 0:0 1:0 2:996 3:0 4:0 5:1 6:1003 7:0 8:0 9:0 10:1000 11:0 12:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 10, reads of each value of 3000: 0:990 1:0 2:0 3:991 4:0 5:1 6:19 7:991 8:0 9:0 10:8 11:0 12:0 higher:0 mode 0C08 Timer0 sysclock, reset at target 1, reads of each value of 3000: 0:1996 1:1004 2:0 3:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer0 dotclock 640 wide, reset at target 2, reads of each value of 3000: 0:1609 1:627 2:631 3:133 4:0 higher:0 mode 0D08 Timer2 sysclock sync mode 1, reset at target 3, reads of each value of 3000: 0:1198 1:601 2:600 3:601 4:0 5:0 higher:0 mode 0C0B Done. ``` 04RC4.txt: ``` ===== 04 RC4 TIMER FLAGS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 target 300, no reset, after 2000 cycles: mode 0C00 then 0400, counter 2054 Timer2 target 0, no reset, after 200 cycles: mode 0C00 then 0400, counter 238 Timer2 target 0, reset at target, after 200 cycles: mode 0C08 then 0C08, counter 0 Timer2 counter written FFF0, after 200 cycles: mode 1400, counter 210 Timer2 running, counter written onto target 8000: mode after 40 cycles 0C00 Timer2 running, counter written 8001 past target 8000: mode after 40 cycles 0400 Timers 1 and 2 past target: Timer1 mode 0C00, then Timer2 mode 0C00 then 0400 Timer2 sysclock target 5000 no reset, counter when bit 11 is first seen: 5025 5017 5017 5017 5017 5017 5017 5017 Timer2 sysclock target 5000 reset, counter when bit 11 is first seen: 20 15 15 15 15 15 15 15 Timer2 sysclock/8 target 100 no reset, counter when bit 11 is first seen: 103 102 102 102 102 102 102 102 Timer2 sysclock from F000, counter when bit 12 is first seen: 22 20 20 20 20 20 20 20 Done. ``` 05RC5.txt: ``` ===== 05 RC5 TIMER IRQ | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Each event: bit 10 before>at the flag, flags (1 target, 2 FFFF), I_STAT bit 6 at once and 16 cycles on Pulse, repeat, IRQ at target (mode 0258): 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>0 f1 i11; polls with bit 10 clear 1, I_STAT 400 cycles after the last 0, mode 0658 Pulse, one-shot, IRQ at target (mode 0218): 1>1 f1 i11 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0618 Toggle, repeat, IRQ at target (mode 02D8): 1>1 f1 i11 0>1 f1 i00 1>1 f1 i11 0>1 f1 i00 1>0 f1 i11 0>1 f1 i00 1>0 f1 i11 0>0 f1 i00; polls with bit 10 clear 267, I_STAT 400 cycles after the last 0, mode 06D8 Toggle, one-shot, IRQ at target (mode 0298): 1>1 f1 i11 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00; polls with bit 10 clear 469, I_STAT 400 cycles after the last 0, mode 0298 No IRQ enabled, repeat (mode 0248): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0648 IRQ at FFFF only, reset at target (mode 0268): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0668 Sysclock, IRQ at target 8000 and FFFF, repeat (mode 0070): 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0470 Sysclock, IRQ at target 8000 and FFFF, one-shot (mode 0030): 1>1 f1 i11 1>1 f2 i00 1>1 f1 i00 1>1 f2 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0430 Toggle, repeat, IRQ at target 8000 and FFFF (mode 00F0): 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00; polls with bit 10 clear 4265, I_STAT 400 cycles after the last 0, mode 04F0 Pulse, repeat, IRQ at target FFFF with reset (mode 0078): 1>1 f3 i11 1>1 f3 i11 1>1 f3 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0478 Sysclock pulse repeat, target 30 (mode 0058): of 4000 polls bit 10 read 0 236, bit 11 set 3529, I_STAT bit 6 seen 3060 Sysclock pulse repeat, target 0 (mode 0058): of 4000 polls bit 10 read 0 0, bit 11 set 4000, I_STAT bit 6 seen 0 Sysclock toggle repeat, target 0 (mode 00D8): of 4000 polls bit 10 read 0 4000, bit 11 set 4000, I_STAT bit 6 seen 0 Toggle one-shot (mode 0298): first event mode 0A98 I_STAT 1; next two 0A98 0A98 I_STAT 0; mode written again reads 0698; next event 0A98 I_STAT 1; next 0A98 I_STAT 0 Pulse one-shot (mode 0218): first event mode 0E18 I_STAT 1; next two 0E18 0E18 I_STAT 0; mode written again reads 0618; next event 0E18 I_STAT 1; next 0E18 I_STAT 0 Toggle repeat (mode 02D8): first event mode 0AD8 I_STAT 1; next two 0ED8 0ED8 I_STAT 1; mode written again reads 06D8; next event 0AD8 I_STAT 1; next 0ED8 I_STAT 0 Sysclock target 5000 reset, counter when I_STAT bit 6 is first seen: 34 22 14 18 22 14 18 22 Sysclock target 5000 reset, counter when bit 11 is first seen: 18 9 15 9 15 9 15 9 Sysclock target 5000 reset, first counter read after the reset: 6 1 4 7 10 0 3 6 Done. ``` 06RC6.txt: ``` ===== 06 RC6 TIMER PERIODS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock reset at target 999, 64 periods, cycles: 65068 67043 66023 65046 Timer1 sysclock reset at target 999, 64 periods, cycles: 64077 66065 65050 66084 Timer0 sysclock reset at target 999, 64 periods, cycles: 65059 66067 65049 65046 Timer2 sysclock reset at target FFFF, 16 periods, cycles: 1114136 1048547 Timer2 sysclock no reset (wrap at FFFF), 16 periods, cycles: 1048553 1048564 Timer2 sysclock/8 reset at target 999, 16 periods, cycles: 127846 127847 127887 127877 Timer2 sysclock/8 no reset (wrap at FFFF), 2 periods, cycles: 1048576 1048550 Timer1 hblank reset at target 99, 4 periods, cycles: 852404 852455 Timer1 hblank reset at target 0, 64 periods, cycles: 3476 3464 Timer0 dotclock 256 wide reset at target 999, 8 periods, cycles: 50432 50483 Timer0 dotclock 256 wide, dots between two hblank ticks: 339 341 339 341 339 341 339 341 Timer0 dotclock 320 wide reset at target 999, 8 periods, cycles: 40397 40448 Timer0 dotclock 320 wide, dots between two hblank ticks: 425 426 426 426 426 424 426 424 Timer0 dotclock 368 wide reset at target 999, 8 periods, cycles: 35344 35379 Timer0 dotclock 368 wide, dots between two hblank ticks: 485 487 487 487 485 487 485 487 Timer0 dotclock 512 wide reset at target 999, 8 periods, cycles: 25241 25241 Timer0 dotclock 512 wide, dots between two hblank ticks: 678 678 682 679 682 682 682 682 Timer0 dotclock 640 wide reset at target 999, 8 periods, cycles: 20224 20224 Timer0 dotclock 640 wide, dots between two hblank ticks: 853 849 853 849 853 848 853 849 Done. ``` 07RC7.txt: ``` ===== 07 RC7 TIMER FIRST TICK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, mode write to first tick: 61 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Timer2 sysclock, counter write to first tick: 59 32 32 32 32 32 32 32 32 32 37 32 32 32 32 32 Timer2 sysclock/8, mode write to first tick: 61 68 48 48 31 31 48 48 48 31 31 48 48 48 31 31 Timer2 sysclock/8, counter write to first tick: 63 32 32 69 49 49 32 49 49 32 49 49 32 49 49 32 Timer0 dotclock 640 wide, mode write to first tick: 65 68 31 48 48 31 31 48 48 31 31 48 48 31 31 48 Timer0 dotclock 640 wide, counter write to first tick: 59 32 69 32 32 32 32 32 32 32 32 32 32 35 32 49 Timer0 dotclock 256 wide, mode write to first tick: 64 68 31 48 48 48 48 48 48 31 48 48 48 48 48 48 Timer1 hblank, mode write to first tick: 1681 2094 2116 2094 2083 2072 2061 2050 2039 2019 2017 1995 1995 1973 1973 1951 Done. ``` 08RC8.txt: ``` ===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer0 sysclock free, cycles between two hblank ticks: 2140 2143 2154 2154 2154 2154 2143 2154 Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1614 1613 1613 1613 1614 1614 Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1633 1626 1630 1634 1626 1630 1623 1627 Timer0 sysclock sync 2 (count in hblank only), value at a tick: 21 14 18 11 15 19 12 15 Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 639 639 639 639 639 Timer0 dotclock sync 1, value at a tick: 644 641 643 644 641 643 644 642 Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55443 57879 57882 57886 Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20137 20111 20107 20118 Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239 Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263 Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237 Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3595 Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1958 Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240 Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5152 Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28463 Done. ``` 09RC9.txt: ``` ===== 09 RC9 TIMER UNUSED ADDR | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped at 1234, target 5678. Reads: lw 1F801100: 0000DA88 lw 1F801104: 3C021C00 lw 1F801108: 3C020000 lw 1F80110C: 3C025A5A lw 1F80111C: 3C025A5A lw 1F80112C: 3C025A5A lw 1F801130: 3C025A5A lw 1F801134: 3C025A5A lw 1F801138: 3C025A5A lw 1F80113C: 3C025A5A lhu 1F801122: 000003E0 lhu 1F801126: 00000000 lhu 1F80112A: 00000000 lhu 1F80112E: 00000000 lhu 1F801132: 00000000 lhu 1F80113E: 00000000 lbu 1F801120: 00000034 lbu 1F801121: 00000012 lbu 1F801128: 00000078 lbu 1F801129: 00000056 lbu 1F80112C: 00000000 lbu 1F801130: 00000000 lbu 1F801131: 00000000 lbu 1F80113F: 00000090 Timer2 past target: lbu 1F801125 0C, then lhu mode 0400 Timer2 past target: lbu 1F801124 00, then lhu mode 0400 Narrow stores to stopped Timer2 (counter 1234, target 5678): sb 000000AB at 1F801120: counter 00AB mode 0401 target 5678 sb 000000AB at 1F801121: counter AB00 mode 0401 target 5678 sb 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 00004321 at 1F801122: counter 0000 mode 0401 target 5678 sb 00000002 at 1F801125: counter 0003 mode 0600 target 5678 sb 00000011 at 1F801128: counter 1234 mode 0401 target 0011 sb 00000011 at 1F801129: counter 1234 mode 0401 target 1100 sh 00000011 at 1F80112A: counter 1234 mode 0401 target 0000 sb 00000011 at 1F80112C: counter 1234 mode 0401 target 5678 Done. ``` ### 28 September 2026 card-h Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/00RUN.txt) · [01RC1.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/01RC1.txt) · [02RC2.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/02RC2.txt) · [03RC3.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/03RC3.txt) · [04RC4.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/04RC4.txt) · [05RC5.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/05RC5.txt) · [06RC6.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/06RC6.txt) · [07RC7.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/07RC7.txt) · [08RC8.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/08RC8.txt) · [09RC9.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/09RC9.txt) 00RUN.txt: ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 9 tests A chain program, linked at 80100000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR 8001F594 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 40000000 Cause 00000020 EPC 80020100 PRId 00000002 ``` 01RC1.txt: ``` ===== 01 RC1 TIMER MODE READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer modes at the start: 1C00 1D00 1C00, targets 0000 0000 0000 Each mode bit written alone, then two reads: Timer0 write 0001: read 0401 then 0401 Timer0 write 0002: read 0402 then 0402 Timer0 write 0004: read 0404 then 0404 Timer0 write 0008: read 0408 then 0408 Timer0 write 0010: read 0410 then 0410 Timer0 write 0020: read 0420 then 0420 Timer0 write 0040: read 0440 then 0440 Timer0 write 0080: read 0480 then 0480 Timer0 write 0100: read 0500 then 0500 Timer0 write 0200: read 0600 then 0600 Timer0 write 0400: read 0400 then 0400 Timer0 write 0800: read 0400 then 0400 Timer0 write 1000: read 0400 then 0400 Timer0 write 2000: read 0400 then 0400 Timer0 write 4000: read 0400 then 0400 Timer0 write 8000: read 0400 then 0400 Timer0 write 0000: read 0400 then 0400 Timer1 write 0001: read 0401 then 0401 Timer1 write 0002: read 0402 then 0402 Timer1 write 0004: read 0404 then 0404 Timer1 write 0008: read 0408 then 0408 Timer1 write 0010: read 0410 then 0410 Timer1 write 0020: read 0420 then 0420 Timer1 write 0040: read 0440 then 0440 Timer1 write 0080: read 0480 then 0480 Timer1 write 0100: read 0500 then 0500 Timer1 write 0200: read 0600 then 0600 Timer1 write 0400: read 0400 then 0400 Timer1 write 0800: read 0400 then 0400 Timer1 write 1000: read 0400 then 0400 Timer1 write 2000: read 0400 then 0400 Timer1 write 4000: read 0400 then 0400 Timer1 write 8000: read 0400 then 0400 Timer1 write 0000: read 0400 then 0400 Timer2 write 0001: read 0401 then 0401 Timer2 write 0002: read 0402 then 0402 Timer2 write 0004: read 0404 then 0404 Timer2 write 0008: read 0408 then 0408 Timer2 write 0010: read 0410 then 0410 Timer2 write 0020: read 0420 then 0420 Timer2 write 0040: read 0440 then 0440 Timer2 write 0080: read 0480 then 0480 Timer2 write 0100: read 0500 then 0500 Timer2 write 0200: read 0600 then 0600 Timer2 write 0400: read 0400 then 0400 Timer2 write 0800: read 0400 then 0400 Timer2 write 1000: read 0400 then 0400 Timer2 write 2000: read 0400 then 0400 Timer2 write 4000: read 0400 then 0400 Timer2 write 8000: read 0400 then 0400 Timer2 write 0000: read 0400 then 0400 Timer0 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0C04 Timer1 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Timer2 target write FFFF reads FFFF, 0 reads 0000, 32 bit ABCD1234 reads 1234, upper half of a 32 bit read 0000 Done. ``` 02RC2.txt: ``` ===== 02 RC2 TIMER COUNTER WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped (sync mode 0): write 1234 reads 1234, after 1000 cycles 1234 Timer2 stopped: 32 bit write ABCD4321 reads 4321, write FFFF reads FFFF Timer2 stopped: counter written = target 8000, mode after 500 cycles 0C01 Timer2 stopped: counter written FFFF, mode after 500 cycles 0C01 Timer2 stopped: counter 4321 then mode write, counter 0000, mode 0401 Timer2 sysclock, two counter reads in a row, the difference: 4 4 4 4 4 4 4 4 Timer2 sysclock, counter written 1000, read at once: 1000 1000 1000 1000 1000 1000 1000 1000 Timer2 sysclock, mode written 0, counter read at once: 0 0 0 0 0 0 0 0 Timer2 sysclock, no reset at target, counter written FFFC FFFD FFFE FFFF 0000, read at once: FFFC FFFD FFFE FFFF 0000 Timer2 sysclock, reset at target 1000, counter written 0FFC 0FFD 0FFE 0FFF 1000, read at once: 0FFC 0FFD 0FFE 0FFF 1000 Timer2 reset at target 1000, counter written 1100, after 400 cycles 12AD, mode 1C08 Timer2 reset at target, target lowered to 100 under the counter, after 400 cycles 0979, mode 0408 Timer2 sysclock/8, counter written 1000, after 800 cycles 1103 Timer0 and Timer1 sysclock, counter written 1000, read at once: 1000 1000 Timer0 and Timer1 sysclock, mode written 0, counter read at once: 0 7 Done. ``` 03RC3.txt: ``` ===== 03 RC3 TIMER HISTOGRAMS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 1, reads of each value of 3000: 0:2010 1:990 2:0 3:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 2, reads of each value of 3000: 0:37 1:1 2:2962 3:0 4:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 3, reads of each value of 3000: 0:1199 1:601 2:600 3:600 4:0 5:0 higher:0 mode 0C08 Timer2 sysclock, reset at target 10, reads of each value of 3000: 0:1016 1:0 2:0 3:977 4:9 5:1 6:9 7:983 8:0 9:0 10:5 11:0 12:0 higher:0 mode 0C08 Timer2 sysclock/8, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 1, reads of each value of 3000: 0:3000 1:0 2:0 3:0 higher:0 mode 0E08 Timer2 sysclock/8, reset at target 10, reads of each value of 3000: 0:348 1:254 2:349 3:252 4:347 5:251 6:348 7:252 8:350 9:249 10:0 11:0 12:0 higher:0 mode 0E08 Timer0 sysclock, reset at target 10, reads of each value of 3000: 0:0 1:0 2:996 3:0 4:0 5:1 6:1003 7:0 8:0 9:0 10:1000 11:0 12:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 10, reads of each value of 3000: 0:990 1:0 2:0 3:991 4:0 5:1 6:19 7:991 8:0 9:0 10:8 11:0 12:0 higher:0 mode 0C08 Timer0 sysclock, reset at target 1, reads of each value of 3000: 0:1996 1:1004 2:0 3:0 higher:0 mode 0C08 Timer1 sysclock, reset at target 0, reads of each value of 3000: 0:3000 1:0 2:0 higher:0 mode 0C08 Timer0 dotclock 640 wide, reset at target 2, reads of each value of 3000: 0:1138 1:767 2:1090 3:5 4:0 higher:0 mode 0D08 Timer2 sysclock sync mode 1, reset at target 3, reads of each value of 3000: 0:1198 1:601 2:600 3:601 4:0 5:0 higher:0 mode 0C0B Done. ``` 04RC4.txt: ``` ===== 04 RC4 TIMER FLAGS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 target 300, no reset, after 2000 cycles: mode 0C00 then 0400, counter 2054 Timer2 target 0, no reset, after 200 cycles: mode 0C00 then 0400, counter 238 Timer2 target 0, reset at target, after 200 cycles: mode 0C08 then 0C08, counter 0 Timer2 counter written FFF0, after 200 cycles: mode 1400, counter 210 Timer2 running, counter written onto target 8000: mode after 40 cycles 0C00 Timer2 running, counter written 8001 past target 8000: mode after 40 cycles 0400 Timers 1 and 2 past target: Timer1 mode 0C00, then Timer2 mode 0C00 then 0400 Timer2 sysclock target 5000 no reset, counter when bit 11 is first seen: 5025 5017 5017 5017 5017 5017 5017 5017 Timer2 sysclock target 5000 reset, counter when bit 11 is first seen: 20 15 15 15 15 15 15 15 Timer2 sysclock/8 target 100 no reset, counter when bit 11 is first seen: 103 102 102 102 102 102 102 102 Timer2 sysclock from F000, counter when bit 12 is first seen: 22 20 20 20 20 20 20 20 Done. ``` 05RC5.txt: ``` ===== 05 RC5 TIMER IRQ | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Each event: bit 10 before>at the flag, flags (1 target, 2 FFFF), I_STAT bit 6 at once and 16 cycles on Pulse, repeat, IRQ at target (mode 0258): 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>1 f1 i11 1>0 f1 i11; polls with bit 10 clear 1, I_STAT 400 cycles after the last 0, mode 0658 Pulse, one-shot, IRQ at target (mode 0218): 1>1 f1 i11 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0618 Toggle, repeat, IRQ at target (mode 02D8): 1>1 f1 i11 0>1 f1 i00 1>1 f1 i11 0>1 f1 i00 1>0 f1 i11 0>1 f1 i00 1>0 f1 i11 0>0 f1 i00; polls with bit 10 clear 267, I_STAT 400 cycles after the last 0, mode 06D8 Toggle, one-shot, IRQ at target (mode 0298): 1>1 f1 i11 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00 0>0 f1 i00; polls with bit 10 clear 469, I_STAT 400 cycles after the last 0, mode 0298 No IRQ enabled, repeat (mode 0248): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0648 IRQ at FFFF only, reset at target (mode 0268): 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00 1>1 f1 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0668 Sysclock, IRQ at target 8000 and FFFF, repeat (mode 0070): 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11 1>1 f1 i11 1>1 f2 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0470 Sysclock, IRQ at target 8000 and FFFF, one-shot (mode 0030): 1>1 f1 i11 1>1 f2 i00 1>1 f1 i00 1>1 f2 i00; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0430 Toggle, repeat, IRQ at target 8000 and FFFF (mode 00F0): 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00 1>0 f1 i11 0>1 f2 i00; polls with bit 10 clear 4265, I_STAT 400 cycles after the last 0, mode 04F0 Pulse, repeat, IRQ at target FFFF with reset (mode 0078): 1>1 f3 i11 1>1 f3 i11 1>1 f3 i11; polls with bit 10 clear 0, I_STAT 400 cycles after the last 0, mode 0478 Sysclock pulse repeat, target 30 (mode 0058): of 4000 polls bit 10 read 0 236, bit 11 set 3529, I_STAT bit 6 seen 3060 Sysclock pulse repeat, target 0 (mode 0058): of 4000 polls bit 10 read 0 0, bit 11 set 4000, I_STAT bit 6 seen 0 Sysclock toggle repeat, target 0 (mode 00D8): of 4000 polls bit 10 read 0 4000, bit 11 set 4000, I_STAT bit 6 seen 0 Toggle one-shot (mode 0298): first event mode 0A98 I_STAT 1; next two 0A98 0A98 I_STAT 0; mode written again reads 0698; next event 0A98 I_STAT 1; next 0A98 I_STAT 0 Pulse one-shot (mode 0218): first event mode 0E18 I_STAT 1; next two 0E18 0E18 I_STAT 0; mode written again reads 0618; next event 0E18 I_STAT 1; next 0E18 I_STAT 0 Toggle repeat (mode 02D8): first event mode 0AD8 I_STAT 1; next two 0ED8 0ED8 I_STAT 1; mode written again reads 06D8; next event 0AD8 I_STAT 1; next 0ED8 I_STAT 0 Sysclock target 5000 reset, counter when I_STAT bit 6 is first seen: 34 22 14 18 22 14 18 22 Sysclock target 5000 reset, counter when bit 11 is first seen: 18 9 15 9 15 9 15 9 Sysclock target 5000 reset, first counter read after the reset: 6 1 4 7 10 0 3 6 Done. ``` 06RC6.txt: ``` ===== 06 RC6 TIMER PERIODS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock reset at target 999, 64 periods, cycles: 65068 67043 66023 65046 Timer1 sysclock reset at target 999, 64 periods, cycles: 64077 66065 65050 66084 Timer0 sysclock reset at target 999, 64 periods, cycles: 65059 66067 65049 65046 Timer2 sysclock reset at target FFFF, 16 periods, cycles: 1114136 1048547 Timer2 sysclock no reset (wrap at FFFF), 16 periods, cycles: 1048553 1048564 Timer2 sysclock/8 reset at target 999, 16 periods, cycles: 127846 127847 127887 127877 Timer2 sysclock/8 no reset (wrap at FFFF), 2 periods, cycles: 1048576 1048550 Timer1 hblank reset at target 99, 4 periods, cycles: 852404 852402 Timer1 hblank reset at target 0, 64 periods, cycles: 3478 3461 Timer0 dotclock 256 wide reset at target 999, 8 periods, cycles: 50432 50484 Timer0 dotclock 256 wide, dots between two hblank ticks: 341 339 341 341 339 341 339 341 Timer0 dotclock 320 wide reset at target 999, 8 periods, cycles: 40397 40448 Timer0 dotclock 320 wide, dots between two hblank ticks: 426 427 427 423 426 424 426 424 Timer0 dotclock 368 wide reset at target 999, 8 periods, cycles: 35344 35328 Timer0 dotclock 368 wide, dots between two hblank ticks: 487 488 484 487 488 487 487 487 Timer0 dotclock 512 wide reset at target 999, 8 periods, cycles: 25242 25242 Timer0 dotclock 512 wide, dots between two hblank ticks: 677 683 679 682 678 682 679 682 Timer0 dotclock 640 wide reset at target 999, 8 periods, cycles: 20224 20224 Timer0 dotclock 640 wide, dots between two hblank ticks: 850 854 849 853 853 853 853 854 Done. ``` 07RC7.txt: ``` ===== 07 RC7 TIMER FIRST TICK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 sysclock, mode write to first tick: 61 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Timer2 sysclock, counter write to first tick: 59 32 32 32 32 38 32 32 32 32 32 32 32 32 32 32 Timer2 sysclock/8, mode write to first tick: 61 68 48 48 31 48 48 48 32 48 48 48 31 31 48 48 Timer2 sysclock/8, counter write to first tick: 63 32 32 69 49 49 32 49 49 32 49 49 32 49 49 32 Timer0 dotclock 640 wide, mode write to first tick: 65 68 31 48 48 31 31 31 48 31 31 48 48 48 31 48 Timer0 dotclock 640 wide, counter write to first tick: 59 32 69 32 32 32 32 32 32 32 32 32 32 35 32 49 Timer0 dotclock 256 wide, mode write to first tick: 64 68 48 31 48 31 48 48 48 48 31 48 48 48 48 48 Timer1 hblank, mode write to first tick: 1681 2105 2105 2094 2083 2072 2061 2050 2039 2028 2006 2006 1984 1973 1973 1951 Done. ``` 08RC8.txt: ``` ===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer0 sysclock free, cycles between two hblank ticks: 2151 2154 2154 2154 2154 2143 2143 2154 Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1613 1613 1614 1614 1614 1614 Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1632 1625 1629 1632 1625 1629 1633 1625 Timer0 sysclock sync 2 (count in hblank only), value at a tick: 21 14 18 11 15 13 16 9 Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 640 639 639 639 639 Timer0 dotclock sync 1, value at a tick: 645 642 645 641 642 644 641 643 Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55443 57883 57875 57879 Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20135 20113 20094 20117 Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0 Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239 Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263 Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237 Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3543 Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1921 Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240 Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0 Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5153 Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28492 Done. ``` 09RC9.txt: ``` ===== 09 RC9 TIMER UNUSED ADDR | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Timer2 stopped at 1234, target 5678. Reads: lw 1F801100: 0000DB31 lw 1F801104: 3C021C00 lw 1F801108: 3C020000 lw 1F80110C: 3C025A5A lw 1F80111C: 3C025A5A lw 1F80112C: 3C025A5A lw 1F801130: 3C025A5A lw 1F801134: 3C025A5A lw 1F801138: 3C025A5A lw 1F80113C: 3C025A5A lhu 1F801122: 000003E0 lhu 1F801126: 00000000 lhu 1F80112A: 00000000 lhu 1F80112E: 00000000 lhu 1F801132: 00000000 lhu 1F80113E: 00000000 lbu 1F801120: 00000034 lbu 1F801121: 00000012 lbu 1F801128: 00000078 lbu 1F801129: 00000056 lbu 1F80112C: 00000000 lbu 1F801130: 00000000 lbu 1F801131: 00000000 lbu 1F80113F: 00000090 Timer2 past target: lbu 1F801125 0C, then lhu mode 0400 Timer2 past target: lbu 1F801124 00, then lhu mode 0400 Narrow stores to stopped Timer2 (counter 1234, target 5678): sb 000000AB at 1F801120: counter 00AB mode 0401 target 5678 sb 000000AB at 1F801121: counter AB00 mode 0401 target 5678 sb 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 87654321 at 1F801120: counter 4321 mode 0401 target 5678 sh 00004321 at 1F801122: counter 0000 mode 0401 target 5678 sb 00000002 at 1F801125: counter 0003 mode 0600 target 5678 sb 00000011 at 1F801128: counter 1234 mode 0401 target 0011 sb 00000011 at 1F801129: counter 1234 mode 0401 target 1100 sh 00000011 at 1F80112A: counter 1234 mode 0401 target 0000 sb 00000011 at 1F80112C: counter 1234 mode 0401 target 5678 Done. ``` ## References [^run]: SCPH-5501 output: [timers2/02RC2.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/02RC2.txt). [^h-rc1]: Run 20260928T0000Z-5501a-card-h: [timers2/01RC1.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/01RC1.txt). [^h-rc2]: Run 20260928T0000Z-5501a-card-h: [timers2/02RC2.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/02RC2.txt). [^h-rc3]: Run 20260928T0000Z-5501a-card-h: [timers2/03RC3.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/03RC3.txt). [^h-rc4]: Run 20260928T0000Z-5501a-card-h: [timers2/04RC4.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/04RC4.txt). [^h-rc5]: Run 20260928T0000Z-5501a-card-h: [timers2/05RC5.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/05RC5.txt). [^h-rc6]: Run 20260928T0000Z-5501a-card-h: [timers2/06RC6.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/06RC6.txt). [^h-rc7]: Run 20260928T0000Z-5501a-card-h: [timers2/07RC7.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/07RC7.txt). [^h-rc8]: Run 20260928T0000Z-5501a-card-h: [timers2/08RC8.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/08RC8.txt). [^h-rc9]: Run 20260928T0000Z-5501a-card-h: [timers2/09RC9.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers2/09RC9.txt).