Root Counter Behavior: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ### Reset at Target | ### Reset at Target | ||
| − | With reset at target n and counting system clock cycles, the reads fit a period of n+2 cycles in which the counter holds 0 for two cycles. At target 3, 0 was read 1199 times and 1, 2 and 3 about 600 times each out of 3000. With target 0 and reset, the counter always reads 0 and flag 11 stays set.[^h-rc3][^h-rc4] | + | With reset at target n and counting system clock cycles, the reads fit a period of n+2 cycles in which the counter holds 0 for two cycles. At target 3, 0 was read 1199 times and 1, 2 and 3 about 600 times each out of 3000. With target 0 and reset, the counter always reads 0 and flag 11 stays set.[^h-rc3][^h-rc4] On system clock / 8 the counter never reads the target value: with target 1 every read was 0, and with target 10 the reads ran from 0 to 9.[^h-rc3] |
| − | On system clock / 8 the counter never reads the target value: with target 1 every read was 0, and with target 10 the reads ran from 0 to 9.[^h-rc3] | ||
| − | |||
| ### Flags | ### Flags | ||