Root Counter Mode Combinations: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 14: | Line 14: | ||
| The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first [Root Counter Behavior](/tests/timers2/) test measured the single cases.[^run] | The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first [Root Counter Behavior](/tests/timers2/) test measured the single cases.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | |||
| ## Results | ## Results | ||