psx.wiki
Log in
Main page
Hardware
Hardware tests
System software
SDKs
File formats
Games
Tools
History
All pages
page
view source
history
View source for Root Counter Mode Combinations
← Root Counter Mode Combinations
You do not have permission to edit this page.
Log in
to edit.
--- title: Root Counter Mode Combinations type: test summary: Runs the root counters in every combination of mode bits and records interrupts, flags and bit 10. category: Hardware tests info: Machine = SCPH-5501 info: Program = timers3 --- ## Overview The program runs each [root counter](/hardware/timers/) in combinations of mode bits instead of one question at a time. Each row sets one counter in one mode and watches it for a fixed time. The row records the first read of the mode after the write, each I_STAT edge of the counter's interrupt with its time, each change of mode bit 10, how many mode reads saw bits 11 and 12, and the counter and mode at the end.[^run] The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first [Root Counter Behavior](/tests/timers2/) test measured the single cases.[^run] See also: - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) - [DMA Registers and Timer Pulse Mode](/tests/dma-registers-timer-pulse-mode/) ## Results ### Mode Bits 3 to 7 The three counters gave the same results with target 0100h over 140000 system clock cycles. No interrupt occurs unless bit 4 (IRQ at target) or bit 5 (IRQ at FFFFh) is set.[^h-t2m] Table: Root counter 2 at the system clock with target 0100h over 140000 cycles | Mode | Bits set | IRQs | Bit 11 seen | | --- | --- | --- | --- | | 0008h | reset at target | 0 | 533 times | | 0010h | IRQ at target | 1 | 3 times | | 0018h | reset, IRQ at target | 1 | 531 times | | 0020h | IRQ at FFFFh | 1, at 65542 | 3 times | | 0050h | IRQ at target, repeat | 3, about 65500 apart | 3 times | | 0058h | reset, IRQ at target, repeat | 542 | 515 times | Without bit 6 (repeat) a counter raises one IRQ and no more. With reset at target 0100h and repeat, root counter 2 raised 542 IRQs in 140000 cycles. That is one IRQ every 258 cycles. Without reset the counter reaches the target once in each 65536-cycle pass.[^h-t2m] In toggle mode (bit 7) an IRQ occurs at every other event. Root counter 0 on the dot clock with target 0040h raised 853 IRQs in pulse mode and 427 in toggle mode in the same time.[^h-t0s] ### Targets With reset at target 0 the counter stays at 0, flag 11 is set at every read, and one IRQ occurs. With target FFFFh and reset, flags 11 and 12 are set together: the mode read 1C08h after 70000 cycles.[^h-ttg][^h-trd] ### Writes While Counting Each counter ran in mode 0058h with target 8000h and was written when it reached about 4000h.[^h-twr] Table: One write to root counter 0 while it counts to target 8000h | Write | Counter read at once | Flag 11 first seen | Flag 12 first seen | | --- | --- | --- | --- | | Counter 0000h | 0019h | 32881 cycles | not seen | | Counter 7FF0h | 8000h, then 000Ch | 125 cycles | not seen | | Counter 8000h | 000Eh | 129 cycles | not seen | | Counter 8001h | 8011h | 65617 cycles | 32844 cycles | | Counter FFFFh | 000Fh | 32876 cycles | 129 cycles | | Target 2000h (below the counter) | 408Fh | 57307 cycles | 49106 cycles | | Target 4400h | 407Ch | 986 cycles | not seen | | Target FFFFh | 407Ch | 49094 cycles | 49094 cycles | A counter written onto the target is reset at once and sets flag 11. A counter written past the target counts on to FFFFh, wraps to 0 and then reaches the target. A target written below the counter is reached only after the wrap.[^h-twr] ### Reading the Flags A halfword read of the mode clears flags 11 and 12, and so do a word read of the mode and a byte read of its upper byte. Reads of the counter or the target leave the flags set. A byte read of the mode's lower byte also leaves them set.[^h-trd] ### Sync Modes Counter 1 counting system clock cycles in mode 0058h with sync mode 2 raised 206 IRQs in 600000 cycles. With the sync bits written but sync disabled it raised 2325. In sync mode 3 it raised the first IRQ 456242 cycles after the mode write and then ran freely. Sync modes written with bit 0 clear made no difference: counter 0 raised 2325 IRQs in each.[^h-tsy] ### Interrupt Rules A one-shot counter that has raised its IRQ raises another after a counter write or a mode write. A target write of the same value or a mode read does not arm it again.[^h-tiq] Table: IRQs in 20000 cycles for a one-shot counter after each action | Action | Counter 0 | Counter 1 | Counter 2 | | --- | --- | --- | --- | | Mode write | 1 | 1 | 1 | | Target written again | 0 | 0 | 0 | | Counter written 0 | 1 | 1 | 1 | | Mode read | 0 | 0 | 0 | | Second mode write | 1 | 1 | 1 | In toggle repeat mode with IRQ at FFFFh only, each counter raised 2 IRQs in 300000 cycles, about 131000 cycles apart, and bit 10 changed 4 times. In pulse repeat mode, back-to-back mode reads saw bit 10 at 0 in about 30 of 2992 reads. No two reads in a row saw it at 0.[^h-tiq] Writing bit 10 as 0 with the mode has no effect: it reads 1 at once and no IRQ follows. In toggle repeat mode, an I_STAT bit acknowledged while bit 10 is 0 does not come back until the next event: root counter 2 with target 1000h raised the first IRQ at 4173 cycles and the next at 12389.[^h-tiq] ## Runs ### 27 September 2026 card-g2 Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/00RUN.txt) · [01T0M.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/01T0M.txt) · [02T1M.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/02T1M.txt) · [03T2M.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/03T2M.txt) · [04T0S.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/04T0S.txt) · [05T1S.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/05T1S.txt) · [06T2S.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/06T2S.txt) · [07TTG.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/07TTG.txt) · [08TWR.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/08TWR.txt) · [09TRD.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/09TRD.txt) · [10TSY.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/10TSY.txt) · [11TIQ.txt](/tests/raw/20260927T0000Z-5501a-card-g2/timers3/11TIQ.txt) ### 27 September 2026 card-g3 Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/00RUN.txt) · [01T0M.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/01T0M.txt) · [02T1M.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/02T1M.txt) · [03T2M.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/03T2M.txt) · [04T0S.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/04T0S.txt) · [05T1S.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/05T1S.txt) · [06T2S.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/06T2S.txt) · [07TTG.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/07TTG.txt) · [08TWR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/08TWR.txt) · [09TRD.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/09TRD.txt) · [10TSY.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/10TSY.txt) · [11TIQ.txt](/tests/raw/20260927T0000Z-5501a-card-g3/timers3/11TIQ.txt) ### 28 September 2026 card-h Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/00RUN.txt) · [01T0M.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/01T0M.txt) · [02T1M.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/02T1M.txt) · [03T2M.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/03T2M.txt) · [04T0S.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/04T0S.txt) · [05T1S.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/05T1S.txt) · [06T2S.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/06T2S.txt) · [07TTG.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/07TTG.txt) · [08TWR.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/08TWR.txt) · [09TRD.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/09TRD.txt) · [10TSY.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/10TSY.txt) · [11TIQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/11TIQ.txt) ## References [^run]: SCPH-5501 output: [timers3/03T2M.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/03T2M.txt). [^h-t2m]: Run 20260928T0000Z-5501a-card-h: [timers3/03T2M.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/03T2M.txt). [^h-t0s]: Run 20260928T0000Z-5501a-card-h: [timers3/04T0S.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/04T0S.txt). [^h-ttg]: Run 20260928T0000Z-5501a-card-h: [timers3/07TTG.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/07TTG.txt). [^h-twr]: Run 20260928T0000Z-5501a-card-h: [timers3/08TWR.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/08TWR.txt). [^h-trd]: Run 20260928T0000Z-5501a-card-h: [timers3/09TRD.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/09TRD.txt). [^h-tsy]: Run 20260928T0000Z-5501a-card-h: [timers3/10TSY.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/10TSY.txt). [^h-tiq]: Run 20260928T0000Z-5501a-card-h: [timers3/11TIQ.txt](/tests/raw/20260928T0000Z-5501a-card-h/timers3/11TIQ.txt).