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---
title: DMA Controller
type: register
summary: Seven-channel DMA controller that moves data between main memory and the devices.
category: Hardware
---

## Summary

The DMA controller has 7 channels, each of which moves words between main memory and one device. Its registers control only the CPU side of a transfer. Most devices must also be prepared on their own side, as the GPU must be told the transfer direction before DMA2 runs.[^dsum]

Sony's hardware manual names three uses. DMA transfers data between the frame buffer and main memory, and from main memory to the sound buffer without stopping sound generation. The scratchpad, however, cannot be the target of a DMA transfer.[^hw33][^hw44][^hw29]

The channels and their devices are shown below:[^dsum]

Table: DMA channels

| Channel | Base | Device | Direction |
| --- | --- | --- | --- |
| DMA0 | 1F801080h | MDECin | RAM to MDEC |
| DMA1 | 1F801090h | MDECout | MDEC to RAM |
| DMA2 | 1F8010A0h | [GPU](/hardware/gpu/) | Command lists and image data |
| DMA3 | 1F8010B0h | [CD-ROM](/hardware/cd-rom/) | CD-ROM to RAM |
| DMA4 | 1F8010C0h | [SPU](/hardware/spu/) | Both directions |
| DMA5 | 1F8010D0h | PIO | Expansion port |
| DMA6 | 1F8010E0h | OTC | Reverse clear of an ordering table |

Each channel has three registers at its base address, and two more registers at 1F8010F0h control all channels together.[^io]

Table: DMA registers

| Address | Name | Content |
| --- | --- | --- |
| Base + 0h | Dn_MADR | Memory address register (R/W) |
| Base + 4h | Dn_BCR | Block count register (R/W) |
| Base + 8h | Dn_CHCR | Channel control register (R/W) |
| 1F8010F0h | DPCR | DMA priority control register |
| 1F8010F4h | DICR | DMA interrupt control register |
| 1F8010F8h | | Unknown |
| 1F8010FCh | | Unknown |

Each channel control register at 1F8010x8h is also mirrored at 1F8010xCh, and the mirror can be read and written.[^mir]

## Dn_MADR - Memory Address

Bits 0 to 23 hold the address in main memory where the transfer starts, and bits 24 to 31 are always zero. Bits 0 and 1 can be written, but any address the hardware updates is word aligned with those bits at zero.[^madr]

Whether the hardware updates MADR depends on the sync mode. In sync mode 0 MADR keeps the start address during and after the transfer, unless chopping is on. In sync modes 1 and 2 it follows the current block, and at the end it holds the end address in mode 1 or the end marker in mode 2.[^madr]

An address that counts down from 000000h wraps to FFFFFCh. Because FFFFFCh lies past the default 8 MB RAM region, the words after the wrap are not written.[^madr]

## Dn_BCR - Block Count

The layout of BCR depends on the sync mode. Sync mode 0 is used for OTC and CD-ROM transfers and takes a single word count:[^bcr]

Table: Dn_BCR in sync mode 0

| Bits | Name | Content |
| --- | --- | --- |
| 0 to 15 | BC | Number of words (0001h to FFFFh, 0 = 10000h) |
| 16 to 31 | | Not used (usually 0 for OTC and 1 for CD-ROM) |

Sync mode 1 is used for MDEC, SPU and GPU image data and splits the transfer into blocks. The total length is BS x BA words.[^bcr]

Table: Dn_BCR in sync mode 1

| Bits | Name | Content |
| --- | --- | --- |
| 0 to 15 | BS | Block size in words (GPU and SPU at most 10h, MDEC at most 20h) |
| 16 to 31 | BA | Number of blocks |

In sync mode 2, used for GPU command lists, BCR is not used and should be zero, since the transfer ends at the end code of the list.[^bcr]

BC, BS and BA each range from 0001h to FFFFh, and 0 means 10000h. A larger block size gives a faster transfer. However, a block must not be larger than the buffer of its device, and the GPU and SPU each have a 16-word buffer. Sync mode 1 counts BA down to zero and sync mode 0 with chopping counts BC down to zero, but in every other case BCR keeps its value.[^bcr]

## Dn_CHCR - Channel Control

CHCR sets the direction, step, sync mode and chopping of a channel and starts the transfer:[^chcr]

Table: Dn_CHCR bits

| Bits | Content |
| --- | --- |
| 0 | Transfer direction (0 = device to RAM, 1 = RAM to device) |
| 1 | MADR step (0 = +4, 1 = -4) |
| 2 to 7 | Unused |
| 8 | Burst mode: chopping on. Slice mode: hangs the DMA. List mode: transfer header before data (unconfirmed) |
| 9 to 10 | Sync mode (0 = burst, 1 = slice, 2 = list, 3 = reserved) |
| 11 to 15 | Unused |
| 16 to 18 | Chopping DMA window size (1 << N words) |
| 19 | Unused |
| 20 to 22 | Chopping CPU window size (1 << N cycles) |
| 23 | Unused |
| 24 | Start transfer (0 = stopped or completed, 1 = start or busy) |
| 25 to 27 | Unused |
| 28 | Force transfer start without waiting for DREQ |
| 29 | Forced burst mode: pause while set. Other modes: keep bit 28 set after a slice |
| 30 | Bus snooping |
| 31 | Unused |

### Sync Modes

The sync mode decides when the controller moves data. In burst mode it moves everything at once after DREQ is first asserted, and in slice mode it moves one block each time DREQ is asserted. In list mode it follows a chain of nodes in RAM.[^chcr]

The hardware clears bit 24 when the transfer completes, so every transfer must set bit 24 to start. It clears bit 28 when the transfer begins. Bit 28 should therefore be set only in sync mode 0, because in the other modes it sends the first block before the device asks for it.[^chcr]

### Channel 6 Restrictions

D6_CHCR has only three bits that can be written: bits 24, 28 and 30 in all. Bit 1 always reads 1, so the OTC channel always steps by -4, and the other bits always read 0.[^chcr]

### Usual Start Values

Software starts each channel with the CHCR values below. psx-spx has not confirmed the DMA2 VRAM write and list values for every game.[^val]

Table: Usual Dn_CHCR start values

| Channel | Value | Use |
| --- | --- | --- |
| DMA0 MDECin | 01000201h | Always |
| DMA1 MDECout | 01000200h | Always |
| DMA2 GPU | 01000200h | VRAM read |
| DMA2 GPU | 01000201h | VRAM write |
| DMA2 GPU | 01000401h | Command list |
| DMA3 CD-ROM | 11000000h | Normal |
| DMA3 CD-ROM | 11400100h | Chopped (rare) |
| DMA4 SPU | 01000201h | Write |
| DMA4 SPU | 01000200h | Read (rare) |
| DMA5 PIO | 11150100h | System 573 ATAPI read |
| DMA6 OTC | 11000002h | Always |

## DPCR - Priority Control

DPCR gives each channel a priority from 0 (highest) to 7 (lowest) and a master enable bit. Bits 28 to 30 set the priority of CPU memory access, and bit 31 has no effect.[^dpcr]

Table: DPCR bits

| Bits | Content |
| --- | --- |
| 0 to 2 | DMA0 MDECin priority |
| 3 | DMA0 MDECin master enable |
| 4 to 6 | DMA1 MDECout priority |
| 7 | DMA1 MDECout master enable |
| 8 to 10 | DMA2 GPU priority |
| 11 | DMA2 GPU master enable |
| 12 to 14 | DMA3 CD-ROM priority |
| 15 | DMA3 CD-ROM master enable |
| 16 to 18 | DMA4 SPU priority |
| 19 | DMA4 SPU master enable |
| 20 to 22 | DMA5 PIO priority |
| 23 | DMA5 PIO master enable |
| 24 to 26 | DMA6 OTC priority |
| 27 | DMA6 OTC master enable |
| 28 to 30 | CPU memory access priority |
| 31 | No effect (R/W) |

DPCR holds 07654321h after reset. When two channels have the same priority the channel number decides, and DMA6 then has the highest priority and DMA0 the lowest.[^dpcr]

## DICR - Interrupt Control

DICR enables the completion interrupt of each channel and holds its flag:[^dicr]

Table: DICR bits

| Bits | Content |
| --- | --- |
| 0 to 6 | Channel 0 to 6 interrupt timing (0 = when the whole transfer completes, 1 = after every slice or list node) |
| 7 to 14 | Unused |
| 15 | Bus error flag, set on a transfer outside RAM. Forces bit 31 (R/W) |
| 16 to 22 | Channel 0 to 6 interrupt mask |
| 23 | Master channel interrupt enable |
| 24 to 30 | Channel 0 to 6 interrupt flags (R, write 1 to clear) |
| 31 | Master interrupt flag (R) |

A completed transfer on channel n sets flag bit 24+n only when bit 16+n and bit 23 are both set. These flags therefore differ from the flags in I_STAT, which are set even when the interrupt is masked.[^dicr]

Bit 31 is read only and is recalculated on every write to DICR. The channel mask bits do not enter the formula, so a flag that is already set keeps bit 31 set until software clears it.[^dicr]

```
IF b15=1 OR (b23=1 AND b(24-30)>0) THEN b31=1 ELSE b31=0
```

When bit 31 changes from 0 to 1 the IRQ3 bit in [I_STAT](/hardware/interrupts/) is set. To acknowledge a channel, write 1 to its flag bit in DICR and then acknowledge IRQ3 in I_STAT.[^dicr]

### Completion Callbacks

Libraries that use DMA, such as libgpu and libsnd, have a function for registering a callback with the kernel. The kernel calls the callback automatically when the DMA transfer completes. Completion processing can therefore be done by setting a flag in an external variable and issuing an event.[^ovr26]

## List Mode

GPU commands normally go from RAM to GP0 by DMA2 in sync mode 2. In this mode the controller transfers words in nodes, and D2_MADR gives the address of the first node. Each node is a header word followed by the words to transfer:[^ll]

Table: List node header

| Bits | Name | Content |
| --- | --- | --- |
| 0 to 23 | NPTR | Address of the next node, or the end marker |
| 24 to 31 | DC | Number of words that follow the header |

The transfer stops at the end marker FFFFFFh. An address above 8 MB also stops it, with a DMA error in DICR, and some games end their lists this way. Such a list fails when the memory is configured for 16 MB.[^ll]

## Transfer Rates

The DMA transfer rates per channel are as follows. MDEC decompression time, GPU drawing time and the CD-ROM sector rate add to these figures.[^rate]

Table: DMA transfer rates

| Channel | Clocks per word | Clocks per 100h words |
| --- | --- | --- |
| DMA0 MDECin | 1 | 0110h |
| DMA1 MDECout | 1 | 0110h |
| DMA2 GPU | 1 | 0110h |
| DMA3 CD-ROM (BIOS timing) | 24 | 1800h |
| DMA3 CD-ROM (game timing) | 40 | 2800h |
| DMA4 SPU | 4 | 0420h |
| DMA5 PIO | 20 | 1400h |
| DMA6 OTC | 1 | 0110h |

The BIOS sets 24 clocks per word for the CD-ROM, but most games change it to 40. The CD-ROM, SPU and PIO timings are set in the [memory control](/hardware/memory-control/) registers.[^rate]

DMA reaches 1 clock per word because it uses DRAM hyper page mode. A 16-word block takes about 17 clocks because the row address must be loaded first. A CPU access to DRAM, by comparison, takes 1 opcode cycle plus 6 wait states, or 7 cycles in all.[^rate]

## CPU Operation During DMA

The CPU keeps running during a DMA transfer as long as it uses only the I-cache, the scratchpad, COP0 and the GTE. It can also place up to 4 writes in the write queue for RAM and I/O registers. A read from RAM or an I/O register stalls the CPU until the DMA finishes, and so does a fifth queued write.[^cpu]

The CPU also runs while a transfer pauses: between the blocks of sync mode 1, between the nodes of sync mode 2, and in sync mode 0 with chopping on.[^cpu]

## References

[^hw29]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 2-9.
[^hw33]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 3-3.
[^hw44]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 4-4.
[^ovr26]: Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-6.
[^io]: psx-spx. I/O Map, DMA Registers. https://psx-spx.consoledev.net/iomap/
[^mir]: psx-spx. Unpredictable Things, Mirrors in I/O Area. https://psx-spx.consoledev.net/unpredictablethings/
[^dsum]: psx-spx. DMA Channels, DMA Register Summary. https://psx-spx.consoledev.net/dmachannels/
[^madr]: psx-spx. DMA Channels, D#_MADR - DMA base address. https://psx-spx.consoledev.net/dmachannels/
[^bcr]: psx-spx. DMA Channels, D#_BCR - DMA Block Control. https://psx-spx.consoledev.net/dmachannels/
[^chcr]: psx-spx. DMA Channels, D#_CHCR - DMA Channel Control. https://psx-spx.consoledev.net/dmachannels/
[^dpcr]: psx-spx. DMA Channels, DPCR - DMA Control Register. https://psx-spx.consoledev.net/dmachannels/
[^dicr]: psx-spx. DMA Channels, DICR - DMA Interrupt Register. https://psx-spx.consoledev.net/dmachannels/
[^val]: psx-spx. DMA Channels, Commonly used DMA Control Register values. https://psx-spx.consoledev.net/dmachannels/
[^ll]: psx-spx. DMA Channels, Linked List DMA. https://psx-spx.consoledev.net/dmachannels/
[^rate]: psx-spx. DMA Channels, DMA Transfer Rates and DRAM Hyper Page mode. https://psx-spx.consoledev.net/dmachannels/
[^cpu]: psx-spx. DMA Channels, CPU Operation during DMA. https://psx-spx.consoledev.net/dmachannels/