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---
title: Memory Map
type: component
summary: Logical and physical address spaces of the PlayStation CPU.
category: Hardware
---

## Overview

The space handled by a program is called logical space. It is expressed by a 32-bit address and is mapped onto physical space several times over, and in C it is accessed with a long pointer. Physical space is the address in the installed memory device. Accessing a logical address that is not mapped in physical space generates a Bus Error exception.[^hw24]

The R3000 TLB is not mounted in the PlayStation. The relationship between physical and logical addresses is therefore always fixed, and the PlayStation has no virtual memory.[^hw23]

## Physical Memory

Physical memory has a 64MB system area. Main memory occupies the bottom of this area and ends at 0x1FFFFF on the PlayStation and at 0x7FFFFF on the developer system, which has 8 MB.[^hw23]

psx-spx gives the full layout below. Each region appears at the same offset in the three segment groups KUSEG, KSEG0 and KSEG1, apart from the scratchpad, which has no KSEG1 address.[^mm]

Table: Physical memory regions

| KUSEG | KSEG0 | KSEG1 | Size | Content |
| --- | --- | --- | --- | --- |
| 00000000h | 80000000h | A0000000h | 2048K | Main RAM (first 64K reserved for the BIOS) |
| 1F000000h | 9F000000h | BF000000h | 8192K | DEV0 expansion (ROM or RAM) |
| 1F800000h | 9F800000h | | 1K | Scratchpad (D-cache used as fast RAM) |
| 1F801000h | 9F801000h | BF801000h | 4K | I/O ports |
| 1F802000h | 9F802000h | BF802000h | 8K | DEV8 expansion (I/O ports) |
| 1FA00000h | 9FA00000h | BFA00000h | 2048K | DEV1 expansion (SRAM BIOS region for DTL boards) |
| 1FC00000h | 9FC00000h | BFC00000h | 512K | BIOS ROM (kernel), 4096K at most |
| FFFE0000h | | | 0.5K | CPU control registers (cache control), in KSEG2 |

The [I/O map](/hardware/io-map/) lists the I/O ports, and the [memory control](/hardware/memory-control/) registers set the size and timing of each region.

### Memory Outside the CPU Bus

Several memories of the PlayStation are not mapped in the CPU address space. They are reached only through their devices:[^mm]

Table: Memory not mapped to the CPU bus

| Size | Memory |
| --- | --- |
| 1024K | VRAM (frame buffers, textures and palettes), with a 2 KB texture cache |
| 512K | Sound RAM (capture buffers, ADPCM data and reverb work area) |
| 0.5K | CD-ROM controller RAM |
| 16.5K | CD-ROM controller ROM (firmware and bootstrap of the MC68HC05 CPU) |
| 32K | CD-ROM buffer (IC303, 32K x 8) |
| 128K | Memory Cards (EEPROM) |

Sony's manuals describe two of these. The GPU has 1 MB of video memory, and the sound buffer of the SPU is 512KB and is not mapped in the CPU address space.[^hw33][^hw44]

psx-spx reports that only two sectors of the 32K CD-ROM buffer appear to be accessible.[^mm]

## Segments

Sony's hardware manual divides logical space into the following segments. The Cache column refers to the I-cache.[^hw24]

Table: Memory maps

| Logic Space | Segment title | Cache |
| --- | --- | --- |
| 0x00000000 to physical space MAX | A | Effective |
| 0x1F800000 to 0x1F8003FF | S | Not effective |
| 0x1F801000 to 0x1FBFFFFF | X | Not effective |
| 0x1FC00000 to 0x1FC7FFFF | P | Effective |
| 0x80000000 to 0x80000000 + physical space MAX | B | Effective |
| 0x9FC00000 to 0x9FC7FFFF | Q | Effective |
| 0xA0000000 to 0xA0000000 + physical space MAX | C | Not effective |
| 0xBFC00000 to 0xBFC7FFFF | R | Not effective |

The segments correspond to the memory devices as shown below. A segment is a block unit of the R3000 memory space divided by function, and it differs from the segment of an 8086 series CPU.[^hw24]

Table: Segments and devices

| Logic Space | Corresponding Logic Memory Segment | Device |
| --- | --- | --- |
| 0x00000000 to MAX | A+B+C | Main Memory (RAM) |
| 0x1F800000 to 0x1F8003FF | S | Scratchpad (D-cache) |
| 0x1F801000 to 0x1FBFFFFF | X | Hardware Register |
| 0x1FC00000 to 0x1FC7FFFF | P+Q+R | Boot ROM |

Interface registers of the peripheral devices are mapped in logical space as memory mapped I/O. Memory may be accessed in units of 1 to 4 bytes, but an interface register is accessed in its own unit size, and an access of any other size generates a bus error.[^os25]

## MIPS Regions

psx-spx describes the same space with the standard MIPS region names. KSEG1 is physical memory without the cache, and KSEG0 is a mirror of it with the cache. KUSEG would hold 2 GB of virtual user memory on MIPS CPUs with a TLB, but on the PlayStation its first 512 MB mirror KSEG0, and an access to the remaining 1.5 GB causes an exception.[^ks]

Table: Region properties

| Address | Name | I-cache | Write queue |
| --- | --- | --- | --- |
| 00000000h | KUSEG | Yes | Yes |
| 80000000h | KSEG0 | Yes | Yes |
| A0000000h | KSEG1 | No | No |
| C0000000h | KSEG2 | No code | No |

KSEG2 normally holds virtual kernel memory. On the PlayStation it holds only the cache control registers at FFFE0000h.[^ks]

Sony's segments A, B and C are the main RAM in KUSEG, KSEG0 and KSEG1, and P, Q and R are the BIOS ROM in the same three regions. The Cache columns of the two tables therefore agree.[^hw24][^ks]

## Memory Mirrors

Apart from the KUSEG, KSEG0 and KSEG1 mirrors, the regions mirror within themselves as follows:[^mir]

Table: Mirrors within a region

| Mirror | Default |
| --- | --- |
| 2 MB RAM mirrored in the first 8 MB | Enabled |
| 512K BIOS ROM mirrored in the last 4 MB | Disabled |
| Expansion hardware mirrored within its region | Depends on the hardware |
| DMA channel control registers at 1F8010x8h mirrored at 1F8010xCh | Always |

The RAM mirror is enabled because the BIOS configures the DRAM controller for an 8 MB bank on a 2 MB console. The sizes of the RAM, BIOS and expansion regions can be changed by software, and so can the base address of the DEV0 region.[^mir][^dram]

## Memory Exceptions

Two kinds of exception come from memory accesses. A misaligned access causes an address error, and probably a KSEG access in user mode does too. An access to an unused region, including a gap in the I/O region, causes a bus error unless a RAM, BIOS or expansion mirror is mapped there.[^exc]

The R3000 requires strict address alignment. Word data must start at a multiple of 4 and halfword data at a multiple of 2, and a data load, data store or instruction fetch that breaks the rule causes an address error.[^hw25]

## Kernel Area

The kernel uses the first 64K bytes of main memory, and the user may use addresses from 0x00010000. The kernel's system tables start at 0x00000100 with the ToT (Table of Tables), and exceptions and interrupts enter the kernel at 0x00000080.[^ovr27][^os26][^hw27]

## References

[^hw23]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 2-3, Figure 2-1.
[^hw24]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 2-4, Figure 2-2, Table 2-2.
[^hw25]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 2-5.
[^hw27]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 2-7, Figure 2-3.
[^hw33]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 3-3.
[^hw44]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 4-4.
[^os25]: Sony Computer Entertainment Inc. PlayStation Operating System. August 1998. Page 2-5.
[^os26]: Sony Computer Entertainment Inc. PlayStation Operating System. August 1998. Page 2-6.
[^ovr27]: Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-7.
[^mm]: psx-spx. Memory Map. https://psx-spx.consoledev.net/memorymap/
[^ks]: psx-spx. Memory Map, KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions. https://psx-spx.consoledev.net/memorymap/
[^mir]: psx-spx. Memory Map, Memory Mirrors. https://psx-spx.consoledev.net/memorymap/
[^exc]: psx-spx. Memory Map, Memory Exceptions. https://psx-spx.consoledev.net/memorymap/
[^dram]: psx-spx. Memory Control, 1F801060h - DRAM_CTRL. https://psx-spx.consoledev.net/memorycontrol/