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---
title: DMA Master Enable
type: test
summary: Checks that an SPU DMA transfer runs only when its enable bit in DPCR is set.
category: Hardware tests
info: Machine = SCPH-5501
info: Program = dma/dpcr (ps1-tests)
---

## Overview

The program writes a test string to sound RAM, then reads it back by [DMA](/hardware/dma/) channel 4 three times. Before each read it changes channel 4's field in DPCR (bits 16 to 19): enable set with priority 5, enable clear with priority 5, and enable clear with priority 0. Each read waits a fixed time and reports whether the transfer completed.[^src]

## Results

With the enable bit set (DPCR 333D3B33h) the read completed and the data matched. With the enable bit clear the transfer never ran, at priority 5 (33353B33h) and at priority 0 (33303B33h); both reads timed out.[^run] DPCR read 333B3B33h before each change in all four runs.[^run]

## Runs

### 25 September 2026

[05DPC.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

### 27 September 2026

[05DPC.txt](/tests/raw/20260927T0000Z-5501a-card-2/main/s024/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

### 27 September 2026 run 2

[05DPC.txt](/tests/raw/20260927T0000Z-5501a-card-b/main/s034/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

### 27 September 2026 run 3

[05DPC.txt](/tests/raw/20260927T0000Z-5501a-card-g/main/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

### 27 September 2026 run 4

[05DPC.txt](/tests/raw/20260927T0000Z-5501a-card-g3/main/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

### 28 September 2026

[05DPC.txt](/tests/raw/20260928T0000Z-5501a-card-h/main/05DPC.txt)

```
===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.
```

## References

[^src]: ps1-tests, dma/dpcr. https://github.com/JaCzekanski/ps1-tests.
[^run]: SCPH-5501 output: [main/05DPC.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/05DPC.txt) and the files beside it, with the other runs listed under Runs.