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---
title: GPU Draw Queue and IRQ1
type: test
summary: Measures the IRQ1 that GP0(1Fh) raises at the end of a DMA list and the recovery of a stalled GPU.
category: Hardware tests
info: Machine = SCPH-5501
info: Program = SXGSYNC
---

## Overview

The program queues ordering tables to the [GPU](/hardware/gpu/) through [DMA](/hardware/dma/) channel 2 in list mode. After the last queued list, the DMA interrupt sends a one-word list holding GP0(1Fh), and the IRQ1 that GP0(1Fh) raises calls a done function. Every drawing group reads its result back from VRAM and compares a checksum with a model of the expected pixels.[^run]

The groups queue four lists at once (Q1), time the done call against a list of large semi-transparent rectangles (Q2), and queue a second list from inside the done function (Q3). Two groups make the GPU stall on purpose: GP0(A0h) with no data (H1) and a list whose tag links to itself (H2). Further groups build and draw packets by CPU (P1, P2) and change the drawing area, offset, mask and texture window from inside a list (S1).[^run]

## Results

GP0(1Fh) sent by DMA channel 2 at the end of the lists raised IRQ1, and every group read back the pixels it expected. With four lists queued, the done function ran once. When the done function queued a second list, both lists were drawn and the function ran twice.[^run]

GPUSTAT read D6802400h inside the done function. Bit 26 (ready for a command) and bit 28 (FIFO empty) were set. In Q2 the done function ran 12,800 counts of root counter 2 at system clock / 8 after the start, and the wait for the queue returned at 12,849.[^run]

GP0(A0h) with no data following it stalled the GPU until the program gave up after its time limit of 30 vertical blanks. GPUSTAT was polled 29,660 times in one vertical blank. After a GP1(01h) reset, a 32 x 32 load read back correctly.[^run]

A list whose tag links to itself kept DMA channel 2 running: CHCR read 01000401h with bit 24 set. Writing CHCR with bit 24 clear stopped it, and CHCR read 00000401h then and one frame later.[^run]

## Runs

### 15 October 2026

[sxgsync/SXGSYNC.txt](/tests/raw/20261015T0552Z-5501a-link/sxgsync/SXGSYNC.txt)

```
SXDEV I_MASK at init AE420100
SXGSYNC start
SXGSYNC Q1 draw 0 pending 4 sync 0 done calls 1 stat in done D6802400
SXGSYNC Q1 tiles crc read 7DDBEE72 model 7DDBEE72 differ 0
SXGSYNC Q2 clock/8 queued50 sync 12849 stat D6802400 done 12800 stat 56802400 calls 1
SXGSYNC Q3 done calls 2
SXGSYNC Q3 tiles crc read A49C9B20 model A49C9B20 differ 0
SXGSYNC H1 sync 1 vblanks 30 count 1 calls 1 stat 70802400 chcr 00000200 GPUSTAT reads a vblank 29660
SXGSYNC H1 load after crc read F2B454B5 model F2B454B5 differ 0
SXGSYNC H2 draw 0 sync 1 vblanks 30 count 2 stat 40802400 chcr 01000401 madr 00024B00 loop at 00024B00 chcr after 00000401 a frame later 00000401
SXGSYNC H2 list after crc read 56BF04DE model 56BF04DE differ 0
SXGSYNC H3 interrupts off sync 1 hblanks 5197 count 3
SXGSYNC H3 load after crc read 1CDD2E80 model 1CDD2E80 differ 0
SXGSYNC P1 tools differ 0
SXGSYNC P1 chain, sub table, forward table crc read 592AB100 model 592AB100 differ 0
SXGSYNC P2 tile 0 env 0 clipped 0 env words 9
SXGSYNC P2 packets by CPU crc read ED48CB28 model ED48CB28 differ 0
SXGSYNC S1 slots 22 draw 0 sync 0
SXGSYNC S1 area, offset, mask crc read 311E9A2D model 311E9A2D differ 0
SXGSYNC S1 window, env crc read 1CB44C81 model 1CB44C81 differ 0
SXGSYNC S1 large tile then area (measure) crc read 0AA65103 model 0AA65103 differ 0
SXGSYNC q1 0 q2 0 q3 0 h1 0 h2 0 h3 0 p1 0 p2 0 s1 0 e3 measure 0 PASS
```

## References

[^run]: Hardware test run 20261015T0552Z-5501a-link on the SCPH-5501: [SXGSYNC.txt](/tests/raw/20261015T0552Z-5501a-link/sxgsync/SXGSYNC.txt).