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---
title: GPUSTAT Bit 13 Across Interlace Changes
type: test
summary: Measures what GPUSTAT bit 13 reads when GP1(08h) switches into and out of 480-line interlace.
category: Hardware tests
info: Machine = SCPH-5501 (NTSC)
info: Program = SXFLD2
---

## Overview

[GPUSTAT](/hardware/gpu/gpustat/) bit 13 reports the interlace field. The program switches the display between 480-line interlace and 240 lines with GP1(08h) and reads GPUSTAT straight after the write and at each of the following vertical blanks.[^run]

It switches out of 480-line interlace eight times, at a different number of horizontal blanks into the frame each time, and reads 16 vertical blanks after. It switches back into 480-line interlace eight times and reads four vertical blanks after.[^run]

See also:

- [GPU Drawing Time and Status Bits](/tests/gpu-drawing-time/)

## Results

Switching out of 480-line interlace keeps the value bit 13 had. When bit 13 was 1 before the switch, GPUSTAT read 14062000h at once and at all 16 following vertical blanks, wherever in the frame the switch came. When bit 13 was 0, GPUSTAT read 14060000h and stayed at 0 across the next vertical blank.[^run]

Switching into 480-line interlace reads the held value at once, and bit 13 then changes at every vertical blank. From 14060000h the next four vertical blanks read 144E2000h, 144E0000h, 144E2000h and 144E0000h. From 14062000h they read the same pattern starting with 144E0000h.[^run]

## Runs

### 15 October 2026

[sxfld2/SXFLD2.txt](/tests/raw/20261015T1512Z-5501a-link/sxfld2/SXFLD2.txt)

```
SXDEV I_MASK at init 3C040100
SXFLD2 start
SXFLD2 480>240 hold r0 pre 144E2000 h 0 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r1 pre 144E2000 h 33 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r2 pre 144E2000 h 66 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r3 pre 144E2000 h 99 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r4 pre 144E2000 h 132 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r5 pre 144E2000 h 165 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r6 pre 144E2000 h 198 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 hold r7 pre 144E2000 h 231 now 14062000 vbl 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000 14062000
SXFLD2 480>240 at 14060000 vbl 14060000
SXFLD2 240>480 back r0 pre 14060000 h 0 now 144E0000 vbl 144E2000 144E0000 144E2000 144E0000
SXFLD2 480>240 at 14062000 vbl 14062000
SXFLD2 240>480 back r1 pre 14062000 h 0 now 144E2000 vbl 144E0000 144E2000 144E0000 144E2000
SXFLD2 480>240 at 94060000 vbl 14060000
SXFLD2 240>480 back r2 pre 14060000 h 0 now 144E0000 vbl 144E2000 144E0000 144E2000 144E0000
SXFLD2 480>240 at 14062000 vbl 14062000
SXFLD2 240>480 back r3 pre 14062000 h 0 now 144E2000 vbl 144E0000 144E2000 144E0000 144E2000
SXFLD2 480>240 at 94060000 vbl 14060000
SXFLD2 240>480 back r4 pre 14060000 h 0 now 144E0000 vbl 144E2000 144E0000 144E2000 144E0000
SXFLD2 480>240 at 14062000 vbl 14062000
SXFLD2 240>480 back r5 pre 14062000 h 0 now 144E2000 vbl 144E0000 144E2000 144E0000 144E2000
SXFLD2 480>240 at 94060000 vbl 14060000
SXFLD2 240>480 back r6 pre 14060000 h 0 now 144E0000 vbl 144E2000 144E0000 144E2000 144E0000
SXFLD2 480>240 at 14062000 vbl 14062000
SXFLD2 240>480 back r7 pre 14062000 h 0 now 144E2000 vbl 144E0000 144E2000 144E0000 144E2000
SXFLD2 end PASS
```

## References

[^run]: Hardware test run 20261015T1512Z-5501a-link on the SCPH-5501: [SXFLD2.txt](/tests/raw/20261015T1512Z-5501a-link/sxfld2/SXFLD2.txt).