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--- title: MDEC Block Timing type: test summary: Measures when the MDEC status register changes during a decode, by output depth, by what came before the decode and by how the output is read, and what the MDEC outputs after an AC run past entry 63. category: Hardware tests info: Machine = SCPH-5501 info: Program = followup23 --- ## Overview The program writes a decode command and its input words to the [MDEC](/hardware/mdec/) at 1F801820h, then polls the status register at 1F801824h for a fixed span. The program records every change of the status word with its time on root counter 2 after the last input word and the number of output words read by then. The raw output gives each change as status@cycles/words read. The quantization and scale tables are loaded first with MDEC(2) and MDEC(3) unless a group says otherwise.[^fbx] Table: Groups | Tag | Decode | | --- | --- | | FBX | The first 32 words of the step stream from the [MDEC Output](/tests/mdecout/) test with a count of 256 at 15 bit, no reads, after five different starts | | TRW | Two macroblocks of one-word blocks with a count of 12, each word read as soon as the output FIFO holds one, at 15 and 24 bit | | ORQ | The FBX stream at 24 and 15 bit, one word read each time status bit 27 is set | | MNT | A 32-word block stream at 8 and 4 bit with its own tables, no reads | | RUN | One block with a quantization factor of 1, DC 16 and an AC run of 63, then five different tails, at 8 bit unsigned with a count of 32 and every word read | See also: - [MDEC Output](/tests/mdecout/) - [MDEC Hand-Made Streams](/tests/mdec2/) - [MDEC Start and Interrupt Entry Timing](/tests/mdec-start-interrupt-entry/) - [MDEC Reset and Store Timing](/tests/sxmdrst/) - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) ## Results ### First Block The current block field of the status moved from Cr to Cb about 805 cycles after word 32. It moved to Y1 about 1,322 cycles after it and to Y2 about 1,832. The output FIFO first held data at about 1,473 cycles. At about 1,529 cycles bit 30 cleared and the data-in request in bit 28 set. The data-out request in bit 27 set at about 1,888 cycles.[^fbx] Table: Cycles after word 32 at which each status change came (run 1) | Start | Cb | Y1 | Output ready | Y2 | Bit 27 set | | --- | --- | --- | --- | --- | --- | | After the tables | 805 | 1,322 | 1,473 | 1,832 | 1,888 | | After a whole decode with no tables between | 805 | 1,322 | 1,473 | 1,832 | 1,888 | | 20,000 cycles after the tables | 805 | 1,322 | 1,473 | 1,837 | 1,893 | | After a reset and 2,000 cycles with no tables | 805 | 1,322 | 1,473 | 1,832 | 1,888 | | After the scale table alone with no reset | 808 | 1,328 | 1,462 | 1,840 | 1,898 | Every start gave the same times within 16 cycles in both runs. The first block of a decode therefore takes the same time whether a decode, a table load, a reset or a long wait came before it, and whether or not tables were loaded since the last reset.[^fbx] ### Output Read at Once With every word read as soon as the output FIFO held one, the block field moved to Cb 812 to 815 cycles after word 12 and to Y1 1,319 to 1,335 cycles after it at both depths. The first word was ready 1,438 to 1,482 cycles after word 12. In the 8,000 cycles that were recorded the program read 212 words at 15 bit and 242 at 24 bit.[^trw] At 24 bit the field stepped at 2,781, 4,017 and 5,253 cycles in the first run, which is 1,236 cycles apart, and 48 words were read in each step. The second run gave the same steps 5 cycles earlier. At 15 bit the steps of the first macroblock from Y1 to Y4 came 494 to 636 cycles apart and were not the same in the two runs. In the second macroblock the steps from Y1 to Y4 came 511 to 533 cycles apart in both runs.[^trw] ### Data-Out Request With one word read each time bit 27 was set, the request set 1,687 cycles after word 32 at 24 bit and 1,902 cycles after it at 15 bit. It cleared after 23 words had been read at 24 bit and after 7 at 15 bit. The request did not set again in the 8,000 cycles that were recorded, so no further words were read.[^orq] ### Mono Depths In the first 8-bit run the status after the last word was E204FFFFh. Bit 30 cleared 235 cycles after word 32, bit 31 cleared at 581 when the first output was ready, and bit 27 set at 831. The second 8-bit run and both 4-bit runs read E0041CFCh after the last word. That word count field, 1CFCh, does not match a command for 32 words, and those runs are left to the raw output.[^mnt] ### AC Run Past Entry 63 Every case gave 32 words of output, which is two blocks of 16 words at 8 bit, except a second run of 63, which gave 48 words. The CRC-32 of the first 16 words was C2FE5235h in every case.[^run] Table: Output after an AC run of 63 by the halfwords that follow it | Tail | Words out | CRC-32 of each 16 words | | --- | --- | --- | | End code | 32 | C2FE5235h 9ECF7B89h | | AC 1, end code | 32 | C2FE5235h E240D580h | | AC 1, AC 1, end code | 32 | C2FE5235h 85A15D5Dh | | 7C01h, end code | 32 | C2FE5235h FFDF0A60h | | A second run of 63, end code | 48 | C2FE5235h 9ECF7B89h 9ECF7B89h | The second block changed with the halfwords after the run. The end code alone and a second run of 63 gave the same second block, 9ECF7B89h, and the second run of 63 gave that block twice.[^run] ## Runs ### 5 October 2026 [followup23/00RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/00RUN.txt) ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 5 tests A chain program, linked at 80100000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR 8001A454 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 00000000 Cause 00000020 EPC 8001B008 PRId 00000002 ``` [followup23/01FBX.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/01FBX.txt) ``` ===== 01 FBX F23 MDEC FIRST BLOCK | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Row 82: MST (followup19.c ms_run) after five different starts; 15 bit, the step stream, count 256, words 1-32 with no reads, then the status for 6000 cycles after word 32. Each change: status@cycles after word 32/words read. After the tables (as 02MST), 15 bit run 1: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After the tables (as 02MST), 15 bit run 2: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After a whole decode, no tables between, 15 bit run 1: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After a whole decode, no tables between, 15 bit run 2: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 20000 cycles after the tables, 15 bit run 1: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1837/0 3E0100DF@1893/0 20000 cycles after the tables, 15 bit run 2: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After a reset and 2000 cycles, no tables, 15 bit run 1: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After a reset and 2000 cycles, no tables, 15 bit run 2: E60400DF after the last word; 6 changes: E60500DF@805/0 E60000DF@1322/0 660000DF@1473/0 360000DF@1529/0 360100DF@1832/0 3E0100DF@1888/0 After the scale table alone, no reset, 15 bit run 1: E60400DF after the last word; 6 changes: E60500DF@808/0 E60000DF@1328/0 660000DF@1462/0 360000DF@1518/0 360100DF@1840/0 3E0100DF@1898/0 After the scale table alone, no reset, 15 bit run 2: E60400DF after the last word; 6 changes: E60500DF@810/0 E60000DF@1327/0 660000DF@1478/0 360000DF@1534/0 360100DF@1840/0 3E0100DF@1896/0 Done. ``` [followup23/02TRW.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/02TRW.txt) ``` ===== 02 TRW F23 MDEC 15 BIT TRAIL | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Row 83: two macroblocks of one-word blocks, count 12, every word read as soon as bit 31 is clear, the status for 8000 cycles after word 12, at 15 and 24 bit. Each change: status@cycles after word 12/words read. Read at once, 15 bit run 1: E604FFFF after the last word; 19 changes: E605FFFF@815/0 E600FFFF@1319/0 6600FFFF@1466/1 6601FFFF@1832/14 6E01FFFF@2243/29 6602FFFF@2354/32 6E02FFFF@2415/33 6E03FFFF@2926/52 6E04FFFF@3762/84 6604FFFF@4298/104 6605FFFF@4384/106 6600FFFF@4892/125 6601FFFF@5407/144 6E01FFFF@5816/159 6601FFFF@5877/160 6E02FFFF@5938/161 6E03FFFF@6449/180 2E03FFFF@6560/183 2E04FFFF@7321/212 Read at once, 15 bit run 2: E604FFFF after the last word; 20 changes: E605FFFF@812/0 E600FFFF@1335/0 6600FFFF@1482/1 6601FFFF@1848/14 6E01FFFF@2109/23 6601FFFF@2170/24 6E01FFFF@2231/25 6E02FFFF@2342/28 6E03FFFF@2978/52 6E04FFFF@3819/84 6604FFFF@4355/104 6605FFFF@4441/106 6600FFFF@4952/125 6601FFFF@5463/144 6E01FFFF@5874/159 6601FFFF@5935/160 6E02FFFF@5996/161 6E03FFFF@6507/180 2E03FFFF@6618/183 2E04FFFF@7379/212 Read at once, 24 bit run 1: E404FFFF after the last word; 14 changes: E405FFFF@812/0 E400FFFF@1335/0 6400FFFF@1438/1 6C00FFFF@1784/13 6C01FFFF@1845/14 6C02FFFF@2781/50 6C03FFFF@4017/98 6C04FFFF@5253/146 6404FFFF@5839/168 6405FFFF@5925/170 6400FFFF@6436/189 6C00FFFF@6897/206 6C01FFFF@6958/207 6C02FFFF@7869/242 Read at once, 24 bit run 2: E404FFFF after the last word; 14 changes: E405FFFF@812/0 E400FFFF@1335/0 6400FFFF@1438/1 6C00FFFF@1779/13 6C01FFFF@1840/14 6C02FFFF@2776/50 6C03FFFF@4012/98 6C04FFFF@5248/146 6404FFFF@5834/168 6405FFFF@5920/170 6400FFFF@6431/189 6C00FFFF@6892/206 6C01FFFF@6953/207 6C02FFFF@7864/242 Done. ``` [followup23/03ORQ.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/03ORQ.txt) ``` ===== 03 ORQ F23 MDEC OUT REQUEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Row 84: MST's stream (count 256, words 1-32), then one word read each time bit 27 is set, the status for 8000 cycles after word 32, at 24 and 15 bit. Each change: status@cycles after word 32/words read. Read on bit 27, 24 bit run 1: E40400DF after the last word; 7 changes: E40500DF@801/0 E40000DF@1324/0 640000DF@1424/0 340000DF@1503/0 3C0000DF@1687/1 3C0100DF@1827/5 340100DF@2357/23 Read on bit 27, 24 bit run 2: E40400DF after the last word; 7 changes: E40500DF@822/0 E40000DF@1324/0 640000DF@1445/0 340000DF@1503/0 3C0000DF@1687/1 3C0100DF@1853/6 340100DF@2357/23 Read on bit 27, 15 bit run 1: E60400DF after the last word; 7 changes: E60500DF@806/0 E60000DF@1334/0 660000DF@1476/0 360000DF@1534/0 360100DF@1844/0 3E0100DF@1902/1 360100DF@2120/7 Read on bit 27, 15 bit run 2: E60400DF after the last word; 7 changes: E60500DF@822/0 E60000DF@1334/0 660000DF@1476/0 360000DF@1534/0 360100DF@1844/0 3E0100DF@1902/1 360100DF@2120/7 Done. ``` [followup23/04MNT.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/04MNT.txt) ``` ===== 04 MNT F23 MDEC MONO TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Row 85: the 4bit/8bit block (kBlkStream, 32 words, count 32) with its tables, no reads, the status for 3000 cycles after word 32, at 8 and 4 bit. Each change: status@cycles after word 32/words read. No reads, 8 bit run 1: E204FFFF after the last word; 3 changes: A204FFFF@235/0 2204FFFF@581/0 2A04FFFF@831/0 No reads, 8 bit run 2: E0041CFC after the last word; 2 changes: 60041CFC@83/0 68041CFC@1593/0 No reads, 4 bit run 1: E0041CFC after the last word; 2 changes: 60041CFC@89/0 68041CFC@1594/0 No reads, 4 bit run 2: E0041CFC after the last word; 2 changes: 60041CFC@83/0 68041CFC@1588/0 Done. ``` [followup23/05RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/05RUN.txt) ``` ===== 05 RUN F23 MDEC RUN PAST 63 | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 Row 95: q 1, DC 16, an AC run of 63, then each tail, 8 bit unsigned, count 32. end: 32 words C2FE5235 9ECF7B89 AC 1, end: 32 words C2FE5235 E240D580 AC 1, AC 1, end: 32 words C2FE5235 85A15D5D 7C01h, end: 32 words C2FE5235 FFDF0A60 run 63 again, end: 48 words C2FE5235 9ECF7B89 9ECF7B89 Done. ``` ## References [^fbx]: SCPH-5501 output: [followup23/01FBX.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/01FBX.txt). [^trw]: SCPH-5501 output: [followup23/02TRW.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/02TRW.txt). [^orq]: SCPH-5501 output: [followup23/03ORQ.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/03ORQ.txt). [^mnt]: SCPH-5501 output: [followup23/04MNT.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/04MNT.txt). [^run]: SCPH-5501 output: [followup23/05RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup23/05RUN.txt).