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--- title: SPU Voice Flags and Interrupts type: test summary: Measures SPU ENDX writes and clearing at key on, volume sweep limits, IRQ address timing, start addresses on an odd unit, reverb area use and sound RAM transfers. category: Hardware tests info: Machine = SCPH-5501 info: Program = followup18 --- ## Overview Each group parks all 24 voices on a silent block at 28000h, uploads its sample image there and reads the image back, and in every group none of the 512 halfwords differed. Root counter 2 counts system clock cycles, and one block of 28 samples at pitch 1000h is 21,504 cycles.[^exh][^viu] The groups write each half of ENDX, key on a voice at 16 phases of the sample clock, and run the volume sweep modes from positive and negative starts. Other groups set the IRQ address on each unit of a playing sample and on address 0000h, capture a voice after Gaussian interpolation and in noise mode, and start a voice on an odd 8-byte unit. The ninth group runs the reverb engine over a filled area. The last group reads SPUSTAT during a manual write and reads sound RAM back by DMA.[^exh][^ods][^rvb][^srg] See also: - [SPU Registers and Envelope](/tests/spu-registers-and-envelope/) - [SPU Noise Flags and Reverb](/tests/spu-noise-flags-and-reverb/) - [SPU Voice After End and Mute](/tests/spu-end-mute/) ## Results ### ENDX All 24 voices looped a block with flags 07h, so every ENDX bit was set. Writing 0000h to the low half of ENDX cleared bits 0 to 15 at once, and the register read 00FF0000h straight after the write. Writing 0000h to the high half cleared bits 16 to 23 in the same way. Every bit read set again 32,997 to 33,657 cycles after the write, as each voice reached the end of its block again.[^exh] Voice 1 was keyed on with its ENDX bit set, at 16 points from 109 to 1,546 cycles after SPUSTAT bit 11 rose. ENDX bit 1 read 0 at 2,168 to 2,247 cycles after the rise for every KON written up to 1,334 cycles after it. For a KON written at 1,439 and 1,546 cycles, the bit read 0 at 3,738 and 3,784 cycles. The three runs gave the same counts except at the first point.[^kex] ### Volume Sweep Voice 2's left volume was written as a fixed start value and then as a sweep with shift 5 and step 0. Each reading is the current volume, and the readings are 3,750 cycles apart. A014h from 4000h fell by 0800h or 0A00h a reading and reached 0000h at the seventh. In A014h and E014h a negative start read 0000h at the first reading. In B014h the starts 4000h, 0100h and FF00h read 0000h at the first reading, while B014h from C000h and F014h from FF00h and C000h moved toward 0.[^swc] Table: Volume sweep readings | Mode | Start | Readings 1 to 3 | Reading 8 | | --- | --- | --- | --- | | A014h | 4000h | 3600h 2C00h 2400h | 0000h | | A014h | C000h | 0000h 0000h 0000h | 0000h | | B014h | 4000h | 0000h 0000h 0000h | 0000h | | B014h | C000h | C8C0h D180h DA40h | 0000h | | E014h | 4000h | 3B25h 36A8h 3282h | 2293h | | E014h | FF00h | 0000h 0000h 0000h | 0000h | | F014h | 4000h | 3B25h 36A8h 3282h | 2293h | | F014h | FF00h | FF10h FF1Fh FF2Eh | FF67h | | F014h | C000h | C4D8h C950h CD71h | DD50h | | 8014h | 0100h | 09C0h 1280h 1B40h | 4540h | | 8014h | FF00h | 07C0h 1080h 1940h | 4500h | | 9014h | 0100h | F900h EF00h E500h | B300h | | C014h | FF00h | 07C0h 0EC0h 1780h | 4340h | | D014h | 0100h | F700h ED00h E300h | B300h | ### IRQ Address Voice 0 played an 8-block silent sample at pitch 1000h from unit 5010h. The IRQ address was set on unit 5010h + u. SPUSTAT bit 6 set 1,749 cycles after KON at u 0 and 7,273 cycles after it at u 1. From u 2 to u 15 the steps were about 9,200 and 12,270 cycles in turn. Each pair of units therefore added about 21,500 cycles, which is the length of one block.[^viu] Table: Cycles from KON to SPUSTAT bit 6 | Unit | Cycles | Unit | Cycles | | --- | --- | --- | --- | | +0 | 1,749 | +8 | 83,276 | | +1 | 7,273 | +9 | 92,468 | | +2 | 18,789 | +10 | 104,809 | | +3 | 27,986 | +11 | 113,997 | | +4 | 40,259 | +12 | 126,279 | | +5 | 49,513 | +13 | 135,486 | | +6 | 61,787 | +14 | 147,773 | | +7 | 71,003 | +15 | 157,023 | When each interrupt was acknowledged and the IRQ enabled again, units +0 and +4 hit 8 times in a row about 1,536 cycles apart. Units +1, +5 and +15 hit twice about 1,530 cycles apart. The pair came again about every 172,000 cycles, which is the length of the 8-block loop.[^viu] With the IRQ address at 0000h, CD volume 0 and transfer control 0004h, the IRQ hit 196,498 to 196,559 cycles after a rise of SPUSTAT bit 11 and then about every 393,200 cycles. SPUSTAT bit 11 was low at every hit. The times did not change with the reverb engine on or off, with the reverb registers zeroed, or with mBASE E000h. With transfer control 0000h there was no hit in 3.6 million cycles. The IRQ addresses 0080h and 0100h hit at the same times as 0000h.[^ciz] ### Start on an Odd Unit Sample A holds one value in bytes 2 to 7 of each block and another in bytes 10 to 15, with bytes 8 and 9 zero: 1000h and 2000h in block 0, 3000h and 4000h in block 1. Keyed on from its even start, voice 1 played levels near 0FEDh, 1FDCh and 2FCBh in turn. Keyed on from the odd unit 5031h, it began at 1FDEh and went on to 2FCEh and 3FBBh. From block 1's odd unit 5033h it began at 3FBFh. A start on an odd unit is therefore not rounded down to the block start, and the voice begins with the value in bytes 10 to 15.[^ods] ### Reverb Area and IRQ With the reverb engine on, the IRQ address at 4000h and every voice parked at 28000h, there was no hit in 2 million cycles with mBASE at 3F000h, 40000h, 41000h or 7F000h. With voice 0 parked at unit 4000h, the IRQ hit 509 to 625 cycles after the engine was turned on and then 1,501 to 1,557 cycles apart, at both mBASE 7F000h and 40000h.[^rvb] ### Transfers After SPUCNT was written 8010h for a manual write of 16 halfwords, SPUSTAT read 0410h from read 12 or 13 and 0010h from read 44 or 45. The 160 reads took 3,877 to 3,911 cycles, so each read took about 24 cycles. With 1 or 4 halfwords the value changed to 0010h at read 15 to 17 in five of the six runs. In the other run it read 0410h from read 3 and 0010h from read 35.[^srg] A DMA read of 8 halfwords with transfer control 0006h put a filler halfword after each of C000h, C001h, C002h and C003h. The filler was 0000h and FFFFh in alternate transfers. Of 32 words stored to 1C58h and loaded back, 31 read back whole, and one read back with its low half 0000h.[^srg] A DMA read of 128 bytes with 1F801014h set to 200931E1h began with FFFFh, and the data that followed were one halfword late. Two or three more halfwords in each read were FFFFh. With 1F801014h set to 220931E1h the 64 halfwords read back whole.[^srg] ## Runs ### 3 October 2026 [00RUN.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/00RUN.txt) ``` ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A 10 tests A chain program, linked at 80010000 Saved on the card in slot 2, from image 1 COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000 BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010F108 PRId 00000002 ``` [01EXH.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/01EXH.txt) ``` ===== 01 EXH F18 ENDX HALVES | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. All 24 voices keyed on together onto one silent block with flags 07h (end, repeat, loop start; nc adpcm-samples.txt:37-49) and released, so every ENDX bit sets as the loop ends. ENDX read as high half, low half; cycles from the write. 1 block = 21504 cycles. ENDX low half written 0000h: before 00FFFFFF, straight after 00FF0000, then: 33134:00FFFFFF ENDX high half written 0000h: before 00FFFFFF, straight after 0000FFFF, then: 33657:00FFFFFF ENDX low half written 0000h: before 00FFFFFF, straight after 00FF0000, then: 32997:00FFFFFF ENDX high half written 0000h: before 00FFFFFF, straight after 0000FFFF, then: 33629:00FFFFFF Done. ``` [02KEX.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/02KEX.txt) ``` ===== 02 KEX F18 KON ENDX PHASE | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Voice 1 loops the 07h block, its ENDX bit 1 set. After SPUSTAT bit 11 rises (a sample boundary, transfer control 0004h) the program waits 96k cycles, k = 0 to 15, and writes KON bit 1. Each entry: cycles from the rise to the KON write, then from the write until ENDX bit 1 reads 0 (0: not within 4000); * marks a bit that was not set before the KON. Run 1: 109:2105 179:1999 284:1894 389:1779 494:1718 564:1657 670:1544 774:1428 845:1369 949:1253 1055:1192 1165:1022 1235:957 1334:842 1439:2299 1546:2238 Run 2: 109:2119 179:1999 284:1894 389:1779 494:1718 564:1657 670:1544 774:1428 845:1369 949:1253 1055:1192 1165:1022 1235:957 1334:842 1439:2299 1546:2238 Run 3: 109:2119 179:1999 284:1894 389:1779 494:1718 564:1657 670:1544 774:1428 845:1369 949:1253 1055:1192 1165:1022 1235:957 1334:842 1439:2299 1546:2238 Done. ``` [03SWC.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/03SWC.txt) ``` ===== 03 SWC F18 SWEEP CLAMP | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Voice 2 left volume (1C20h) as a sweep, current volume 1E08h (spx:561-568, :650). Bit 15 sweep, 14 exponential, 13 decrease, 12 phase, 6-2 shift, 1-0 step. The start is a fixed volume written 4000 cycles before. Voice 2 plays the silent loop; main volume 0. Decrease modes, shift 5 step 0: A014 from 4000: first change 583, every 3750: 3600 2C00 2400 1A00 1000 0600 0000 0000 A014 from 0100: first change 534, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 A014 from FF00: first change 238, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 A014 from C000: first change 238, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 B014 from 4000: first change 164, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 B014 from 0100: first change 90, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 B014 from FF00: first change 90, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 B014 from C000: first change 313, every 3750: C8C0 D180 DA40 E300 EBC0 F480 FB80 0000 E014 from 4000: first change 460, every 3750: 3B25 36A8 3282 2EAD 2BD2 287E 256B 2293 E014 from 0100: first change 388, every 3750: 00EC 00D8 00C4 00B4 00A5 0099 008A 007C E014 from FF00: first change 90, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 E014 from C000: first change 238, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 F014 from 4000: first change 164, every 3750: 3B25 36A8 3282 2EAD 2B22 27DC 24D5 2293 F014 from 0100: first change 90, every 3750: 00EC 00D8 00C4 00B4 00A5 0096 0087 007A F014 from FF00: first change 91, every 3750: FF10 FF1F FF2E FF3D FF49 FF53 FF5D FF67 F014 from C000: first change 238, every 3750: C4D8 C950 CD71 D142 D4CA D80D DA7B DD50 Increase modes from 0100h and FF00h, shift 5 step 0: 8014 from 0100: first change 610, every 3750: 09C0 1280 1B40 2240 2B00 33C0 3C80 4540 8014 from FF00: first change 90, every 3750: 07C0 1080 1940 2200 2AC0 3380 3C40 4500 9014 from 0100: first change 756, every 3750: F900 EF00 E500 DB00 D100 C700 BD00 B300 9014 from FF00: first change 460, every 3750: F500 EB00 E100 D700 CF00 C500 BB00 B100 C014 from 0100: first change 389, every 3750: 09C0 1280 1B40 2400 2B00 33C0 3C80 4540 C014 from FF00: first change 686, every 3750: 07C0 0EC0 1780 2040 2900 31C0 3A80 4340 D014 from 0100: first change 164, every 3750: F700 ED00 E300 D900 CF00 C500 BB00 B300 D014 from FF00: first change 611, every 3750: F500 ED00 E300 D900 CF00 C500 BB00 B100 Exponential decrease, shift 5 step 3: E017 from 4000: first change 173, every 3750: 3CEE 3A01 3737 348F 3208 2FA0 2D56 2B94 E017 from C000: first change 90, every 3750: 0000 0000 0000 0000 0000 0000 0000 0000 F017 from 4000: first change 238, every 3750: 3CEE 3A01 3737 348F 3208 2FA0 2DC9 2B94 F017 from C000: first change 240, every 3750: C30E C5F6 C8BB CB5E CDE1 D045 D28C D44A Done. ``` [04VIU.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/04VIU.txt) ``` ===== 04 VIU F18 IRQ EACH UNIT | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Voice 0, pitch 1000h, an 8-block silent sample at 28080h (unit 5010h), looping (flags 04h, 00h x6, 03h). Cycles from KON to SPUSTAT bit 6 with the IRQ address on unit 5010h + u (0: none in 200000). One block = 28 samples = 21504 cycles. +0:1749 +1:7273 +2:18789 +3:27986 +4:40259 +5:49513 +6:61787 +7:71003 +8:83276 +9:92468 +10:104809 +11:113997 +12:126279 +13:135486 +14:147773 +15:157023 Up to 8 hits, each acknowledged (SPUCNT bit 6 off until SPUSTAT bit 6 reads 0, then on), cycles from KON, 400000 at most: unit +0: 1790 3360 4895 6431 7967 9503 11039 12575 unit +1: 6438 7967 178436 179964 350512 352047 unit +4: 40240 41775 43311 44847 46383 47919 49455 50991 unit +5: 49674 51202 221750 223285 393729 395263 unit +15: 156940 158461 328972 330493 Done. ``` [05CIZ.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/05CIZ.txt) ``` ===== 05 CIZ F18 IRQ AT UNIT 0 | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. IRQ address 0000h (CD left capture, spx:848-856), CD volume 1DB0h/1DB2h 0, SPUCNT bit 0 (CD audio) 0, every voice parked at 28000h. Up to 8 hits, acknowledged and re-armed, 3.6 million cycles at most; h/l = SPUSTAT bit 11 at the hit. 512 samples = 393216 cycles. Reverb registers as found (1DC0h-1DFEh): 033D 0231 7E00 5000 B400 B000 4C00 B000 6000 5400 1ED6 1A31 1D14 183B 1BC2 16B2 1A32 15EF 15EE 1055 1334 0F2D 11F6 0C5D 1056 0AE1 0AE0 07A2 0464 0232 8000 8000 found, IRQ 0000, DTC 0004, mBASE FFFE, bit 7 0, from bit 11 rising: 196506l 589766l 982962l 1376154l 1769414l 2162610l 2555802l 2949062l found, IRQ 0000, DTC 0000, mBASE FFFE, bit 7 0, from the arm: none found, IRQ 0000, DTC 0004, mBASE FFFE, bit 7 1, from bit 11 rising: 196559l 589755l 982947l 1376207l 1769403l 2162595l 2555855l 2949051l found, IRQ 0000, DTC 0000, mBASE FFFE, bit 7 1, from the arm: none found, IRQ 0000, DTC 0004, mBASE E000, bit 7 0, from bit 11 rising: 196549l 589741l 983001l 1376197l 1769389l 2162649l 2555845l 2949037l zeroed, IRQ 0000, DTC 0004, mBASE FFFE, bit 7 0, from bit 11 rising: 196559l 589755l 982947l 1376207l 1769403l 2162595l 2555855l 2949051l zeroed, IRQ 0000, DTC 0004, mBASE FFFE, bit 7 1, from bit 11 rising: 196498l 589758l 982954l 1376146l 1769406l 2162602l 2555794l 2949054l zeroed, IRQ 0000, DTC 0000, mBASE FFFE, bit 7 0, from the arm: none Controls, CD right and voice 1 capture offset 0: found, IRQ 0080, DTC 0004, mBASE FFFE, bit 7 0, from bit 11 rising: 196498l 589758l 982954l 1376146l 1769406l 2162602l 2555794l 2949054l found, IRQ 0100, DTC 0004, mBASE FFFE, bit 7 0, from bit 11 rising: 196503l 589695l 982955l 1376151l 1769343l 2162603l 2555799l 2948991l Done. ``` [06GRD.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/06GRD.txt) ``` ===== 06 GRD F18 GAUSS ROUNDING | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Voice 1 plays tone T (spuenv 12VCP: block 0 shift 4 filter 0 nibbles 0..F, block 1 shift 4 filter 1, looped), ADSR attack 0, decay Fh, sustain level Fh, then a sustain that never steps; its level written as shown. 64 samples of voice 1's capture (800h, after ADSR, spx:270-273), from the start of the first half, read after SPUSTAT bit 11 rises. T, pitch 1000: level 7FF7, written 7FFF reads 7FFF, after the capture 7FFF 04F9 05F8 0497 FA60 F907 FA06 FB05 FC03 FD02 FE01 FF00 FFFF 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907 FA06 FB11 FC50 FD8A FEAF FFC3 00C4 01B6 0299 036E 0436 04F1 05A1 0645 06DF 0724 05FD 049E 0354 021F 00FD FFEF FEF1 FE03 FD23 FC53 FB8E FAD5 FA29 FA94 FF31 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907 FA06 FB05 FC03 T, pitch 0800: level 7FF7, written 7FFF reads 7FFF, after the capture 7FFF 00DE 022D 02FB 037B 03FA 0479 04F9 0579 05F8 0643 0497 FF79 FA60 F8BB F907 F985 FA06 FA85 FB05 FB84 FC03 FC83 FD02 FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FD 017D 01FC 027C 02FB 037B 03FA 0479 04F9 0579 05F8 0643 0497 FF79 FA60 F8BB F907 F985 FA06 FA86 FB11 FBAD FC50 FCEF FD8A FE1F FEAF FF3C FFC3 0045 00C4 013F 01B6 022A T, pitch 1000: level 7FF7, written 3FFF reads 3FFF, after the capture 3FFF 014E 037B 04F9 05F8 0497 FA60 F907 FA06 FB05 FC03 FD02 FE01 FF00 FFFF 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907 FA06 FB11 FC50 FD8A FEAF FFC3 00C4 01B6 0299 01B7 021B 0278 02D0 0322 036F 0392 02FE 024F 01AA 010F 007E FFF7 FF78 FF01 FE91 FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 T, pitch 1000: level 7FF7, written 4000 reads 4000, after the capture 4000 04F9 05F8 0497 FA60 F907 FA06 FB05 FC03 FD02 FE01 FF00 FFFF 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907 FA06 FB11 FC50 FD8A FEAF FFC3 00C4 01B6 0299 036E 021B Done. ``` [07NLF.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/07NLF.txt) ``` ===== 07 NLF F18 NOISE LFSR | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. SPUCNT noise shift 15 step 3 (bits 13-10, 9-8, spx:701-702; a new level every sample, spu2 07SNO:70-74). Voice 1 noise mode (NON bit 1, spx:681) on the silent loop, keyed on, its level written 7FFFh in a sustain that never steps. 64 samples of its capture. Key on 1: noise, pitch 1000: level 7FF7, written 7FFF reads 7FFF, after the capture 7FFF 0000 0000 0000 0000 C9DC 0770 1101 2203 4408 8812 1024 2049 4094 812B 0255 04AC 0959 12B3 2567 4ACF 95A7 2B3C 5679 AD06 59FB B40A 6802 D017 A02F 404D 80AD 0149 0294 052A 0A55 14AA 2956 52AC A564 4AC8 9592 2B23 5647 AC91 5921 B245 648A C916 922D 245A 48B5 916C 22D8 45B2 8B66 16CC 2D9A 5B36 B66F 6CDD D9BD B37A 66F4 CDEA Key on 2: noise, pitch 1000: level 7FF7, written 7FFF reads 7FFF, after the capture 7FFF 0000 0000 0C09 3027 6E12 DC27 B84F 709D E13C C278 84F0 09E0 13C1 2783 4F07 9E11 3C22 7845 F08D E11B C23A 8474 08D8 11B0 2361 46C4 8D9A 1B22 3645 6C8B D929 B253 6495 C93D 9275 24EA 49D5 93AC 2758 4EB1 9D65 3ACA 7596 EB2F D65F ACBE 597B B2F9 65F2 CBE6 97CD 2F99 5F34 BE6A 7CD4 F9AA F354 E6A9 CD53 9AA6 354B 6A98 D532 AA64 The same at level 4000h: noise, pitch 1000: level 7FF7, written 4000 reads 4000, after the capture 4000 0000 0000 0000 0000 0000 0000 0000 0000 1C65 9198 03A5 074C 0E99 1D34 3A69 74D4 E9AB D357 A6AF 4D5E 9AC6 357A 6AF5 D5FC ABF9 57E2 AFD8 5F9F BF50 7E90 FD32 FA65 Done. ``` [08ODS.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/08ODS.txt) ``` ===== 08 ODS F18 ODD START | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Sample A at 28180h (unit 5030h): four blocks, each header 00h (shift 0 filter 0); bytes 2-7 one value, bytes 8-9 00h 00h (as a header: shift 0, filter 0, no flags), bytes 10-15 another: 1000h,2000h / 3000h,4000h / 5000h,6000h / 7000h,1000h, flags 03h at block 3's bytes 1 and 9. Repeat written 5000h (silent loop). Voice 1 capture (the whole ring). Even start (unit 5030), pitch 1000, repeat after 5000: onset at 78, from 4 before it: 0000 0000 0000 0000 06F8 0DF0 0FED 0FED 0FED 0FED 0FEC 0FED 0D8D 0257 0000 FFFF 04C0 1B2B 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 223D 2D72 2FCB 2FCB 2FCB 2FCB 2FCB 2FCB Odd start (unit 5031), pitch 1000, repeat after 5000: onset at 482, from 4 before it: 0000 0000 0000 0000 0DF1 1BE3 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 223F 2D75 2FCE 2FCE 2FCE 2FCE 2FCE 2FCE 2FCE 2FCE 2FCB 2FCC 28AA 0709 0000 FFFF 0982 3658 3FBB 3FBB 3FBB 3FBB 3FBB 3FBB Block 1 odd (unit 5033), pitch 1000, repeat after 5000: onset at 382, from 4 before it: 0000 0000 0000 0000 1BE4 37C8 3FBF 3FBF 3FBF 3FBF 3FBB 3FBA 421B 4D50 4FA8 4FA8 4FA8 4FA8 4FA8 4FA8 4FA8 4FA8 4FA8 4FA9 43C6 0BBB 0000 FFFF 0E42 5184 5F98 5F98 5F98 5F98 5F98 5F98 Odd start (unit 5031), pitch 0400, repeat after 5000: onset at 280, from 4 before it: 0000 0000 0000 0000 0DF1 1BE3 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 1FDE 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC 1FDC Done. ``` [09RVB.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/09RVB.txt) ``` ===== 09 RVB F18 REVERB | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Reverb area 7F000h-7FFFFh (mBASE FE00h), filled with 0100h + index (or as shown), then SPUCNT as shown (bit 7 on) for 60000 cycles and read back (nc reverb-formula.txt:4-34). Addresses as spu2 12SRV; vLOUT/vROUT 0. G rows: voice 1 (volume 3FFFh) loops a block of one value into the reverb (EON bit 1), vLIN/vRIN 4000h, vIIR 7FFFh, main volume as shown. Each: halfwords changed, a CRC, and the first 12 changes (index from 7F000h:value). G0 DC 7000h, main 0, bit 14 0: 316 changed, crc 8BBE7E0F 116:0000 117:0000 118:0000 119:0000 11A:0000 11B:0000 11C:0000 11D:0000 11E:0000 11F:0000 120:0000 121:0000 G1 DC 7000h, main 3FFFh, bit 14 0: 312 changed, crc 931F5ABD 116:0000 117:0000 118:0000 119:0000 11A:0000 11B:0000 11C:0000 11D:0000 11E:0000 11F:0000 120:0000 121:0000 G2 DC 7000h, main 0, bit 14 1: 312 changed, crc EE299EBE 116:FFFF 117:0000 118:FFFB 119:0009 11A:FFDD 11B:0050 11C:FF45 11D:0188 11E:FC7F 11F:0DEE 120:3B3E 121:3635 G2 DC 0100h, main 0, bit 14 1: 312 changed, crc BBD4D9C9 116:FFFF 117:FFFF 118:FFFF 119:FFFF 11A:FFFF 11B:0000 11C:FFFD 11D:0001 11E:FFF7 11F:001D 120:0083 121:0078 G3 DC 0100h, main 3FFFh, bit 14 1: 312 changed, crc BBD4D9C9 116:FFFF 117:FFFF 118:FFFF 119:FFFF 11A:FFFF 11B:0000 11C:FFFD 11D:0001 11E:FFF7 11F:001D 120:0083 121:0078 vIIR 4000h: 312 changed, crc 00B4E30E 101:0100 102:0080 103:0040 104:0020 105:0010 106:0008 107:0004 108:0002 109:0001 10A:0000 10B:0000 10C:0000 vIIR 8000h: 312 changed, crc EC7F6D8B 101:FC00 102:0800 103:F000 104:2000 105:C000 106:7FFF 107:8000 108:0000 109:0000 10A:0000 10B:0000 10C:0000 vIIR C000h: 312 changed, crc B1D24D61 101:0300 102:0480 103:06C0 104:0A20 105:0F30 106:16C8 107:222C 108:3342 109:4CE3 10A:7354 10B:7FFF 10C:7FFF vIIR 4000h, area 1000h: 248 changed, crc AA5804C4 101:0800 102:0400 103:0200 104:0100 105:0080 106:0040 107:0020 108:0010 109:0008 10A:0004 10B:0002 10C:0001 vIIR C000h, area 1000h: 248 changed, crc 66F45644 101:1800 102:2400 103:3600 104:5100 105:7980 106:7FFF 107:7FFF 108:7FFF 109:7FFF 10A:7FFF 10B:7FFF 10C:7FFF vIIR 8000h, area 1000h: 248 changed, crc 32CD6515 101:E000 102:4000 103:8000 104:0000 105:0000 106:0000 107:0000 108:0000 109:0000 10A:0000 10B:0000 10C:0000 IRQ9 with the engine on (bit 7; vIIR 4000h, combs, vWALL, APFs 2000h), voices parked at 28000h, up to 4 hits from SPUCNT bit 7 on, 2 million cycles each (nc reverb-formula.txt: 36-46; spu2 13SIR:17 hit at IRQ 4000h with mBASE 8000h, with spu2's voices parked at unit 4000h): mBASE 3F000h, mBASE 7E00, IRQ 4000: hits none mBASE 40000h, mBASE 8000, IRQ 4000: hits none mBASE 41000h, mBASE 8200, IRQ 4000: hits none mBASE 7F000h, mBASE FE00, IRQ 4000: hits none Voice 0 parked at unit 4000h, mBASE 7F000h, mBASE FE00, IRQ 4000: hits 625 2182 3718 5254 Voice 0 parked at unit 4000h, mBASE 40000h, mBASE 8000, IRQ 4000: hits 509 2010 3546 5082 Done. ``` [10SRG.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/10SRG.txt) ``` ===== 10 SRG F18 SPU REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 The image at 28000h uploaded and read back: 0 halfwords of 512 differ. Manual Write (SPUCNT 8010h) of k halfwords from the Fifo to 30000h: SPUSTAT (bit 11 masked) read 160 times back to back from the SPUCNT write; the cycles the 160 reads took, and each change as read number:value. Three runs. k 1: was 0000, 3911 cycles: 3:0410 35:0010 k 1: was 0000, 3879 cycles: 16:0010 k 1: was 0000, 3878 cycles: 17:0010 k 4: was 0000, 3877 cycles: 15:0010 k 4: was 0000, 3878 cycles: 15:0010 k 4: was 0000, 3878 cycles: 16:0010 k 16: was 0000, 3877 cycles: 12:0410 44:0010 k 16: was 0000, 3878 cycles: 12:0410 44:0010 k 16: was 0000, 3882 cycles: 13:0410 45:0010 Type 3 (transfer control 0006h) DMA read of 8 halfwords at 30000h holding C000h, C001h, ..; the buffer was EEEEh. Six times: C000 0000 C001 0000 C002 0000 C003 0000 EEEE EEEE C000 FFFF C001 FFFF C002 FFFF C003 FFFF EEEE EEEE C000 0000 C001 0000 C002 0000 C003 0000 EEEE EEEE C000 FFFF C001 FFFF C002 FFFF C003 FFFF EEEE EEEE C000 0000 C001 0000 C002 0000 C003 0000 EEEE EEEE C000 FFFF C001 FFFF C002 FFFF C003 FFFF EEEE EEEE 32 sw to 1C58h of (1000h + 101h i) << 16 | (2000h + 303h i), each after both halves were written 0; timer 2 just before the sw (low 3 bits) and the lw back: 3:10002000 6:11012303 4:12022606 2:13032909 0:14042C0C 6:15052F0F 4:16063212 2:17073515 0:18083818 6:19093B1B 4:1A0A3E1E 2:1B0B4121 0:1C0C4424 6:1D0D4727 4:1E0E4A2A 2:1F0F4D2D 0:20105030 6:21115333 4:22125636 2:23135939 0:24145C3C 6:25155F3F 4:26166242 2:27176545 0:28186848 6:29196B4B 4:2A1A6E4E 2:2B1B7151 1:2C1C7454 3:2D1D7757 1:2E1E0000 7:2F1F7D5D Low half wrong 1, high half wrong 0. DMA read of 128 bytes at 30000h holding D000h, D001h, .. (uploaded and drained), the buffer EEEEh, with 1F801014h as shown: 200931E1: FFFF D000 D001 D002 D003 D004 D005 D006 D007 D008 D009 D00A D00B D00C D00D D00E D00F D010 D011 D012 FFFF D014 D015 D016 D017 D018 D019 D01A D01B D01C D01D D01E FFFF D020 D021 D022 D023 D024 D025 D026 D027 D028 D029 D02A D02B D02C D02D D02E D02F D030 D031 D032 D033 D034 D035 D036 D037 D038 D039 D03A D03B D03C D03D D03E 200931E1: FFFF D000 D001 D002 D003 D004 D005 D006 D007 D008 D009 D00A FFFF D00C D00D D00E D00F D010 D011 D012 D013 D014 D015 D016 D017 D018 D019 D01A D01B D01C D01D D01E FFFF D020 D021 D022 D023 D024 D025 D026 FFFF D028 D029 D02A D02B D02C D02D D02E D02F D030 D031 D032 D033 D034 D035 D036 D037 D038 D039 D03A D03B D03C D03D D03E 200931E1: FFFF D000 D001 D002 D003 D004 D005 D006 D007 D008 D009 D00A D00B D00C D00D D00E D00F D010 D011 D012 D013 D014 FFFF D016 D017 D018 D019 D01A D01B D01C D01D D01E FFFF D020 D021 D022 D023 D024 D025 D026 FFFF D028 D029 D02A D02B D02C D02D D02E D02F D030 D031 D032 D033 D034 D035 D036 D037 D038 D039 D03A D03B D03C D03D D03E 220931E1: D000 D001 D002 D003 D004 D005 D006 D007 D008 D009 D00A D00B D00C D00D D00E D00F D010 D011 D012 D013 D014 D015 D016 D017 D018 D019 D01A D01B D01C D01D D01E D01F D020 D021 D022 D023 D024 D025 D026 D027 D028 D029 D02A D02B D02C D02D D02E D02F D030 D031 D032 D033 D034 D035 D036 D037 D038 D039 D03A D03B D03C D03D D03E D03F Done. ``` ## References [^exh]: SCPH-5501 output: [followup18/01EXH.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/01EXH.txt) [^kex]: SCPH-5501 output: [followup18/02KEX.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/02KEX.txt) [^swc]: SCPH-5501 output: [followup18/03SWC.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/03SWC.txt) [^viu]: SCPH-5501 output: [followup18/04VIU.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/04VIU.txt) [^ciz]: SCPH-5501 output: [followup18/05CIZ.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/05CIZ.txt) [^ods]: SCPH-5501 output: [followup18/08ODS.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/08ODS.txt) [^rvb]: SCPH-5501 output: [followup18/09RVB.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/09RVB.txt) [^srg]: SCPH-5501 output: [followup18/10SRG.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup18/10SRG.txt)