Serial Interfaces (SIO)

Registers of the two serial interfaces of the PlayStation.

Summary

The PlayStation has two serial interfaces. SIO0 at 1F801040h drives the controller ports and Memory Card slots and is hardwired to a synchronous master mode similar to SPI. SIO1 at 1F801050h drives the serial port on the back of the unit and is hardwired to asynchronous (UART) mode.¹ The two units are alike but not identical, and psx-spx describes them as loosely based on the Intel 8251A USART.¹

The serial port connects two PlayStations with a link cable, which Sony's libcomb supports for two-player games, and libsio uses it for standard input and output to a PC during development.^{2 3} The controller protocol page describes the byte exchange on SIO0.

Each unit has the following registers. The base is 1F801040h for SIO0 and 1F801050h for SIO1:¹

Sony's header libsio.h of Run-Time Library 4.7 defines names for the SIO1 status, control and mode bits. The bit names below are those names; SIO0 has no official names.^{4 1}

DR - Data Register

A read returns the oldest byte of the receive FIFO in bits 0 to 7, and bits 8 to 31 preview the next three entries. A byte can be read when SR bit 1 is set. psx-spx recommends 8-bit access only, because some emulators handle 16-bit and 32-bit reads incorrectly.⁵

A write to bits 0 to 7 starts a transfer once TXEN is 1, CTS is on and SR bit 2 shows the transmitter ready. A write while SR bit 0 is 0 overwrites the waiting byte.⁵ The write also latches the current TXEN, and the transfer starts if either the current or the latched value is set. A transfer can therefore still start after TXEN is cleared, which psx-spx reports Wipeout 2097 relies on.⁵

The transmitter holds nearly 2 bytes. One byte is being sent, and once its start bit has gone out one more can wait in DR. A write to DR clears SR bits 0 and 2, bit 0 is set again when the transfer starts, and bit 2 is set when the last written byte has been sent.⁶

The receive FIFO holds 8 bytes. A byte received while the FIFO is full overwrites the last entry and sets the overrun bit, and the hardware does not drop RTS by itself.⁷ Sony's link cable manual describes the same controller with a 1-byte transmission buffer and an 8-byte receiving buffer, and an interrupt after 1, 2, 4 or 8 received bytes.^{8 9}

psx-spx reports two read quirks. A 16-bit read returns two FIFO entries but removes only one, while a 32-bit read removes four. A read from the empty FIFO returns the last byte received, or zero once the copies run out.⁷

SR - Status Register

Bit 0 is set after the start bit has been sent, and bit 2 after all bits including the stop bit.¹⁰ The same bits appear in Sony's driver status table for the link cable, with bit 9 as interrupt on, bit 8 CTS, bit 7 DSR, bit 5 frame error, bit 4 overrun, bit 3 parity error, bit 2 no sending data, bit 1 receive data readable and bit 0 send data writable.⁹

On SIO0 the DSR input is wired to the /ACK pin of the controller ports. Bit 7 is therefore 1 while /ACK is low, and bits 4 to 6 and 8 are always zero.¹⁰

MR - Mode Register

Sony's communication mode table for the link cable gives the same layout but reverses bit 5, with 1 for odd parity and 0 for even. libsio.h names bit 5 MR_P_EVEN, and psx-spx gives 1 for even.^{9 4 11}

On SIO0 the character length must be 8 bits, the clock high when idle and parity disabled, because all controllers and Memory Cards expect these settings.¹¹ libcomb accepts only 8-bit characters without parity and uses 2 stop bits by default.¹²

CR - Control Register

On SIO0 the DTR output is wired to /CS. Bit 1 pulls /CS low on the port that bit 13 selects, and all other signals are shared by both ports.¹³ Bit 2 also works differently on SIO0: when it is 0 a byte is received only while bit 1 is set, and when it is 1 one byte is received regardless of /CS and the bit then clears itself.¹³

psx-spx notes that the kernel's controller driver uses only the DSR (/ACK) interrupt of SIO0.¹³

The interrupt is acknowledged by first clearing the interrupt controller flag (bit 8 for SIO1) and then setting CR bit 4. In the other order a new interrupt that occurs just after bit 4 is set may be missed. The interrupt returns almost at once if the enabled condition is still true when bit 4 is set.¹⁴

BR - Baud Rate Register

BR holds a 16-bit reload value for the baud rate timer. The timer is decremented on every clock cycle and reloaded when BR is written and when it reaches zero, and on reload the value is multiplied by the MR factor and divided by 2. The bit rate is therefore:¹⁵

SIO0: BitsPerSecond = 33868800 / MAX(((Reload*Factor) AND NOT 1),1)
SIO1: BitsPerSecond = 33868800 / MAX(((Reload*Factor) AND NOT 1),Factor)

Controllers and Memory Cards run at about 250 kHz, which the kernel sets with BR = 0088h: the clock is high for 44h cycles and low for 44h cycles.¹⁵ libcomb sets the link cable to a rate from 1 to 2,073,600 bps that divides 2,073,600. The default is 9600 bps.¹²

SIO1 Control Lines

The serial controller has two pairs of control lines, DTR/DSR and RTS/CTS. libcomb uses both pairs for synchronous read() and write().⁹ psx-spx reports that the transmitter sends only while CTS is on.¹⁰

1F80105Ch is an internal SIO1 register that software should not access. psx-spx reports that a value written there reads back rotated by 8 bits and partly masked. SIO0 has no such register.¹⁶

References