SPU Registers

I/O registers of the Sound Processing Unit at 1F801C00h to 1F801FFFh.

Summary

The SPU is controlled through 16-bit registers at 1F801C00h to 1F801FFFh. Sony did not publish register-level SPU documentation, so the register names on this page are the ones psx-spx uses.¹ The older psx-spx by Martin Korth calls ATTR "SPUCNT" and STATX "SPUSTAT", and both names are common in other documents.² The register areas are as follows:

Bus Access

The SPU sits on a 16-bit data bus. Reads of 8, 16 and 32 bits work, and 16-bit writes work. 32-bit writes are supported but occasionally lost, so a 32-bit value is best written as two 16-bit halves. 8-bit writes are not implemented: a byte write to an odd address is ignored, and a byte write to an even address is performed as a 16-bit write of the low half of the register.³

The SPU processes written values at its 44.1 kHz rate. A new value therefore takes up to 1/44100 second (300h CPU cycles) to take effect.³ Sony states the same limit for libspu: at least 1/44100 second of SPU processing must pass between two calls that set the same function.⁴

Voice Registers

Each voice N has the eight registers below at 1F801C00h + N x 10h.

PITCH

PITCH sets the ADPCM sample rate of the voice. The value 1000h is 44100 Hz.⁵

Sony's libspu takes pitch values from 0000h to 3FFFh. The relation between the value set and the interval of the original sample is shown below.⁶

The pitch for a VAG sample follows from the sampling frequency in its header: pitch = (sampling frequency << 12) / 44100. A 44.1 kHz sample therefore plays at 1000h and a 22.05 kHz sample at 800h.⁴

The pitch counter of each voice advances by PITCH once per 44.1 kHz cycle. Bits 12 and up of the counter select the sample within the ADPCM block, and bits 4 to 11 are the index into the Gaussian interpolation table. A step above 3FFFh is clipped to 4000h, so the highest rate is 176.4 kHz. However, the mixer outputs only 44.1 kHz, and any rate above that makes the hardware skip samples. PITCH has no effect on noise, whose rate is set in ATTR for all voices at once.⁵

SSA

SSA holds the start address of the sample in the sound buffer in 8-byte units. Key On copies SSA to the internal current address of the voice, and the register itself does not advance during playback. A write to SSA therefore has no effect on a voice that is already playing.⁷

LSAX

LSAX holds the loop address in 8-byte units. When the voice reaches a block with the Loop Start flag, the hardware copies the current address into LSAX, and when it finishes a block with the Loop End flag, it jumps to the address in LSAX. Looping therefore works from the sample data alone. Reading LSAX shows whether a Loop Start flag has been reached, and writing it can send a one-shot sample to a silent loop elsewhere in memory.⁷ The block flags are described in SPU ADPCM.

Voice Flag Registers

Each voice flag is a set of 24 bits in two registers: the low register holds voices 0 to 15 and the high register holds voices 16 to 23.⁸

Key On sets the envelope volume of the voice to zero and starts the attack. Key Off is normally written during sustain, but it can be written at any time, and the voice then goes straight to release. Reading KON or KOF returns the last value written, so neither register shows whether a voice is sounding. ENDX is the status register: Key On clears the bit of the voice, and a Loop End flag in an ADPCM header sets it. A value written to ENDX can be read back for a short time before the hardware overwrites it.⁸

PMON

PMON bit N makes the output of voice N-1 modulate the pitch of voice N, and bit 0 is therefore unused.⁵ Sony describes the effect as an LFO between adjoining voices, with NewPitch(n) = (1 + V(n-1)) x Pitch(n), where V(n-1) is the volume of voice n-1. Two voices are consequently used to make one tone.⁹ In the hardware the factor is the output of voice n-1 plus 8000h, which gives a range of 0.00 to 1.99. The product is clipped to 4000h after the multiplication, so PITCH values of 4000h to 7FFFh are useful with modulation. Values of 8000h and up are mistaken for negative numbers.⁵

NON

A voice with its NON bit set plays the noise generator in place of its ADPCM data. The SPU has one noise generator, and its rate comes only from the shift and step fields in ATTR. All noise voices therefore play at the same frequency, and the only way around this is a random ADPCM pattern in the sound buffer. The generator runs once per 44.1 kHz cycle as follows:¹⁰

Timer = Timer - NoiseStep           ; NoiseStep is 4 to 7
ParityBit = Level.bit15 xor bit12 xor bit11 xor bit10 xor 1
if Timer < 0: Level = Level * 2 + ParityBit
if Timer < 0: Timer = Timer + (20000h >> NoiseShift)
if Timer < 0: Timer = Timer + (20000h >> NoiseShift)

Control Registers

Every register that holds a sound buffer address holds the byte address divided by 8.¹¹

ATTR

Changes to bits 0 to 5 take effect after a delay, so software waits until the low bits of STATX show the new value. Before a new transfer mode is set, the Stop mode is set first and confirmed in STATX in the same way.¹² Clearing bit 7 stops the SPU from writing the reverb buffer, which is needed while the buffer is cleared. However, reads from the reverb buffer still reach the output, and the reverb output volume must be set to zero to silence it.¹³

STATX

STATX is read-only in practice: a written value reads back for a short time before the hardware overwrites it.¹²

Bit 11 tells which half of the four 1KB capture buffers the SPU is writing. It works only when bit 2 or bit 3 of RAM_CTRL is set.¹²

Volume Registers

MVOLL, MVOLR, VOLL and VOLR each have a direct mode and a sweep mode, and both encodings are given in ADSR and Volume. AVOLL, AVOLR, BVOLL and BVOLR are plain signed 16-bit volumes from -8000h to +7FFFh. The current volume registers read the live level of each sweep and are not normally written by software.¹⁴

The level that reaches the mixer for each side of a voice is (ENVX x VOLX) >> 15.¹⁴

Sound Buffer Transfer

TSA and DATA

TSA holds the sound buffer address for manual and DMA transfers. A write to TSA also loads an internal current address, and it is this internal address that advances during the transfer while TSA keeps its value. DATA is the FIFO for manual writes and holds up to 32 halfwords.¹¹

RAM_CTRL

RAM_CTRL is not initialized at power on, so software must write it before the sound buffer is accessed.¹¹

The value 0004h selects a single 512KB bank, which is the configuration of all known retail, development and arcade hardware. Other values change the address unit to match a larger memory, and on a 512KB console they corrupt writes by repeating or dropping halfwords from the FIFO.¹¹ Reverb also stays off until RAM_CTRL is set.¹⁵

Manual Write

For more than one block, steps 4 to 6 repeat. However, ATTR is then already in manual write mode and STATX does not change, so a delay of at least 300h cycles replaces the wait in step 5.¹¹

DMA Write and Read

No method is known to read the sound buffer without DMA. A DMA read is also unstable when bits 24 to 27 of DEV4_CTRL are zero: each block then starts with an inserted FFFFh and loses its last halfword. Setting DEV4_CTRL to 220931E1h avoids the problem.¹¹

libspu Transfers

SpuWrite() transfers data from main memory to the sound buffer and SpuRead() transfers it back. libspu has two transfer modes. DMA transfer is the default: it runs asynchronously, so the CPU can do other work, and SpuIsTransferCompleted() must be called afterward. I/O transfer is write-only and uses the CPU, so nothing else runs until it ends. Because a read always uses DMA, its destination must be a large static variable or a heap area, not a stack or auto variable. SpuSetTransferStartAddr() must be called before any transfer.¹⁶

If CDInit() is not called before SpuInit(), detection of transfer completion may fail. This happens in particular with SpuIsTransferCompleted(SPU_TRANSFER_WAIT).¹⁶

Interrupt

IRQA holds an address in the sound buffer divided by 8. The SPU raises interrupt 9 when the address is accessed, provided ATTR bit 6 is set, and STATX bit 6 shows the request. The accesses that trigger it are shown below.¹⁷

Every voice reads the sound buffer all the time, even in noise mode, at zero volume or after release. A silent voice can therefore trigger the interrupt, and unused voices are best pointed at an endlessly looped silent block. The IRQ address is also best aligned to a 16-byte ADPCM block, because an address inside a block sometimes misses.¹⁷

An IRQ address in the capture area (0000h to 01FFh) triggers on the SPU's own capture writes. Each capture buffer holds 200h samples, so the rate is about 86.13 Hz (44100 / 200h). Capture interrupts do not occur when bits 2 and 3 of RAM_CTRL are both zero.¹⁷

In libspu, SpuSetIRQAddr() sets the address, SpuSetIRQ() enables or disables the interrupt, and SpuSetIRQCallback() registers the function to call.¹⁸

Unknown Registers

1F801DA0h, 1F801DBCh to 1F801DBFh and 1F801E60h to 1F801E7Fh can be read and written, but writes to them have no known effect on sound output, and the SPU does not change them.¹⁹

References