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CPU Loop During DMA2 and Timer Reads

Measures how much a cached CPU loop slows during DMA2 lists of different shapes, a RAM store followed by a load, and timer 2 read in a loop with reset at target and after a mode or counter write.

CPU Loop During DMA2 and Timer Reads
MachineSCPH-5501
Programfollowup32

This is an old revision of this page, as edited by RemmyLee at 05:49, 23 October 2026. Edit this revision | Latest revision

Overview

The program runs three groups, and each one times a loop and prints its time in cycles.1 In RLT, timer 1 on the 33.8688 MHz clock times the loop while timer 2 is the timer under test.2

Table 1: Groups
Tag Group
CWN A cached loop of 5000 turns (addiu, bne, nop) with no bus access, alone and straight after a DMA2 list starts, for lists of 1 to 1024 nodes of 0 to 255 words
SLP 1000 turns of a RAM store, n NOPs, a RAM lw and a NOP, with the load in another page or on the stored word, and with the store's address stepping through a 32 KB window
RLT Timer 2 reset at target 1, 2, 3 or 10, read 1000 times by a loop from RAM with k NOPs, and the time from a mode or counter write to the first tick

See also:

Results

Cached Loop During a DMA2 List

Alone, the loop took 15,060 to 15,065 cycles. During a list the loop took up to 284 cycles longer. A list of 256 nodes of 4 words cost the loop 4 or 5 cycles. Four nodes of 255 words cost the loop 273 cycles, and 16 nodes of 255 words cost it 277 or 278. A single node of 255 words left the loop 7 cycles faster than alone.3

Table 2: Cycles the loop lost during each list in the first of two runs
List Words List alone Loop lost
16 nodes of 0 words 0 192 28
1024 nodes of 0 words 0 10,478 18
1 node of 255 words 255 24 -7
4 nodes of 255 words 1,020 861 273
8 nodes of 128 words 1,024 1,068 128
32 nodes of 32 words 1,024 1,522 46
64 nodes of 16 words 1,024 2,038 15
128 nodes of 8 words 1,024 2,962 9
256 nodes of 4 words 1,024 5,034 4
16 nodes of 64 words 1,024 1,240 72
16 nodes of 128 words 2,048 2,268 132
16 nodes of 255 words 4,080 4,279 277

The two runs of 8 nodes of 128 words differed: the loop lost 128 cycles in the first and 284 in the second.3

Store Then Load

A thousand turns of a store, n NOPs and a load took 14,311 to 14,328 cycles for n 0 to 5 and 15,152 to 15,173 cycles for n 6. A load of the stored word gave the same times as a load in another page. With the store's address stepping by 0 to 4,096 bytes a turn, the times were 14,330 to 14,347 cycles with no NOP, 15,172 to 15,192 with 4 NOPs and 16,118 to 16,131 with 5 NOPs. The size of the step made no difference.4

Timer 2 was read once a turn over 200 turns. It advanced by 24 cycles in 189 to 191 of the turns. The other turns took 29 or 30 cycles, except for one turn of 25 cycles and the first turn, which took 82 to 86.4

Timer 2 Read in a Loop

The loop of 1000 reads with k NOPs took 10,067 cycles with no NOP and 11,067 with one. With 2, 3 or 4 NOPs it took 12,067 to 12,072 cycles, and from 5 NOPs on each NOP again added 1,000 cycles, which is one cycle a turn. With target 1 and the 33.8688 MHz clock the count read only 0 or 1.2 From a write of timer 2's mode or of its counter to the first tick seen on timer 1, the time was 27 cycles in all 16 tries from a cold cache and 22 cycles in all 16 tries warm.2

Runs

5 October 2026

followup32/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
3 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010B13C PRId 00000002

followup32/01CWN.txt

===== 01 CWN F32 CACHED LOOP BY NODES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
A cached loop of 5000 turns (addiu, bne, nop; no bus access) alone and straight after
a DMA2 list starts: list = the list alone, polled (cycles); loop alone; during; twice.
  16 nodes of   0 words (   0 words): list 192, loop 15060, during 15088 (+28); list 161, loop 15060, during 15082 (+22);
  16 nodes of  16 words ( 256 words): list 488, loop 15060, during 15080 (+20); list 488, loop 15060, during 15090 (+30);
  16 nodes of  64 words (1024 words): list 1240, loop 15060, during 15132 (+72); list 1246, loop 15060, during 15132 (+72);
  16 nodes of 128 words (2048 words): list 2268, loop 15060, during 15192 (+132); list 2262, loop 15060, during 15202 (+142);
  16 nodes of 255 words (4080 words): list 4279, loop 15060, during 15337 (+277); list 4271, loop 15060, during 15338 (+278);
   1 nodes of 255 words ( 255 words): list 24, loop 15060, during 15053 (+-7); list 24, loop 15060, during 15053 (+-7);
   4 nodes of 255 words (1020 words): list 861, loop 15060, during 15333 (+273); list 861, loop 15060, during 15333 (+273);
   8 nodes of 128 words (1024 words): list 1068, loop 15064, during 15192 (+128); list 1058, loop 15060, during 15344 (+284);
  32 nodes of  32 words (1024 words): list 1522, loop 15060, during 15106 (+46); list 1528, loop 15060, during 15096 (+36);
  64 nodes of  16 words (1024 words): list 2038, loop 15065, during 15080 (+15); list 2022, loop 15065, during 15080 (+15);
 128 nodes of   8 words (1024 words): list 2962, loop 15063, during 15072 (+9); list 2969, loop 15060, during 15078 (+18);
 256 nodes of   4 words (1024 words): list 5034, loop 15064, during 15068 (+4); list 5028, loop 15063, during 15068 (+5);
  64 nodes of   0 words (   0 words): list 659, loop 15060, during 15082 (+22); list 647, loop 15060, during 15082 (+22);
 256 nodes of   0 words (   0 words): list 2614, loop 15060, during 15082 (+22); list 2621, loop 15060, during 15086 (+26);
1024 nodes of   0 words (   0 words): list 10478, loop 15064, during 15082 (+18); list 10477, loop 15065, during 15082 (+17);
Done.

followup32/02SLP.txt

===== 02 SLP F32 STORE THEN LOAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
A RAM store, n NOPs, a RAM lw, nop, then addiu, bne, nop (cpu6 01SLS, 100 turns:
n 0 1471, n 4 1478, n 5 1484). 1000 turns, three runs each.
sw, n NOPs, lw of another page (n 0-6): n0 14320/14311/14317 n1 14325/14316/14313 n2 14316/14311/14313 n3 14321/14320/14314 n4 14325/14317/14322 n5 14320/14320/14321 n6 15173/15160/15158
sw, n NOPs, lw of the same word (n 0-6): n0 14322/14315/14322 n1 14328/14313/14326 n2 14324/14315/14321 n3 14316/14321/14314 n4 14325/14317/14322 n5 14320/14320/14321 n6 15167/15156/15152
The store's address stepping by s bytes a turn in a 32 KB window (addiu, and, addu
after the load's nop), 1000 turns:
step    0: n0 14338/14333 n4 15190/15176 n5 16121/16121
step    4: n0 14340/14331 n4 15185/15175 n5 16121/16121
step   16: n0 14343/14337 n4 15179/15183 n5 16125/16118
step   64: n0 14347/14330 n4 15189/15173 n5 16126/16125
step  256: n0 14331/14340 n4 15178/15172 n5 16131/16126
step 1024: n0 14341/14333 n4 15190/15176 n5 16121/16121
step 2048: n0 14347/14332 n4 15192/15189 n5 16121/16121
step 4096: n0 14347/14330 n4 15189/15173 n5 16126/16125
200 turns with timer 2 read after the load's nop and kept: each turn-to-turn count
with how many turns had it:
sw, 0 NOPs, lw, nop, lhu timer 2, run 1: 82 x1 (first at turn 0) 24 x190 (first at turn 1) 30 x4 (first at turn 3) 29 x4 (first at turn 56)
sw, 0 NOPs, lw, nop, lhu timer 2, run 2: 82 x1 (first at turn 0) 24 x191 (first at turn 1) 30 x3 (first at turn 31) 29 x4 (first at turn 52)
sw, 4 NOPs, lw, nop, lhu timer 2, run 1: 85 x1 (first at turn 0) 24 x190 (first at turn 1) 30 x3 (first at turn 20) 29 x5 (first at turn 41)
sw, 4 NOPs, lw, nop, lhu timer 2, run 2: 86 x1 (first at turn 0) 24 x190 (first at turn 1) 29 x6 (first at turn 9) 30 x2 (first at turn 62)
sw, 5 NOPs, lw, nop, lhu timer 2, run 1: 82 x1 (first at turn 0) 24 x190 (first at turn 1) 29 x5 (first at turn 6) 30 x3 (first at turn 27)
sw, 5 NOPs, lw, nop, lhu timer 2, run 2: 82 x1 (first at turn 0) 24 x189 (first at turn 1) 25 x1 (first at turn 4) 29 x6 (first at turn 25) 30 x2 (first at turn 78)
Done.

followup32/03RLT.txt

===== 03 RLT F32 TIMER READ LOOPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer 2 reset at target (mode 0008h, 0208h for sysclock/8) read 1000 times by a loop
from RAM: lhu, k NOPs, sb to the scratchpad; cycles on timer 1 (sysclock), counts.
Timer2 sysclock, target 1, k 0: 10067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 1: 11067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 2: 12070 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 3: 12067 cycles; 0:0 1:1000 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 4: 12067 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 5: 13067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 6: 14073 cycles; 0:666 1:334 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 7: 15067 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 2, k 0: 10067 cycles; 0:500 1:499 2:1 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 1: 11067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 2: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 3: 12067 cycles; 0:0 1:1000 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 4: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 5: 13067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 6: 14067 cycles; 0:500 1:0 2:500 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 7: 15067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 3, k 0: 10067 cycles; 0:1 1:0 2:0 3:999 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 1: 11067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 2: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 3: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 4: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 5: 13067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 6: 14067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 7: 15067 cycles; 0:0 1:1000 2:0 3:0 4:0 5:0 higher:0
Timer2 sysclock, target 10, k 0: 10069 cycles; 0:166 1:0 2:166 3:0 4:166 5:0 6:168 7:0 8:167 9:0 10:167 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 1: 11067 cycles; 0:168 1:84 2:83 3:83 4:83 5:83 6:83 7:83 8:83 9:83 10:84 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 2: 12067 cycles; 0:0 1:1000 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 3: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 4: 12072 cycles; 0:1000 1:0 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 5: 13067 cycles; 0:166 1:83 2:83 3:83 4:83 5:83 6:84 7:84 8:84 9:84 10:83 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 6: 14067 cycles; 0:167 1:0 2:167 3:0 4:167 5:0 6:167 7:0 8:166 9:0 10:166 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 7: 15067 cycles; 0:250 1:0 2:250 3:0 4:0 5:250 6:0 7:0 8:250 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 0: 10067 cycles; 0:125 1:125 2:0 3:125 4:125 5:125 6:125 7:0 8:125 9:125 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 1: 11071 cycles; 0:88 1:100 2:99 3:101 4:100 5:100 6:100 7:101 8:99 9:100 10:12 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 2: 12067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 3: 12067 cycles; 0:50 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:50 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 4: 12067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 5: 13067 cycles; 0:88 1:99 2:100 3:100 4:100 5:100 6:101 7:100 8:100 9:100 10:12 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 6: 14067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 7: 15067 cycles; 0:62 1:125 2:124 3:63 4:125 5:63 6:125 7:126 8:62 9:125 10:0 11:0 12:0 higher:0
Timer 2 sysclock, the write to the first tick on timer 1 (RC7's), 16 tries each:
mode write, cold: 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
mode write, warm: 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
counter write, cold: 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
counter write, warm: 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
Done.

References

  1. ^ SCPH-5501 output: followup32/00RUN.txt

  2. ^ a b c SCPH-5501 output: followup32/03RLT.txt

  3. ^ a b SCPH-5501 output: followup32/01CWN.txt

  4. ^ a b SCPH-5501 output: followup32/02SLP.txt

Categories: Hardware tests