MDEC Output

Measures the MDEC status register, table loads, decode output by CPU and by DMA, DMA block sizes and reset.

This is an old revision of this page, as edited by RemmyLee at 05:40, 23 October 2026. Edit this revision | Latest revision

Overview

The program drives the MDEC with streams taken from the ps1-tests MDEC programs: a single block, a step-by-step stream of four macroblocks, and the first 30 macroblocks of a frame. Each decode records the number of words read, a CRC-32 of the output and the final status, then one row for each block or macroblock. Output of 16 words or fewer is printed whole.¹

The program also writes the control and command registers, loads tables with short and long word counts, reads the data port when it is empty, decodes by DMA0 and DMA1 at several block sizes, and resets the MDEC part way through a decode. The steps that may hang run last, in the separate images mdecout_dbs64, mdecout_dbsback and mdecout_rst.¹

Results

Status Register

The status after reset is 80040000h. Writing the control register with any of bits 0 to 30 changes nothing in the status.²

A command word sets the low 16 bits of the status to its bits 0 to 15, and status bits 23 to 26 to its bits 25 to 28. Command 1E001234h gave status 87841234h, and command 0 after it returned the status to 80040000h.²

Reads of the data port with nothing to read returned 3C101F80h after reset and 3C028010h after a decode. Neither is MDEC output: both are values left on the bus.²

Table Loads

MDEC(2) with bit 0 clear takes 16 words (the luminance table only) and with bit 0 set 32 words. MDEC(3) takes 32 words whatever its bits 0 to 15 hold. The low 16 bits of the status count down from the number of words minus 1 to 0 and then read FFFFh.³ A table load cut short by a word does not end the load: the next word written, even a command, is taken as table data.³

Decoding

The step stream decoded by CPU gave 512 words at 15 bit and 768 at 24 bit. Every repeat of the test gave the same CRC. Written one word at a time with reads between, the stream gave the same 512 words and CRC.⁴⁵ Command bit 25 (bit 15 output) left 4-bit and 8-bit output unchanged, and the status showed it in bit 23.⁶

A decode command whose word count cuts the stream gave fewer words than the stream holds. A count of 33 or 233 left the MDEC waiting for more input.⁷

Decoding by DMA

The decode time is the same for every output depth. For the frame stream it is about 3090 cycles a macroblock.⁸⁹

DMA1 block sizes of 2 to 32 words gave the same output and CRC. With blocks of 1 word or of 64 words DMA1 did not finish, and the wait timed out. A backward DMA1 (CHCR bit 1 set) wrote 512 words below its start address.¹⁰¹¹¹²

Reset

After a reset by control bit 31 part way through a decode, the status read 26000000h. The tables loaded earlier were kept, and the next decode gave the same output as before the reset. A reset during DMA0 and DMA1 left both channels busy, and DMA1 had written 96 words.¹³¹⁴

Runs

27 September 2026 card-b

Raw output: s019/00RUN.txt · s019/01REG.txt · s019/02TBL.txt · s019/03QTE.txt · s019/04IQY.txt · s019/05S15.txt · s019/06S24.txt · s019/07S84.txt · s019/08FRC.txt · s019/09F24.txt · s019/10ODD.txt · s019/11EAR.txt · s019/12BLK.txt · s019/13SDM.txt · s019/14FDM.txt · s020/15DBS.txt · s020/16RST.txt

27 September 2026 card-g

Raw output: 00RUN.txt · 01REG.txt · 02TBL.txt · 03QTE.txt · 04IQY.txt · 05S15.txt · 06S24.txt · 07S84.txt · 08FRC.txt · 09F24.txt · 10ODD.txt · 11EAR.txt · 12BLK.txt · 13SDM.txt · 14FDM.txt · 15DBS.txt · 16RST.txt

27 September 2026 card-g3

Raw output: 00RUN.txt · 01REG.txt · 02TBL.txt · 03QTE.txt · 04IQY.txt · 05S15.txt · 06S24.txt · 07S84.txt · 08FRC.txt · 09F24.txt · 10ODD.txt · 11EAR.txt · 12BLK.txt · 13SDM.txt · 14FDM.txt · 15DBS.txt · 16RST.txt

28 September 2026 card-h

Raw output: 00RUN.txt · 01REG.txt · 02TBL.txt · 03QTE.txt · 04IQY.txt · 05S15.txt · 06S24.txt · 07S84.txt · 08FRC.txt · 09F24.txt · 10ODD.txt · 11EAR.txt · 12BLK.txt · 13SDM.txt · 14FDM.txt · 15DBS.txt · 16RST.txt

28 September 2026 card-h mdecout_dbs64

Raw output: 00RUN.txt · 01DBS.txt

00RUN.txt:

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BB0 PRId 00000002

01DBS.txt:

===== 01 DBS MDEC DMA BLOCK SIZES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Step stream, 15 bit unsigned. Per case: whole CRC, then per 16x16 macroblock.
15 bit unsigned by DMA, DMA1 blocks of 64: TIMED OUT, 6768 cycles, CRC 783C8D2D, status 6E01001F
  CHCR0 01000201 CHCR1 00000200 MADR1 000307B8 BCR1 00000040
mb  0 crc AF06B5CB first 00000000 last 00007BDE
mb  1 crc 6DAFE596 first 00007FFF last 04212108
mb  2 crc 7492A9D5 first 00000000 last 08420000
mb  3 crc F7583393 first 7FFF0000 last 04210000
DMA1 backward: not run in this table.
Done.

28 September 2026 card-h mdecout_dbsback

Raw output: 00RUN.txt · 01DBS.txt

00RUN.txt:

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 8001E528 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8001F094 PRId 00000002

01DBS.txt:

===== 01 DBS MDEC DMA BLOCK SIZES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Step stream, 15 bit unsigned. Per case: whole CRC, then per 16x16 macroblock.
DMA1 blocks of 64: not run in this table.
DMA1 backward from word 1023: done, status 8604FFFF, MADR1 001207B4
  words of the 6464 word buffer changed 512; lowest and highest changed: 512 1023
mb  0 crc 9196A7DC first 7FFC7FFC last 17FF17FF
mb  1 crc 4FCB150A first 68996899 last 145B145B
mb  2 crc 67823B26 first 04210000 last 00000000
mb  3 crc D8058DD0 first 04212108 last 00000000
Done.

28 September 2026 card-h mdecout_rst

Raw output: 00RUN.txt · 01RST.txt

00RUN.txt:

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8010F094 PRId 00000002

01RST.txt:

===== 01 RST MDEC RESET MID | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA both ways, reset after DMA1 BCR 000D0020 (DMA0 BCR 00040020): status E6030062, later 80040000
  later: CHCR0 01000201 BCR0 00040020 MADR0 00010CD0; CHCR1 01000200 BCR1 000D0020 MADR1 000300C0
  words DMA1 wrote: 96, CRC of the first 96: 1E01317C
Step stream by CPU after it: 512 words, CRC 01471D2F, status 8604FFFF
Done.

References