Bus Access and Device Register Timing

Measures COM0 recovery on BIOS ROM loads, loads and stores around RAM writes, word stores to SPU registers, DMA start, MDEC control writes after a reset, root counter 0 after an hblank reset and KSEG1 stores to the scratchpad.

Overview

The program times short code sequences on root counter 2, which counts system clock cycles and is read with loads. Each sequence is timed three times, and most run once beforehand to warm the instruction cache. A loop of 100 turns closes each turn with ADDIU, BNEZ and a NOP. The groups that write the memory control registers or I_MASK, the SPU or DPCR put back the values they found. KSS ran as a separate program named followup24r in the same run as the other groups.¹²

See also:

• Memory Control and Bus Timing
• SPU 32-bit Stores
• DMA Timing
• Load Landing and Device Loads

Results

COM0 Recovery

COM0 is the recovery period in COM_DELAY, and a region uses it when bit 8 of its delay register is set (Memory Control). With COM0 at 15 a single BIOS byte load took the same 23 cycles as with COM0 at 0. A load followed by 4 NOPs, or by a use of its value, also took the same time at both settings.¹

The recovery time therefore falls on an access that follows another one closely. A second load straight after the first cost 10 to 13 cycles more at COM0 15, and 11 more with 4 NOPs between them. With 16 NOPs between them it cost 2 more. Four loads in a row took 36 cycles more, which is 12 for each load after the first. In 100 turns of one load the extra 990 cycles come to 10 for each of the 99 loads that follow another.¹

Loads After a RAM Store

An I_STAT load and a NOP took 716 to 733 cycles over 100 turns. A RAM store just before the load raised the row to 952 to 959 cycles, which is 236 to 243 more. With one NOP between the store and the load the row took 961 to 965 cycles, so that NOP ran in time the load spent waiting. From 2 NOPs on each further NOP added about 100 cycles, which is its own time.³

A RAM store after the I_STAT load in place of its NOP cost about 130 cycles when nothing came before the load and about 390 when a RAM store came before it. A RAM store before a BIOS ROM load added 196 to 201 cycles to the 2,934 of the load alone.³

Word Stores to SPU Registers

A word store to an SPU reverb register pair wrote the high halfword every time: 9ABCh read back from the upper register after 32 of 32 stores at every pair. The low halfword DEF0h read back after 28 of 32 stores for the pairs from 1DC0h to 1DE4h and after 29 of 32 for the pairs from 1DE8h to 1DFCh. The read after a short pause gave the same count as the read at once, so a low halfword that was lost stayed lost.⁴

DMA Start

For every size a timer read straight after the CHCR store read 4 cycles whether the channel was enabled or disabled. With 4 NOPs between the store and the read, the count was 7 with the channel disabled. With it enabled the count was 13, 16 and 28 for 1, 4 and 16 words, for DMA6 and for DMA0 alike. The transfer therefore held the CPU for 5 cycles and one more for each word, and the read straight after the store finished before the transfer took the bus. In three DMA6 rows the first sample with the channel enabled was larger than the other two, up to 28 cycles, and the table gives the later samples.⁵

Access on a Load's Landing Cycle

The distance of the store from the loaded word made no difference. At each number of NOPs the four distances gave times within 30 cycles over 100 turns. From 4 to 6 NOPs the row took 1,442 to 1,472 cycles, and with 8 NOPs it took 1,632 to 1,641.⁶

Stores in a Load Delay Slot

A store in the delay slot of a RAM load that follows a RAM store took the same time wherever the store went. GP0, the scratchpad, I_MASK and an SPU register all gave 1,631 to 1,641 cycles over 100 turns. When the store before the load went to the scratchpad instead of RAM, the same turn took 1,136 to 1,147 cycles, which is about 500 less.⁷

After two RAM loads a RAM store took 1,877 cycles. With a NOP before the store the turn took 2,099 to 2,104 cycles instead. In the sequence of load, store, load and store, a NOP after the first store made the turn about 130 cycles faster. A NOP after the second load made it about 166 cycles slower.⁷

MDEC Control Write After a Reset

With 0 or 1 NOP between the reset and the control write, the status read 40000000h after the table command. With 2 or 3 NOPs it read 80040000h, the value the MDEC Output test reads straight after a reset. With 4 NOPs it read A004000Fh: the MDEC was busy and waited for 16 more words, so it had taken the table command. Bit 28, the data-in request, was clear in every row, and each value was the same in all three runs.⁸

Root Counter 0 After an Hblank Reset

Free running, root counter 0 counted 809 to 810 dots in the 2,000 cycles after root counter 1's tick, which is about 100 dots each 250 cycles. In sync mode 1, which resets the counter at hblank, it read 0 to 4 dots 500 cycles after the tick and then rose at the same rate to 596 to 601 at 2,000 cycles. At 0 and 250 cycles it read 333 to 580 dots, so the reset came between 250 and 500 cycles after the tick.⁹

KSEG1 Stores to the Scratchpad

Halfword and byte stores to BF800100h and word stores to BF800000h and BF8003FCh raised no exception. None of them reached the scratchpad, and the word read back at its 1F80xxxxh address still held 5C4A0001h.²

Runs

5 October 2026

followup24/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
8 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8010B680 PRId 00000002

followup24/01CMF.txt

===== 01 CMF F24 COM0 FIRST OR LAST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
COM_DELAY 00031125, BIOS delay 0013253F (bit 8 set); each row three times at COM0 0, then 15
(row 98: which access in a measurement does not pay COM0).
nothing: 33 15 15 / 15 15 15
1 lbu: 28 23 23 / 23 23 23
2 lbu: 46 34 32 / 44 44 44
4 lbu: 65 50 50 / 86 86 86
lbu, 4 nops: 45 23 23 / 23 23 23
lbu, 16 nops: 63 51 51 / 51 51 51
lbu, use: 37 37 37 / 37 37 37
lbu, lbu: 55 36 36 / 49 49 49
lbu, 4 nops, lbu: 42 33 33 / 44 44 44
lbu, 16 nops, lbu: 75 42 42 / 44 44 44
100 turns of lbu (07CMA): 1139 1119 1119 / 2109 2111 2109
Done.

followup24/02SIO.txt

===== 02 SIO F24 IO LOAD AFTER RAM SW | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns, cached, three times each (row 99: how long an IO load waits behind a RAM write).
RAM sw, I_STAT lw, nop: 952 958 959
RAM sw, nop, I_STAT lw, nop: 965 964 961
RAM sw, 2 nops, I_STAT lw, nop: 1065 1064 1067
RAM sw, 4 nops, I_STAT lw, nop: 1262 1260 1251
RAM sw, 8 nops, I_STAT lw, nop: 1659 1659 1659
RAM sw, I_STAT lw, RAM sw: 1342 1345 1345
RAM sw, nop, I_STAT lw, RAM sw: 1352 1369 1363
RAM sw, 4 nops, I_STAT lw, RAM sw: 1333 1356 1351
I_STAT lw, nop: 733 716 716
I_STAT lw, RAM sw: 854 852 860
RAM sw, BIOS lw, nop: 3135 3130 3130
RAM sw, 4 nops, BIOS lw, nop: 3348 3343 3343
RAM sw, BIOS lw, RAM sw: 3556 3542 3547
BIOS lw, nop: 2934 2934 2934
Done.

followup24/03SPW.txt

===== 03 SPW F24 SPU 32 BIT STORE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
32 sw of 9ABCDEF0h to each pair, the low half's landings at once and a pause on, the
high half's (row 100):
1DC0: low 28 at once, 28 later; high 32 of 32
1DC4: low 28 at once, 28 later; high 32 of 32
1DC8: low 28 at once, 28 later; high 32 of 32
1DCC: low 28 at once, 28 later; high 32 of 32
1DD0: low 28 at once, 28 later; high 32 of 32
1DD4: low 28 at once, 28 later; high 32 of 32
1DD8: low 28 at once, 28 later; high 32 of 32
1DDC: low 28 at once, 28 later; high 32 of 32
1DE0: low 28 at once, 28 later; high 32 of 32
1DE4: low 28 at once, 28 later; high 32 of 32
1DE8: low 29 at once, 29 later; high 32 of 32
1DEC: low 29 at once, 29 later; high 32 of 32
1DF0: low 29 at once, 29 later; high 32 of 32
1DF4: low 29 at once, 29 later; high 32 of 32
1DF8: low 29 at once, 29 later; high 32 of 32
1DFC: low 29 at once, 29 later; high 32 of 32
Done.

followup24/04DST.txt

===== 04 DST F24 DMA START | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Clocks from a CHCR store to a timer read straight after it (k 0) or 4 NOPs on (k 4), the
channel enabled / disabled in DPCR, three times each (row 101):
OTC  1 words, k 0: 7/4 4/4 4/4
OTC  1 words, k 4: 28/7 13/7 13/7
OTC  4 words, k 0: 4/4 4/4 4/4
OTC  4 words, k 4: 26/7 16/7 16/7
OTC 16 words, k 0: 4/4 4/4 4/4
OTC 16 words, k 4: 28/7 28/7 28/7
DMA0 one block of  1 words, k 0: 4/4 4/4 4/4
DMA0 one block of  1 words, k 4: 13/7 13/7 13/7
DMA0 one block of  4 words, k 0: 4/4 4/4 4/4
DMA0 one block of  4 words, k 4: 16/7 16/7 16/7
DMA0 one block of 16 words, k 0: 4/4 4/4 4/4
DMA0 one block of 16 words, k 4: 28/7 28/7 28/7
Done.

followup24/05LNP.txt

===== 05 LNP F24 LANDING BY PLACE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of lw, p NOPs (4, 5, 6, 8), the access, a NOP (row 102), three times each:
RAM sw the same word: 1442 1455 1445 1453 1455 1451 1466 1466 1471 1635 1632 1632
RAM sw 128 bytes on: 1451 1455 1451 1449 1443 1455 1472 1471 1463 1632 1632 1632
RAM sw 4 KB on: 1446 1458 1453 1451 1447 1449 1459 1469 1465 1641 1632 1632
RAM sw 64 KB on: 1446 1458 1453 1451 1447 1449 1459 1469 1465 1641 1632 1632
BIOS lw: 3682 3654 3661 3644 3654 3661 3725 3724 3729 3927 3923 3926
Done.

followup24/06SLX.txt

===== 06 SLX F24 STORE IN A LOAD SLOT | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns each, three times (row 103):
RAM sw, lw, GP0 sw: 1631 1633 1639
RAM sw, lw, scratchpad sw: 1641 1631 1641
RAM sw, lw, I_MASK sw: 1635 1640 1641
RAM sw, lw, SPU 1DC0h sh: 1632 1636 1634
lw, nop: 936 944 945
lw, GP0 sw: 1055 1046 1061
scratchpad sw, lw, GP0 sw: 1136 1147 1147
scratchpad sw, lw, scratchpad sw: 1143 1136 1143
RAM lw, lw, RAM sw: 1877 1877 1877
RAM lw, lw, nop, RAM sw: 2099 2104 2099
RAM lw, lw, GP0 sw: 1655 1653 1653
I_STAT lw, lw, RAM sw: 1257 1268 1265
lw, sw, lw, sw (SLD): 2624 2623 2626
lw, sw, nop, lw, sw: 2498 2489 2497
lw, sw, lw, nop, sw: 2790 2790 2792
lw, sw next word, lw, sw next word: 2585 2595 2595
lw, sw, lw into $13, sw: 2467 2474 2474
Done.

followup24/07MRH.txt

===== 07 MRH F24 MDEC RESET HOLD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
80000000h, k NOPs, 60000000h to MDEC1, a table command, MDEC1 bit 28 (row 104), warm:
k 0: 40000000 40000000 40000000
k 1: 40000000 40000000 40000000
k 2: 80040000 80040000 80040000
k 3: 80040000 80040000 80040000
k 4: A004000F A004000F A004000F
Done.

followup24/08T0D.txt

===== 08 T0D F24 T0 DOTS AFTER HBLANK RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Dots on Timer0 k cycles after Timer1's hblank tick: reset at hblank (0103h) | free
difference (0100h), min-max of 16 (row 106):
 k    0: 393-580 | 15-16
 k  250: 333-414 | 116-116
 k  500: 0-4 | 211-212
 k  750: 99-103 | 312-313
 k 1000: 200-203 | 412-413
 k 1250: 296-300 | 508-509
 k 1500: 396-400 | 608-609
 k 1750: 497-500 | 708-709
 k 2000: 596-601 | 809-810
Done.

followup24r/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001CD28 PRId 00000002

followup24r/01KSS.txt

===== 01 KSS F24 KSEG1 SCRATCHPAD STORES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Stores to the scratchpad through KSEG1 over 5C4A0001h (row 105):
sh BF800100: exception no 0, word now 5C4A0001
sb BF800100: exception no 0, word now 5C4A0001
sw BF800000: exception no 0, word now 5C4A0001
sw BF8003FC: exception no 0, word now 5C4A0001
Done.

References