CPU Stores and Device Delays

Measures RAM store bursts, loads that land on a following instruction and uncached code alone and during a DMA2 list, with timer 1 toggle mode, SIO1 CTRL bit 7 and the COM0 and COM3 delay fields.

Overview

Each CPU row of the first program runs a loop of 100 turns from the instruction cache, or from KSEG1 where the row says so. Root counter 2 times the loop, and the program reads the counter with loads only. Every row runs once alone and once straight after DMA2 starts a list of 1024 empty nodes, and the pair is repeated. The output also gives the count at which the list was seen to end.¹

The CPU groups store 1 to 12 words back to back, place one instruction on the cycle a RAM load's data lands, follow a backward branch with a RAM load, and run a store, a load and a store with NOPs between them. A fifth group runs stores, branches and loads from KSEG1. Two further groups read registers. TTG writes mode 00D8h to root counter 1 with a target of 0 and reads I_STAT bit 5 and the mode back, and SRG writes CTRL bit 7 of SIO1 under four MODE values with nothing attached to the port.¹

The second program changes the memory control registers and puts each one back before it prints. COM times 100 SPU KOFF halfword stores and 100 POST byte stores (1F802041h) under COM0 values of 0, 3, 9 and 15. BRD reads four BIOS words with the BIOS read delay set to 1, then times 100 byte loads of 1F801800h with the CD-ROM read delay at 0 to 4 and bit 11 set, under COM3 values of 0, 3, 6 and 9.²

See also:

• RAM Access During a DMA2 List
• CPU Access Types During a DMA2 List
• Load and Use During a DMA2 List
• Memory Control and Bus Timing

Results

Store Bursts

Alone, the second and third store in a turn each added about 115 cycles over 100 turns, and each store from the fourth on added 200 to 215. During the list each store added 1,316 to 1,335 cycles, which is about 13 cycles a store. The list also took longer as the stores grew: it ended at 10,843 cycles with one store a turn and at 13,541 with ten. Each store therefore delayed the end of the list by about 300 cycles. With 11 and 12 stores the list ended before the loop did.¹

Instruction on the Landing Cycle

After a RAM load and 5 NOPs, an ADDU, SLL, LUI or MULT on the landing cycle took 1,447 to 1,457 cycles alone. A taken forward BEQ took 100 cycles more. During the list these rows took 1,591 to 1,653 cycles, but a store took 2,671 and a second load 2,551. Each further NOP before the instruction added 100 cycles alone, and during the list the ALU rows rose from about 1,595 at 5 NOPs to about 1,740 at 7.¹

Loads After a Backward Branch

An inner loop of two turns with k instructions before a backward BNE, followed by a RAM load and 2 NOPs, took 1,559, 1,753 and 1,953 cycles alone for k 1, 2 and 3. During the list it took 1,638, 1,820 and 1,998 cycles, so the list cost 45 to 80 cycles over the 100 turns.¹

Store Load Store

A RAM store, a load of another word and a second store took 1,891 cycles alone with no NOPs between them and 2,064 to 2,077 with 1 to 4 NOPs. During the list the row took 3,928 to 3,933 cycles at every gap.¹

Uncached Code

KSEG1 is not cached, so these rows fetch every instruction over the bus. A load followed by one NOP took 3,648 cycles alone and a load followed by two took 4,255. Each uncached instruction therefore cost about 6 cycles a turn. During the list the same NOP added 1,219 cycles, which is about 12 a turn. A store followed by a jump to the next word took the same time as a store followed by 2 NOPs: 4,357 cycles alone and 9,037 during the list. In the rows with two stores and a taken branch and in the row of three stores the list ended before the loop.¹

Root Counter 1 Mode 00D8h

The program acknowledges I_STAT bit 5 before each mode write. Read at once after the write, I_STAT bit 5 was 1 and the mode read 08D8h. Read 1,000, 2,000 and 3,000 cycles after the write, I_STAT bit 5 was 0 and the mode read 0CD8h, so mode bit 10 had changed from 0 to 1.¹

SIO1 CTRL Bit 7

CTRL bit 7 read back as 1 under MODE 004Eh, 000Dh and 00CEh, and read 0 under MODE 0000h. After a reset, SIO1 STAT read 00000185h five times in a row.¹

COM0 Delay

COM_DELAY held 00031125h as found. The time of 100 SPU stores and of 100 POST stores rose with COM0, and the two were equal except at COM0 0. From COM0 3 to 15 each step of COM0 added 98 cycles over the 100 stores, which is about one cycle a store.²

BIOS and CD-ROM Read Delays

The BIOS delay register held 0013243Fh and the CD-ROM delay register 00020843h as found. With the BIOS read delay set to 1, all four BIOS words read back with FFh in the low byte, and so did the halfword at offset 2 of each. The word at BFC00100h read 951204FFh.²

With CD-ROM delay bit 11 set, COM3 set a floor under the time of a CD-ROM byte load. Under COM3 0 the read delay raised the time from 953 cycles at delay 0 to 1,245 at delay 4. Under COM3 3 delays 0 to 3 all took 1,145 cycles, and under COM3 9 every delay took 1,745.²

Runs

2 October 2026

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
7 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8001C8B4 PRId 00000002

01NSW.txt

02LND.txt

03BBR.txt

===== 03 BBR F10 BACK BRANCH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of a two-turn inner loop (k instructions, a backward bne, its delay slot), then a
RAM lw and 2 NOPs, k 1 to 3, alone and during a list of 1024 empty nodes (row 26).
k 1: alone 1559, during 1638, list done at 10737; alone 1546, during 1639, list done at 10729;
k 2: alone 1753, during 1820, list done at 10739; alone 1746, during 1810, list done at 10732;
k 3: alone 1953, during 1998, list done at 10752; alone 1946, during 2000, list done at 10748;
Done.

04SLS.txt

===== 04 SLS F10 SW LW SW | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of a RAM sw, k NOPs, a RAM lw of another word, k NOPs, a RAM sw, alone and
during a list of 1024 empty nodes (row 30).
k 0: alone 1891, during 3932, list done at 11338; alone 1883, during 3933, list done at 11328;
k 1: alone 2071, during 3930, list done at 11334; alone 2071, during 3932, list done at 11328;
k 2: alone 2077, during 3933, list done at 11326; alone 2068, during 3928, list done at 11317;
k 3: alone 2070, during 3929, list done at 11333; alone 2064, during 3930, list done at 11325;
k 4: alone 2071, during 3930, list done at 11338; alone 2070, during 3928, list done at 11317;
Done.

05KST.txt

===== 05 KST F10 KSEG1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns from KSEG1 (no cache), alone and during a list of 1024 empty nodes: stores, a
store and a jump, a taken branch after stores, loads and uses (rows 16, 27, 33, 41).
sw, j to the next, nop: alone 4357, during 9037, list done at 12096; alone 4408, during 9029, list done at 12085;
sw, 2 NOPs: alone 4357, during 9037, list done at 12096; alone 4408, during 9029, list done at 12085;
sw, sw, 0 NOPs, taken beq: alone 5804, during 12744 (list ended first), list done at 12854; alone 5803, during 12743 (list ended first), list done at 12835;
sw, sw, 1 NOPs, taken beq: alone 6445, during 13287 (list ended first), list done at 13397; alone 6433, during 13300 (list ended first), list done at 13387;
sw, sw, 2 NOPs, taken beq: alone 7018, during 13840 (list ended first), list done at 13950; alone 7011, during 13845 (list ended first), list done at 13932;
sw, sw, 3 NOPs, taken beq: alone 7634, during 14412 (list ended first), list done at 14526; alone 7622, during 14428 (list ended first), list done at 14520;
sw, sw, 4 NOPs, taken beq: alone 8233, during 14985 (list ended first), list done at 15095; alone 8221, during 15009 (list ended first), list done at 15096;
RAM lw, nop: alone 3648, during 7722, list done at 11755; alone 3643, during 7729, list done at 11760;
RAM lw, nop, nop: alone 4255, during 8941, list done at 11954; alone 4248, during 8940, list done at 11934;
RAM lw, nop, use: alone 4453, during 8940, list done at 11948; alone 4452, during 8942, list done at 11941;
I_STAT lw, nop: alone 3233, during 7515, list done at 11546; alone 3226, during 7516, list done at 11538;
I_STAT lw, nop, nop: alone 3846, during 8748, list done at 11759; alone 3838, during 8751, list done at 11747;
I_STAT lw, nop, use: alone 4135, during 8747, list done at 11757; alone 4123, during 8751, list done at 11752;
three sw, 4 NOPs: alone 7502, during 14477 (list ended first), list done at 14587; alone 7502, during 14476 (list ended first), list done at 14563;
Done.

06TTG.txt

===== 06 TTG F10 TIMER 00D8 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer 1 with target 0 in mode 00D8h (reset at target, IRQ at target, toggle, repeat):
I_STAT bit 5 and the mode as read, 0 to 3 times 1000 cycles after the mode write (row 37).
wait 0: I_STAT bit 5 1, mode 08D8
wait 1: I_STAT bit 5 0, mode 0CD8
wait 2: I_STAT bit 5 0, mode 0CD8
wait 3: I_STAT bit 5 0, mode 0CD8
Done.

07SRG.txt

===== 07 SRG F10 SIO1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
SIO1: CTRL bit 7 written under four MODE values and read back; STAT read five times
after a reset (row 39). Nothing is attached to the serial port.
MODE 004E: CTRL reads 0080
MODE 0000: CTRL reads 0000
MODE 000D: CTRL reads 0080
MODE 00CE: CTRL reads 0080
STAT after a reset: 00000185 00000185 00000185 00000185 00000185
Done.

2 October 2026 (followup10r)

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
2 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 8001BD48 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8001C8B4 PRId 00000002

01COM.txt

===== 01 COM F10R COM0 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of an SPU KOFF sh and of a POST (1F802041h) sb under COM_DELAY COM0 0, 3, 9
and 15, the rest of COM_DELAY as found; cycles by timer 2 (row 42).
COM_DELAY as found 00031125
COM0  0: SPU sh 1223, POST sb 1216
COM0  3: SPU sh 1412, POST sb 1412
COM0  9: SPU sh 2000, POST sb 2000
COM0 15: SPU sh 2588, POST sb 2588
Done.

02BRD.txt

===== 02 BRD F10R READ DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
BIOS lw and lhu of four words at read delay 1; CD-ROM lbu of 1F801800h (100 turns)
at read delay 0 to 4 with bit 11 set under COM3 0, 3, 6, 9 (row 43).
BIOS delay as found 0013243F, CD-ROM 00020843, COM 00031125
BIOS BFC00000 at read delay 1: lw 180013FF, lhu at +2 3CFF
BIOS BFC00100 at read delay 1: lw 951204FF, lhu at +2 9DFF
BIOS BFC10000 at read delay 1: lw 180000FF, lhu at +2 3CFF
BIOS BFC7FF00 at read delay 1: lw 000000FF, lhu at +2 00FF
COM3 0, CD-ROM lbu at read delay 0-4: 953 946 1045 1145 1245
COM3 3, CD-ROM lbu at read delay 0-4: 1145 1145 1145 1145 1245
COM3 6, CD-ROM lbu at read delay 0-4: 1445 1445 1451 1445 1445
COM3 9, CD-ROM lbu at read delay 0-4: 1745 1745 1745 1745 1745
Done.

References