I/O Access Width
Writes 12345678h to memory and I/O registers as a byte, halfword and word and reads back what arrived.
| Machine | SCPH-5501 |
|---|---|
| Program | cpu/io-access-bitwidth (ps1-tests) |
Overview
For each address the program clears the location at the read width, then stores the CPU register value 12345678h with SB, SH and SW in turn and reads the location back. It repeats the table three times, reading back as a word, a halfword and a byte. The old value is put back after each row.1
The stores use the plain SB, SH and SW instructions. JOY_CTRL, SIO_CTRL and SPUCNT are not word aligned, so a word store there raises an address error. The program prints "--CRASH--" when the store raised an exception. Its own word reads of those three registers use an LWL and LWR pair, so they include the bytes of the next register.1
Results
RAM and the scratchpad keep exactly the bytes written: a byte store leaves 78h and a halfword store 5678h. The BIOS ROM ignores all stores and reads 3C080013h.2
The DMA and timer registers take the whole 32-bit CPU register from a byte or halfword store. A byte store of 12345678h to DMA control (1F8010F0h) read back 12345678h, and timer 0's target read 5678h after a byte store. DMA channel 0's address register kept 345678h from every width, so it holds 24 bits.2
| Register | Address | SB | SH | SW |
|---|---|---|---|---|
| RAM | 80080000h | 00000078h | 00005678h | 12345678h |
| BIOS ROM | BFC00000h | 3C080013h | 3C080013h | 3C080013h |
| Scratchpad | 1F800000h | 00000078h | 00005678h | 12345678h |
| Expansion 2 | 1F802000h | FFFFFFFFh | FFFFFFFFh | FFFFFFFFh |
| Expansion 3 | 1FA00000h | FFFFFFFFh | FFFFFFFFh | FFFFFFF7h |
| DMA0 MADR | 1F801080h | 00345678h | 00345678h | 00345678h |
| DPCR | 1F8010F0h | 12345678h | 12345678h | 12345678h |
| DICR | 1F8010F4h | 00340038h | 00340038h | 00340038h |
| JOY_MODE | 1F801048h | 38h | 38h | 38h |
| JOY_CTRL | 1F80104Ah | 0 | 0 | address error |
| SIO_MODE | 1F801058h | 78h | 78h | 78h |
| SIO_CTRL | 1F80105Ah | C0C00000h | C0C00000h | address error |
| CD-ROM status | 1F801800h | 18181818h | 1A1A1A1Ah | 1A1A1A1Ah |
| GPUSTAT | 1F801814h | 14802000h | 14802000h | 14802000h |
| MDEC status | 1F801824h | 80040000h | 80040000h | 80040000h |
| SPUCNT | 1F801DAAh | 5678h | 5678h | address error |
I_MASK at 1F801074h and timer 0's target at 1F801108h kept only their low bits: 678h for I_MASK and 5678h for the target. Their upper halves read back a different value in each run, among them 14A2h, A085h, 0200h, 0C00h and 1F80h, so those bits are not storage.2
The CD-ROM status port reads the same byte in all four positions of a word. A byte store left 18h and a halfword or word store left 1Ah. GPUSTAT and the MDEC status do not change from any store.2
Read back as a halfword or a byte, each register gave the low part of the word values above. MDEC status read 0 at those widths, and GPUSTAT read 0 as a byte.2
Runs
25 September 2026
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0x14a20678 0xa0850678 0x678
T0_TARGET (0x1f801108) 0x1f805678 0x1f805678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0x80040000 0x80040000 0x80040000
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
27 September 2026
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0x2000678 0x2000678 0x1f800678
T0_TARGET (0x1f801108) 0x1f805678 0x2005678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0xa0041bfc 0xa0041bfc 0xa0041bfc
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
27 September 2026 run 2
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0x2000678 0x2000678 0x1f800678
T0_TARGET (0x1f801108) 0x1f805678 0x2005678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0x80040000 0x80040000 0x80040000
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
27 September 2026 run 3
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0x2000678 0x2000678 0x1f800678
T0_TARGET (0x1f801108) 0x1f805678 0x2005678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0x80040000 0x80040000 0x80040000
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
27 September 2026 run 4
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0xc000678 0xc000678 0x1f800678
T0_TARGET (0x1f801108) 0x1f805678 0xc005678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0x80040000 0x80040000 0x80040000
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
28 September 2026
===== 03 IOB IO BITWIDTH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
cpu/io-access-bitwidth
Test how writes with different bitwidths behaves for different io devices
Note: Disable "Exception Handling Surveillance" in Caetla first"
Reading as 32bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit 32bit
RAM (0x80080000) 0x78 0x5678 0x12345678
BIOS (0xbfc00000) 0x3c080013 0x3c080013 0x3c080013
SCRATCHPAD (0x1f800000) 0x78 0x5678 0x12345678
EXPANSION2 (0x1f802000) 0xffffffff 0xffffffff 0xffffffff
EXPANSION3 (0x1fa00000) 0xffffffff 0xffffffff 0xfffffff7
DMA0_ADDR (0x1f801080) 0x345678 0x345678 0x345678
DMAC_CTRL (0x1f8010f0) 0x12345678 0x12345678 0x12345678
DMAC_INTR (0x1f8010f4) 0x340038 0x340038 0x340038
JOY_MODE (0x1f801048) 0x38 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0 --CRASH--
SIO_MODE (0x1f801058) 0x78 0x78 0x78
SIO_CTRL (0x1f80105a) 0xc0c00000 0xc0c00000 --CRASH--
I_MASK (0x1f801074) 0xc000678 0xc000678 0x1f800678
T0_TARGET (0x1f801108) 0x1f805678 0xc005678 0x1f805678
CDROM_STAT (0x1f801800) 0x18181818 0x1a1a1a1a 0x1a1a1a1a
GPUSTAT (0x1f801814) 0x14802000 0x14802000 0x14802000
MDECSTAT (0x1f801824) 0x80040000 0x80040000 0x80040000
SPUCNT (0x1f801daa) 0x5678 0x5678 --CRASH--
Reading as 16bit, writing as:
SEGMENT ( ADDRESS) 8bit 16bit
RAM (0x80080000) 0x78 0x5678
BIOS (0xbfc00000) 0x13 0x13
SCRATCHPAD (0x1f800000) 0x78 0x5678
EXPANSION2 (0x1f802000) 0xffff 0xffff
EXPANSION3 (0x1fa00000) 0xffff 0xffff
DMA0_ADDR (0x1f801080) 0x5678 0x5678
DMAC_CTRL (0x1f8010f0) 0x5678 0x5678
DMAC_INTR (0x1f8010f4) 0x38 0x38
JOY_MODE (0x1f801048) 0x38 0x38
JOY_CTRL (0x1f80104a) 0 0
SIO_MODE (0x1f801058) 0x78 0x78
SIO_CTRL (0x1f80105a) 0 0
I_MASK (0x1f801074) 0x678 0x678
T0_TARGET (0x1f801108) 0x5678 0x5678
CDROM_STAT (0x1f801800) 0x1818 0x1a1a
GPUSTAT (0x1f801814) 0x2000 0x2000
MDECSTAT (0x1f801824) 0 0
SPUCNT (0x1f801daa) 0x5678 0x5678
Reading as 8bit, writing as:
SEGMENT ( ADDRESS) 8bit
RAM (0x80080000) 0x78
BIOS (0xbfc00000) 0x13
SCRATCHPAD (0x1f800000) 0x78
EXPANSION2 (0x1f802000) 0xff
EXPANSION3 (0x1fa00000) 0xff
DMA0_ADDR (0x1f801080) 0x78
DMAC_CTRL (0x1f8010f0) 0x78
DMAC_INTR (0x1f8010f4) 0x38
JOY_MODE (0x1f801048) 0x38
JOY_CTRL (0x1f80104a) 0
SIO_MODE (0x1f801058) 0x78
SIO_CTRL (0x1f80105a) 0
I_MASK (0x1f801074) 0x78
T0_TARGET (0x1f801108) 0x78
CDROM_STAT (0x1f801800) 0x18
GPUSTAT (0x1f801814) 0
MDECSTAT (0x1f801824) 0
SPUCNT (0x1f801daa) 0x78
Done.
References
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^ a b ps1-tests, cpu/io-access-bitwidth. https://github.com/JaCzekanski/ps1-tests.
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^ a b c d e SCPH-5501 output: main/03IOB.txt and the files beside it, with the other runs listed under Runs.
Categories: Hardware tests