DMA Master Enable: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ## Results | ## Results | ||
| − | With the enable bit set (DPCR 333D3B33h) the read completed and the data matched. With the enable bit clear the transfer never ran, at priority 5 (33353B33h) and at priority 0 (33303B33h); both reads timed out.[^run] | + | With the enable bit set (DPCR 333D3B33h) the read completed and the data matched. With the enable bit clear the transfer never ran, at priority 5 (33353B33h) and at priority 0 (33303B33h); both reads timed out.[^run] DPCR read 333B3B33h before each change in all four runs.[^run] |
| − | DPCR read 333B3B33h before each change in all four runs.[^run] | ||
| − | |||
| ## Runs | ## Runs | ||