DMA Master Enable

Checks that an SPU DMA transfer runs only when its enable bit in DPCR is set.

This is an old revision of this page, as edited by RemmyLee at 05:11, 23 October 2026. Edit this revision | Latest revision

Overview

The program writes a test string to sound RAM, then reads it back by DMA channel 4 three times. Before each read it changes channel 4's field in DPCR (bits 16 to 19): enable set with priority 5, enable clear with priority 5, and enable clear with priority 0. Each read waits a fixed time and reports whether the transfer completed.¹

Results

With the enable bit set (DPCR 333D3B33h) the read completed and the data matched. With the enable bit clear the transfer never ran, at priority 5 (33353B33h) and at priority 0 (33303B33h); both reads timed out.²

DPCR read 333B3B33h before each change in all four runs.²

Runs

25 September 2026

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

27 September 2026

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

27 September 2026 run 2

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

27 September 2026 run 3

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

27 September 2026 run 4

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

28 September 2026

05DPC.txt

===== 05 DPC DMA DPCR | BIOS 19951204 System ROM Version 3.0 11/18/96 A

dma/dpcr
Tests DMA transfer behaviour with various DPCR values.

pass - writeToSPURAM
Testing DMA read with master enable = true, priority = 5
  DPCR was 0x333B3B33, setting to 0x333D3B33
  ... transfer complete
pass - testSPUDMARead
Testing DMA read with master enable = false, priority = 5
  DPCR was 0x333B3B33, setting to 0x33353B33
  ... transfer timed out
Testing DMA read with master enable = false, priority = 0
  DPCR was 0x333B3B33, setting to 0x33303B33
  ... transfer timed out
Done.

References