Root Counter Mode Combinations: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first [Root Counter Behavior](/tests/timers2/) test measured the single cases.[^run] | The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first [Root Counter Behavior](/tests/timers2/) test measured the single cases.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | - [DMA Registers and Timer Pulse Mode](/tests/dma-registers-timer-pulse-mode/) | ||
| + | |||
| ## Results | ## Results | ||