Root Counter Mode Combinations

Runs the root counters in every combination of mode bits and records interrupts, flags and bit 10.

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Overview

The program runs each root counter in combinations of mode bits instead of one question at a time. Each row sets one counter in one mode and watches it for a fixed time. The row records the first read of the mode after the write, each I_STAT edge of the counter's interrupt with its time, each change of mode bit 10, how many mode reads saw bits 11 and 12, and the counter and mode at the end.¹

The counter under test is timed by another root counter counting system clock cycles: root counter 2, or root counter 0 when root counter 2 is under test. Each group masks IRQ4 to IRQ6 in I_MASK and polls and acknowledges I_STAT itself with interrupts off. The first Root Counter Behavior test measured the single cases.¹

See also:

• Peripheral Registers and Bus Delays
• DMA Registers and Timer Pulse Mode

Results

Mode Bits 3 to 7

The three counters gave the same results with target 0100h over 140000 system clock cycles. No interrupt occurs unless bit 4 (IRQ at target) or bit 5 (IRQ at FFFFh) is set.²

Without bit 6 (repeat) a counter raises one IRQ and no more. With reset at target 0100h and repeat, root counter 2 raised 542 IRQs in 140000 cycles. That is one IRQ every 258 cycles. Without reset the counter reaches the target once in each 65536-cycle pass.²

In toggle mode (bit 7) an IRQ occurs at every other event. Root counter 0 on the dot clock with target 0040h raised 853 IRQs in pulse mode and 427 in toggle mode in the same time.³

Targets

With reset at target 0 the counter stays at 0, flag 11 is set at every read, and one IRQ occurs. With target FFFFh and reset, flags 11 and 12 are set together: the mode read 1C08h after 70000 cycles.⁴⁵

Writes While Counting

Each counter ran in mode 0058h with target 8000h and was written when it reached about 4000h.⁶

A counter written onto the target is reset at once and sets flag 11. A counter written past the target counts on to FFFFh, wraps to 0 and then reaches the target. A target written below the counter is reached only after the wrap.⁶

Reading the Flags

A halfword read of the mode clears flags 11 and 12, and so do a word read of the mode and a byte read of its upper byte. Reads of the counter or the target leave the flags set. A byte read of the mode's lower byte also leaves them set.⁵

Sync Modes

Counter 1 counting system clock cycles in mode 0058h with sync mode 2 raised 206 IRQs in 600000 cycles. With the sync bits written but sync disabled it raised 2325. In sync mode 3 it raised the first IRQ 456242 cycles after the mode write and then ran freely. Sync modes written with bit 0 clear made no difference: counter 0 raised 2325 IRQs in each.⁷

Interrupt Rules

A one-shot counter that has raised its IRQ raises another after a counter write or a mode write. A target write of the same value or a mode read does not arm it again.⁸

In toggle repeat mode with IRQ at FFFFh only, each counter raised 2 IRQs in 300000 cycles, about 131000 cycles apart, and bit 10 changed 4 times. In pulse repeat mode, back-to-back mode reads saw bit 10 at 0 in about 30 of 2992 reads. No two reads in a row saw it at 0.⁸

Writing bit 10 as 0 with the mode has no effect: it reads 1 at once and no IRQ follows. In toggle repeat mode, an I_STAT bit acknowledged while bit 10 is 0 does not come back until the next event: root counter 2 with target 1000h raised the first IRQ at 4173 cycles and the next at 12389.⁸

Runs

27 September 2026 card-g2

Raw output: 00RUN.txt · 01T0M.txt · 02T1M.txt · 03T2M.txt · 04T0S.txt · 05T1S.txt · 06T2S.txt · 07TTG.txt · 08TWR.txt · 09TRD.txt · 10TSY.txt · 11TIQ.txt

27 September 2026 card-g3

Raw output: 00RUN.txt · 01T0M.txt · 02T1M.txt · 03T2M.txt · 04T0S.txt · 05T1S.txt · 06T2S.txt · 07TTG.txt · 08TWR.txt · 09TRD.txt · 10TSY.txt · 11TIQ.txt

28 September 2026 card-h

Raw output: 00RUN.txt · 01T0M.txt · 02T1M.txt · 03T2M.txt · 04T0S.txt · 05T1S.txt · 06T2S.txt · 07TTG.txt · 08TWR.txt · 09TRD.txt · 10TSY.txt · 11TIQ.txt

References