SPU Noise Flags and Reverb

Reads the SPU registers, the voice 1 capture buffer and the reverb area to measure noise, ADPCM flag bits, key on by voice, the capture level and the reverb engine's writes.

This is an old revision of this page, as edited by RemmyLee at 05:40, 23 October 2026. Edit this revision | Latest revision

Overview

The program asks what the SPU Registers and Envelope test left open. Every row reads a register, the voice 1 capture buffer, or sound RAM through DMA4. Times are system clock cycles counted by root counter 2, and one SPU sample is 768 cycles.¹

Nothing is audible. Main volume stays 0 except in the main volume sweep rows, and every voice volume is 0 except where a row says otherwise. Each of the 13 groups restores the registers it touches, the 32 reverb registers, root counter 2, 1F801014h and DPCR, and keys off every voice before it returns.¹ The SPU registers, ADPCM and reverb pages describe the hardware.

Results

SPUCNT and Register Widths

SPUCNT reads back every value written to it at once and again 3000 cycles later. SPUCNT bits 6 to 13 change nothing in SPUSTAT bits 0 to 10. A 32-bit load from 1F801DACh returns the transfer control register in the low half and SPUSTAT in the high half: it read 08000004h with transfer control 0004h and SPUSTAT 0800h.¹

All 32 reverb registers, vLOUT, vROUT and mBASE hold every value written to them: 0000h, FFFFh, AAAAh, 5555h, 8000h and 0001h each read back unchanged. A 32-bit store to 1DC0h writes the low half to 1DC0h and the high half to 1DC2h.¹

ADPCM Decode

The decode rows (groups 03 to 05) printed 0000h for every sample of the tested block, so they give no decode values. The marker block before it read 30CEh, 619Dh and 6F8Eh at the start of every row.¹

Noise

The noise rate depends on the shift and step in SPUCNT and not on the voice's pitch. At shifts 0 to 5 the level did not change in 256 samples, and at shift 15 it changed every sample at every step.¹

Each step adds a quarter of the step 0 rate, and each shift doubles it. The counts are close to (step + 4) / 2^(17 - shift) changes a sample.¹

Flag Byte

Each row plays one block with the flag byte shown and then a silent block. The repeat address is set to the silent loop at 20000h (4000h) before KON, and the tested block sits at 22000h (4400h).¹

Bit 0 (End) sets ENDX after one block, which took about 17200 cycles at pitch 1000h. With bit 0 alone the voice falls silent, and with bits 0 and 1 (End+Repeat) it keeps its level and jumps to the repeat address. Bit 2 (Loop Start) sets the repeat address to its own block. Bit 1 alone and bits 3 to 7 had no effect on these three readings.¹

KON on a voice whose ENDX bit was set cleared the bit after 853 to 2316 cycles. KOFF, however, leaves ENDX set.¹

Key On by Voice

KON and KOFF take longer on higher voice numbers. Started at a sample boundary, KON took 4421 cycles to the first level change on voice 0 and 4961 on voice 23, and KOFF took 568 on voice 0 and 1156 on voice 23.¹

Started 256 or 512 cycles after the boundary, the KON times ranged from 3948 to 5978 cycles, so the start within the sample also changes the latency.¹

Capture Level

The voice 1 capture buffer holds the sample multiplied by the ADSR level as a signed number. With a loop of one value 7000h, a level of 4000h captured 37C7h and a level of 1234h captured 0FDDh. A level of 8000h captured the negative value 9071h, a level of 0001h captured 0000h, and a level of FFFFh captured FFFFh for every positive sample.¹

Volume Sweep

A linear increase with the phase bit set (9000h to 9053h) moves the volume downward from C000h toward 8000h, and a linear decrease (A000h) from 4000h reaches 0000h. Shift 0 with step 0 reached its end value at the first reading in each direction.¹

Reverb Writes

The reverb area 7F000h to 7FFFFh was filled with known values and the engine ran for 60000 cycles. With vIIR 4000h alone, 339 halfwords changed, and the first changes halved at each step: 0100h, 0080h, 0040h and on to 0000h. With vIIR 8000h the changed values instead alternate in sign and grow: FC00h, 0800h, F000h, 2000h and C000h, up to 7FFFh and 8000h at the limits.¹ With SPUCNT bit 7 off the engine still wrote zeros: 32 halfwords changed with every volume set, and 27 with the all-pass and comb volumes set.¹

Reverb and IRQ9

The reverb engine's writes raise IRQ9. With the IRQ address where mLSAME writes, IRQ9 hit 468 cycles after bit 7 went on, and it hit with bit 7 off as well. An IRQ address where mLAPF2 writes also hit. However, an IRQ address where mLCOMB1 reads never hit with bit 7 on or off, and neither did an address outside the reverb area.¹

With mBASE at 40000h, IRQ address 4000h hit within 338 cycles while 1000h and 7000h did not. With mBASE at 44000h or 60000h, IRQ address 1000h did not hit in 2 million cycles.¹

Runs

Run 5501a-card-g2 on 27 September 2026

Raw output: 00RUN.txt · 01SCN.txt · 02SRR.txt · 03SAD.txt · 04SAS.txt · 05SPI.txt · 06SPM.txt · 07SNO.txt · 08SEF.txt · 09SKV.txt · 10SSW.txt · 11SCL.txt · 12SRV.txt · 13SIR.txt

The output of this run is 53 KB. Its files are listed above and are not shown in full on this page.

Run 5501a-card-g3 on 27 September 2026

Raw output: 00RUN.txt · 01SCN.txt · 02SRR.txt · 03SAD.txt · 04SAS.txt · 05SPI.txt · 06SPM.txt · 07SNO.txt · 08SEF.txt · 09SKV.txt · 10SSW.txt · 11SCL.txt · 12SRV.txt · 13SIR.txt

The output of this run is 53 KB. Its files are listed above and are not shown in full on this page.

Run 5501a-card-h on 28 September 2026

Raw output: 00RUN.txt · 01SCN.txt · 02SRR.txt · 03SAD.txt · 04SAS.txt · 05SPI.txt · 06SPM.txt · 07SNO.txt · 08SEF.txt · 09SKV.txt · 10SSW.txt · 11SCL.txt · 12SRV.txt · 13SIR.txt

The output of this run is 53 KB. Its files are listed above and are not shown in full on this page.

References