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Hardware tests

CPU Loads and BIOS ROM Reads

Measures back-to-back loads, timed loads in a cold cache line, a store during a DMA2 list, COP0 r6, BIOS ROM reads at read delays 0 and 1, cache line fills from the ROM and bus error loads.

CPU Loads and BIOS ROM Reads
MachineSCPH-5501
Programfollowup27 and followup27r

Overview

The first version of the program runs six groups, and the later version runs three others. Each group prints the values the console returned and the cycles it took.12

Table 1: Groups
Tag Version Group
BBR followup27 100 turns of k RAM loads of one word back to back and a NOP, with the third load into a new register, the first load's register or the second's
CFW followup27 A call into a cold cache line, with the timed lhu at word 0 to 3 of the line
IMT followup27 The upper half of I_MASK after a store of 12345678h and a load of a timer register
SLQ followup27 100 turns of a timer read, a RAM sh, k NOPs, a timer read and a RAM lw, alone and during a DMA2 list of 1024 empty nodes
TAR followup27 COP0 r6 around branches, around system calls and after an interrupt taken in a 3-word loop
BRX followup27 Loads from the BIOS ROM at read delays 0 and 1, with nothing, a RAM load or a RAM store before them
BFL followup27r A call into "jr ra; nop" at word 0 to 3 of a line in RAM and in the BIOS ROM through KSEG0
BEX followup27r Loads of BFC80100h and FFFE0140h, which lie outside the BIOS ROM
ISV followup27r Cache isolation: an isolated load and store of a word with other values and addresses

See also:

Results

Back-to-Back Loads

With three loads a turn, the loop took 2,121 cycles with the third load into a new register, 2,215 cycles into the second load's register and 2,314 cycles into the first load's register. Writing the register of the first load therefore cost about 2 cycles a turn and the register of the second about 1 cycle. With 4 to 8 loads a turn, either choice added 59 to 101 cycles over the 100 turns.3

Table 2: Cycles for 100 turns in the first run
k New register First load's register Second load's register
2 1,510 1,510 1,510
3 2,121 2,314 2,215
4 2,729 2,827 2,826
5 3,351 3,440 3,452
6 3,945 4,043 4,043
7 4,567 4,656 4,653
8 5,203 5,266 5,262

Load in a Cold Line

The count was zeroed, a call went into a cold line, and an lhu read the count. An lhu at word 2 or 3 took 33 to 36 cycles, and an lhu at word 0 or 1 took 27 to 31.4

Table 3: Cycles from the count zeroed to its read
Entry lhu at Cold (three runs) Warm
Word 0 Word 0 30, 27, 27 27
Word 1 Word 1 27, 27, 27 27
Word 2 Word 2 34, 34, 34 37
Word 3 Word 3 33, 33, 36 33
Word 0, a NOP Word 1 28, 28, 28 31
Word 1, a NOP Word 2 35, 35, 35 35
Word 2, a NOP Word 3 34, 34, 34 34
Word 0, 2 NOPs Word 2 36, 36, 36 36
Word 0, 3 NOPs Word 3 36, 36, 36 36

Store During a DMA2 List

Alone, the 100 turns took 2,635 to 2,641 cycles with 0 to 2 NOPs after the store, and each further NOP added about 100 cycles, which is one cycle a turn. During the list the time stayed at 4,762 to 4,788 cycles for 0 to 4 NOPs and at 4,883 to 4,903 cycles for 6 to 16 NOPs, and it was 5,845 to 5,852 cycles with 24 NOPs.5

Table 4: Cycles for 100 turns and the sum of B minus A over turns 1 to 99 in the first of two runs
k Alone B minus A alone During the list B minus A during the list
0 2,640 743 4,787 1,002
2 2,635 749 4,788 999
3 2,710 800 4,772 998
4 2,812 909 4,780 997
6 3,001 1,102 4,894 2,218
8 3,191 1,291 4,903 2,249
12 3,590 1,683 4,898 2,309
16 4,026 2,079 4,895 2,307
24 4,796 2,871 5,845 3,260

COP0 r6

COP0 r6 read BFC02BACh when the group started. It kept that value around taken branches and a jump and around the EnterCriticalSection and ExitCriticalSection calls. The 3-word loop at 8010FAC0h then ran twelve times with interrupts on, about 750,000 cycles each, and r6, EPC and Cause were read after each run. In the first run EPC was 8010FAC0h and r6 kept BFC02BACh. In the second run EPC was 8010FAC4h, which is the address of the bne, and r6 changed to 8010FAC0h, which is the bne's target. It read 8010FAC0h in every later run, whichever of the two addresses EPC held.6

BIOS ROM at Read Delays 0 and 1

At read delay 0 every BIOS ROM load returned FFFFFFFFh. At read delay 1 the word at BFC00004h (3508243Fh) read 2C243FFFh and the word at BFC00014h (24080B88h) read 080B8BFFh every time, whatever access came before the load. The word at BFC00000h (3C080013h) read 1C0013FFh, 180013FFh or 3C0013FFh. The register read 0013243Fh before and after the group.7

Line Fill From the BIOS ROM

A call into "jr ra; nop" in RAM took 23 to 32 cycles cold and warm. In the BIOS ROM through KSEG0 the cold call took 68 cycles at every word, close to the 68 to 72 cycles through KSEG1, and the warm call 18 cycles at words 0 to 2. At word 3 the warm call also took 68 cycles.8

Bus Error Loads

A load of BFC80100h and a load of FFFE0140h each raised one exception with Cause 0000001Ch, code 7, and EPC at the load. The destination register read 5A5A5A5Ah afterwards in every case. A save to the memory card just before the load made no difference.9

Cache Isolation

At 8001E924h, with 22222222h stored, the cache word read 00002812h before the step, the isolated load returned 00000000h, and memory held 11111111h afterwards. The output ends after the address of the second case, which is 80021B60h.10

Runs

5 October 2026 followup27

followup27/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
6 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 8001AB88 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8001B6F4 PRId 00000002

followup27/01BBR.txt

===== 01 BBR F27 THIRD LOAD REGISTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of k RAM lw of one word back to back (k 2 to 8), then 1 NOP, cached, warm,
two runs each (row 74; followup15 BBL lw one word 1481 2086 2695 3323 3916 for k 2-6).
third into a new register: 1510/1555 2121/2164 2729/2782 3351/3400 3945/3997 4567/4610 5203/5254
third into the first's: 1510/1545 2314/2354 2827/2868 3440/3483 4043/4090 4656/4701 5266/5313
third into the second's: 1510/1552 2215/2257 2826/2871 3452/3503 4043/4093 4653/4711 5262/5315
Done.

followup27/02CFW.txt

===== 02 CFW F27 COLD LINE LOAD WORD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
measure()'s shape: count zeroed, jalr into one cold line, jr into line B, lhu of the count.
Cold three times (FlushCache before each), then warm (row 79; 05FLN 1 line cold 33).
enter word 0, lhu at word 0: 30 27 27 / warm 27
enter word 1, lhu at word 1: 27 27 27 / warm 27
enter word 2, lhu at word 2: 34 34 34 / warm 37
enter word 3, lhu at word 3: 33 33 36 / warm 33
enter word 0, a NOP, lhu at word 1: 28 28 28 / warm 31
enter word 1, a NOP, lhu at word 2: 35 35 35 / warm 35
enter word 2, a NOP, lhu at word 3: 34 34 34 / warm 34
enter word 0, 2 NOPs, lhu at word 2: 36 36 36 / warm 36
enter word 0, 3 NOPs, lhu at word 3: 36 36 36 / warm 36
Done.

followup27/03IMT.txt

===== 03 IMT F27 IMASK UPPER AFTER TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
I_MASK's upper half after sw 12345678h, lw of a timer register, the read; cold / warm, two
runs each; a as IMU, b and c with marked words after the access (row 57; IMU l 03E0/3C03).
timer 0 counter: a 0000/2610 0000/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 0 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 0 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 counter: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 counter: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
Done.

followup27/04SLQ.txt

===== 04 SLQ F27 STORE WAIT IN A LIST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of: timer read A, RAM sh, k NOPs, timer read B, RAM lw. Alone, then during a list
of 1024 empty nodes (total/node at the end/list done); B - A over turns 1-99 (row 47).
k  0 alone 2640; B-A 7-13 sum 743; L0 4787/428/11057; B-A 10-13 sum 1002;
k  0 alone 2641; B-A 7-13 sum 744; L0 4780/426/11029; B-A 10-13 sum 999;
k  1 alone 2635; B-A 7-13 sum 745; L0 4762/427/11052; B-A 10-13 sum 997;
k  1 alone 2641; B-A 7-13 sum 747; L0 4767/425/11029; B-A 10-13 sum 999;
k  2 alone 2635; B-A 7-13 sum 749; L0 4788/428/11060; B-A 10-13 sum 999;
k  2 alone 2641; B-A 7-13 sum 751; L0 4765/425/11026; B-A 10-13 sum 1000;
k  3 alone 2710; B-A 8-12 sum 800; L0 4772/427/11055; B-A 10-13 sum 998;
k  3 alone 2710; B-A 8-12 sum 802; L0 4775/426/11022; B-A 10-13 sum 1000;
k  4 alone 2812; B-A 9-17 sum 909; L0 4780/428/11046; B-A 10-13 sum 997;
k  4 alone 2811; B-A 9-17 sum 903; L0 4771/425/11027; B-A 10-13 sum 1001;
k  6 alone 3001; B-A 11-17 sum 1102; L0 4894/430/11136; B-A 13-27 sum 2218;
k  6 alone 3005; B-A 11-17 sum 1107; L0 4893/428/11125; B-A 13-27 sum 2204;
k  8 alone 3191; B-A 13-17 sum 1291; L0 4903/430/11156; B-A 13-29 sum 2249;
k  8 alone 3200; B-A 13-17 sum 1295; L0 4888/428/11115; B-A 13-27 sum 2201;
k 12 alone 3590; B-A 17-17 sum 1683; L0 4898/430/11154; B-A 23-29 sum 2309;
k 12 alone 3588; B-A 17-17 sum 1683; L0 4890/428/11119; B-A 23-27 sum 2305;
k 16 alone 4026; B-A 21-21 sum 2079; L0 4895/430/11138; B-A 23-27 sum 2307;
k 16 alone 4009; B-A 21-21 sum 2079; L0 4883/428/11104; B-A 23-26 sum 2301;
k 24 alone 4796; B-A 29-29 sum 2871; L0 5845/522/11153; B-A 29-38 sum 3260;
k 24 alone 4800; B-A 29-29 sum 2871; L0 5852/521/11124; B-A 29-39 sum 3264;
Done.

followup27/05TAR.txt

===== 05 TAR F27 COP0 R6 JUMPDEST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
COP0 r6 (JUMPDEST) (row 78). As the group starts: BFC02BAC; I_MASK 0C040009
Interrupts off, cold then warm: before a taken beq BFC02BAC, after it BFC02BAC, after a j BFC02BAC;
 warm BFC02BAC BFC02BAC BFC02BAC (code at 8010FAC0)
Around EnterCriticalSection (a syscall): BFC02BAC then BFC02BAC; after ExitCriticalSection BFC02BAC
A 3 word loop at 8010FAC0 (nop, bne at +4, addiu in its slot at +8), interrupts on, 250000
turns (about 750000 cycles) each run: r6, EPC, Cause after it, then r6 again 1000 cycles on:
 r6 BFC02BAC EPC 8010FAC0 (+0) Cause 00000000; r6 later BFC02BAC
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause D0000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause D0000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause D0000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC0 (+0) Cause 00000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause D0000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC0 (+0) Cause 00000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC0 (+0) Cause 00000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause 10000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC0 (+0) Cause 00000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC0 (+0) Cause 00000000; r6 later 8010FAC0
 r6 8010FAC0 EPC 8010FAC4 (+4) Cause D0000000; r6 later 8010FAC0
Done.

followup27/06BRX.txt

===== 06 BRX F27 BIOS READ DELAY BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
BIOS lw at read delay 0 and 1 (row 43). BIOS delay as found 0013243F. Each value cold/warm.
P is 00000000h, FFFFFFFFh, 12345678h and the true word, in that order.
Delay 0, BFC00000 (3C080013): nothing between FFFFFFFF/FFFFFFFF
 RAM lw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
 RAM sw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
Delay 0, BFC00004 (3508243F): nothing between FFFFFFFF/FFFFFFFF
 RAM lw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
 RAM sw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
Delay 0, BFC00014 (24080B88): nothing between FFFFFFFF/FFFFFFFF
 RAM lw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
 RAM sw of P: FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF FFFFFFFF/FFFFFFFF
Delay 1, BFC00000 (3C080013): nothing between 1C0013FF/1C0013FF
 RAM lw of P: 3C0013FF/1C0013FF 180013FF/3C0013FF 180013FF/180013FF 1C0013FF/180013FF
 RAM sw of P: 1C0013FF/180013FF 180013FF/180013FF 180013FF/1C0013FF 180013FF/1C0013FF
Delay 1, BFC00004 (3508243F): nothing between 2C243FFF/2C243FFF
 RAM lw of P: 2C243FFF/2C243FFF 2C243FFF/2C243FFF 2C243FFF/2C243FFF 2C243FFF/2C243FFF
 RAM sw of P: 2C243FFF/2C243FFF 2C243FFF/2C243FFF 2C243FFF/2C243FFF 2C243FFF/2C243FFF
Delay 1, BFC00014 (24080B88): nothing between 080B8BFF/080B8BFF
 RAM lw of P: 080B8BFF/080B8BFF 080B8BFF/080B8BFF 080B8BFF/080B8BFF 080B8BFF/080B8BFF
 RAM sw of P: 080B8BFF/080B8BFF 080B8BFF/080B8BFF 080B8BFF/080B8BFF 080B8BFF/080B8BFF
BIOS delay now 0013243F.
Done.

5 October 2026 followup27r

followup27r/00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
3 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 8010B3BC PRId 00000002

followup27r/01BFL.txt

===== 01 BFL F27 BIOS LINE FILL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
One call into "jr ra; nop" at word e of a line: cycles from the count zeroed to its read
after the return (row 28): RAM, then the BIOS ROM through KSEG0.
word 0:
 RAM 8001FA00: cold 26 26 26, warm 26, KSEG1 32
 BIOS: found
 BIOS 9FC006A0: cold 68 68 68, warm 18, KSEG1 72
word 1:
 RAM 8001FA04: cold 25 25 25, warm 29, KSEG1 28
 BIOS: found
 BIOS 9FC01AC4: cold 68 68 68, warm 18, KSEG1 68
word 2:
 RAM 8001FA08: cold 23 23 23, warm 23, KSEG1 28
 BIOS: found
 BIOS 9FC00808: cold 68 68 68, warm 18, KSEG1 68
word 3:
 RAM 8001FA0C: cold 32 32 32, warm 32, KSEG1 28
 BIOS: found
 BIOS 9FC0093C: cold 68 68 68, warm 68, KSEG1 68
Done.

followup27r/02BEX.txt

===== 02 BEX F27 BUS ERROR LOADS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Loads that should raise a bus error (row 93). BIOS delay/size 0013243F.
hook in, no save just before, lw BFC80100: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
a card save just before, lw BFC80100: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
a card save, then the hook in again, lw BFC80100: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
hook in, no save just before, again, lw BFC80100: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
hook in, no save just before, lw FFFE0140: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
a card save just before, lw FFFE0140: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
a card save, then the hook in again, lw FFFE0140: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
hook in, no save just before, again, lw FFFE0140: exceptions 1, cause 7 (Cause 0000001C), EPC 8001F988 (load at 8001F988), flag 1, reg 5A5A5A5A
BIOS delay/size now 0013243F.
Done.

followup27r/03ISV.txt

===== 03 ISV F27 ISOLATE STEP 4 VALUES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Cache isolation step 4 from cached code: the word set to 11111111h, then isolated lw, sw of
the value, lw, sw back (row 14; IS4 read 7FEF0000h after 22222222h).
8001E924, stored 22222222: cache word before 00002812, read 00000000, memory after 11111111
80021B60, stored 00000000:

References

  1. ^ SCPH-5501 output: followup27/00RUN.txt

  2. ^ SCPH-5501 output: followup27r/00RUN.txt

  3. ^ SCPH-5501 output: followup27/01BBR.txt

  4. ^ SCPH-5501 output: followup27/02CFW.txt

  5. ^ SCPH-5501 output: followup27/04SLQ.txt

  6. ^ SCPH-5501 output: followup27/05TAR.txt

  7. ^ SCPH-5501 output: followup27/06BRX.txt

  8. ^ SCPH-5501 output: followup27r/01BFL.txt

  9. ^ SCPH-5501 output: followup27r/02BEX.txt

  10. ^ SCPH-5501 output: followup27r/03ISV.txt

Categories: Hardware tests