GP1 Display Control Commands

Reset, display and DMA commands written to the GP1 port of the GPU.

Summary

GP1 is the control port of the GPU at 0x1F801814. A write to GP1 sends a display control command, and a read returns the status register (GPUSTAT).¹ Each command is one word with the 8-bit command number in the upper bits and a 24-bit parameter in the lower bits. Unlike GP0 commands, GP1 commands go directly to the GPU and do not pass through the command FIFO, so they can be sent even while the FIFO is full.²

GP1(0Ah), GP1(0Ch) to GP1(0Fh) and GP1(21h) to GP1(3Fh) are not used, and GP1(40h) to GP1(FFh) mirror GP1(00h) to GP1(3Fh).³

In libgpu the display state is the DISPENV structure, whose members correspond to the commands as shown in the table. Its members are the display area in the frame buffer (disp), the position on the screen (screen), the interlace flag (isinter) and the 24-bit mode flag (isrgb24).⁴ PutDispEnv() makes a DISPENV the current display environment. Unlike a drawing environment, its settings take effect at once, so the display position can be changed while drawing continues in the background.⁴⁵

GP1(00h) - Reset GPU

GP1(00h) resets the GPU. Its parameter bits are not used and should be 0. The reset has the effect of the following commands:⁶

After the reset GPUSTAT reads 14802000h. GP1(09h) is not affected by the reset. The X1 and Y1 values place the upper left edge of the picture off the visible screen.⁶

Libgpu resets the graphics system with ResetGraph(), which takes a reset level. Every level stops the drawing command in progress, cancels the requests in the queue and enters wait status, and the levels differ in what they preserve:⁷

Level 0 is a complete reset, executed once when the program starts; it initializes the display to 256 x 240 and masks the display. Level 1 cancels drawing only and is used when switching the double buffer. Level 3 is a complete reset that keeps the display and drawing environments and leaves the display unmasked. Consequently, a child process started with Exec() should begin with ResetGraph(3), because a level 0 reset would disturb the screen set up by the parent.⁷

GP1(01h) - Reset Command Buffer

GP1(01h) clears the command FIFO and the CLUT cache. The parameter bits are not used.⁸

GP1(02h) - Acknowledge GPU Interrupt

GP1(02h) clears the interrupt flag in bit 24 of GPUSTAT. GP0(1Fh) sets the flag.⁹

GP1(03h) - Display Enable

GP1(03h) turns the display on or off. Bit 0 is DMSK (0 = on, 1 = off), shown in bit 23 of GPUSTAT; bits 1 to 23 are not used. With the display off the GPU outputs a black picture and still sends sync signals to the television.¹⁰

GP1(04h) - DMA Direction

GP1(04h) selects when the GPU requests DMA. Bits 0 to 1 are the DMA direction. GPUSTAT shows the setting in bits 29 to 30:¹¹

The direction must be set before DMA channel 2 is used. Transfers by software without DMA are possible with any setting, but the setting changes the meaning of GPUSTAT bit 25.¹¹¹²

GP1(05h) - Start of Display Area

GP1(05h) sets the upper left corner of the display area in VRAM. Bits 0 to 9 are the X coordinate in halfwords (0 to 1023), bits 10 to 18 the Y coordinate in lines (0 to 511), and bits 19 to 23 are not used.¹³

In libgpu this is (disp.x, disp.y) of DISPENV. For a double buffer at (0, 0)-(320, 240) and (0, 240)-(320, 480), the display area origin alternates between (0, 240) and (0, 0) while the drawing area uses the other buffer.⁵

GP1(06h) - Horizontal Display Range

GP1(06h) sets where each line of the picture starts and ends on the screen. Both values are 12 bits and count video clock cycles from the horizontal sync:¹⁴

The number of pixels per line is (((X2 - X1) / cycles per pixel) + 2) AND NOT 3. The hardware therefore rounds the width to a multiple of 4 pixels, and for resolutions other than 320 the values may need adjusting to match exactly. The video clock is that of the console region and does not change with the mode that GP1(08h) selects.¹⁴ psx-spx gives the following X1 and X2 for a full-width picture in official games:¹⁴

The screen size does not change the size of a pixel. The GPU sends more or fewer pixels to the screen, and many sets show only part of an enlarged picture.¹⁵ Sony expresses the same idea in the screen member of DISPENV, whose standard coordinates are (0, 0) to (256, 240). A smaller screen area is an underscan and a larger one an overscan, and the pixel size stays the same.⁴

GP1(07h) - Vertical Display Range

GP1(07h) sets the first and last scanline of the picture. Both values count scanlines from the vertical sync:¹⁶

The number of lines is Y2 - Y1, and no rounding is applied. If Y2 is much too large, the GPU stops generating vertical blank interrupts (IRQ0). On most television sets only 224 of 240 NTSC lines are visible, and many PAL games show only 256 lines.¹⁶ psx-spx notes that most NTSC games use X1 = 260h and Y1, Y2 centered on 88h, while PAL games use many different values, and some games change these values to shake the screen.¹⁶¹⁷

For PAL output Sony moves the 240-line NTSC picture down by changing the screen member of DISPENV: screen.y = 8 (that is, (256 - 240)/2) and screen.h = 240, with x and w unchanged.¹⁸

GP1(08h) - Display Mode

GP1(08h) sets the resolution, video standard, color depth and interlace of the display. Its fields are as follows:¹⁹

Interlace must be on for all lines to be seen in 480-line mode. The color depth bit affects only the display, because the drawing commands always draw in 15-bit color. The interlace bit, however, also affects drawing.¹⁹ Bit 7 is the "reverse" setting of older Sony libraries and works only on the v1 arcade GPU.¹⁹

The GPU page lists the screen modes that Sony documents. In DISPENV the width disp.w can be 256, 320, 360, 512 or 640 and the height disp.h 240 or 480; with a height of 480 the display is interlaced whatever the isinter flag says.⁴ Libgpu selects PAL with SetVideoMode(MODE_PAL), and on the DTL-H2000 the DIP switch must also be set.¹⁸

GP1(09h) - Set VRAM Size

GP1(09h) exists only on the v2 GPU. Bit 0 allows Y coordinates from 512 to 1023 (0 = no, wrap to 0 to 511; 1 = yes). On a retail console only the first VRAM chip select is used, so enabling this mode makes textures disappear if GP0(E1h) bit 11 is also set. The v1 GPU uses GP1(20h) instead, whose parameter values are uncertain.²⁰

GP1(10h) - Read GPU Internal Register

GP1(10h) latches an internal register in the GP0 read port, where the CPU can read it at once. Bits 0 to 23 select the register; GP1(11h) to GP1(1Fh) are mirrors. Unlike a VRAM read, a register read does not use GPUSTAT bit 27, so the CPU must not wait for that bit. The latched value stays until another read is requested, and it is not updated when the register changes.²¹

The version index gives a way to detect the GPU type. psx-spx shows a detection routine from Perfect Assassin: it latches index 4 and then index 7, and a result of 2 identifies a v2 GPU. Otherwise it writes GP0(E1h) with bit 12 set and reads GPUSTAT bit 12 to tell the v1 GPU from the v0.²²

References